JP2750256B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP2750256B2
JP2750256B2 JP5025195A JP2519593A JP2750256B2 JP 2750256 B2 JP2750256 B2 JP 2750256B2 JP 5025195 A JP5025195 A JP 5025195A JP 2519593 A JP2519593 A JP 2519593A JP 2750256 B2 JP2750256 B2 JP 2750256B2
Authority
JP
Japan
Prior art keywords
lid
sealing material
weight
metal layer
insulating base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5025195A
Other languages
Japanese (ja)
Other versions
JPH06244297A (en
Inventor
弘二 井苅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP5025195A priority Critical patent/JP2750256B2/en
Publication of JPH06244297A publication Critical patent/JPH06244297A/en
Application granted granted Critical
Publication of JP2750256B2 publication Critical patent/JP2750256B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device.

【0002】[0002]

【従来の技術】従来、半導体素子、特にLSI等の半導
体集積回路素子を収容するための半導体素子収納用パッ
ケージはアルミナセラミックス等の電気絶縁材料から成
り、その上面の略中央部に半導体集積回路素子を収容す
るための凹部を有し、且つ該凹部周辺から外部にかけて
導出されたタングステン、モリブデン、マンガン等の高
融点金属粉末から成るメタライズ配線層を有する絶縁基
体と、半導体集積回路素子を外部電気回路に電気的に接
続するために前記メタライズ配線層に銀ロウ等のロウ材
を介し取着された外部リード端子と、アルミナセラミッ
クス等の電気絶縁材料から成る蓋体とから構成されてお
り、絶縁基体の凹部底面に半導体集積回路素子を接着剤
を介して接着固定し、半導体集積回路素子の各電極とメ
タライズ配線層とをボンディングワイヤを介して電気的
に接続するとともに絶縁基体の上面に蓋体を半田から成
る封止材により接合させ、絶縁基体と蓋体とから成る容
器の内部に半導体集積回路素子を気密に封止することに
よって製品としての半導体装置となる。
2. Description of the Related Art Conventionally, a package for accommodating a semiconductor element, especially a semiconductor integrated circuit element such as an LSI is made of an electrically insulating material such as alumina ceramics, and a semiconductor integrated circuit element is provided substantially at the center of the upper surface thereof. An insulating base having a metallized wiring layer made of a refractory metal powder of tungsten, molybdenum, manganese or the like led out from the periphery of the recess to the outside, and a semiconductor integrated circuit element having an external electric circuit. An external lead terminal attached to the metallized wiring layer via a brazing material such as silver brazing for electrical connection to the metallized wiring layer, and a lid made of an electrically insulating material such as alumina ceramics. The semiconductor integrated circuit device is bonded and fixed to the bottom surface of the concave portion with an adhesive, and each electrode of the semiconductor integrated circuit device and the metallized wiring layer It is electrically connected via bonding wires and the lid is joined to the upper surface of the insulating base with a sealing material made of solder, and the semiconductor integrated circuit element is hermetically sealed inside a container consisting of the insulating base and the lid. By doing so, it becomes a semiconductor device as a product.

【0003】尚、かかる従来の半導体素子収納用パッケ
ージは絶縁基体への蓋体の接合が絶縁基体及び蓋体の相
対向する主面に予め銀ーパラジウムから成る金属層を被
着させておき、絶縁基体と蓋体の各々に被着させた金属
層を半田を介し接合することによって行われている。
In such a conventional package for housing a semiconductor element, a metal layer made of silver-palladium is previously applied to the main surfaces of the insulating substrate and the lid which are opposed to each other by joining the lid to the insulating substrate. It is performed by bonding a metal layer adhered to each of the base and the lid via solder.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージは蓋体等に被着させた
金属層が銀ーパラジウムから成っており、該銀ーパラジ
ウムは表面が酸化され易く、一旦、表面に酸化物膜が形
成されると半田との濡れ性が大きく劣化し、絶縁基体及
び蓋体に被着させた金属層と封止材としての半田との接
合強度が低下し、最終的には蓋体を絶縁基体に強固に接
合させることが困難となる欠点を有していた。
However, in this conventional package for housing a semiconductor element, the metal layer attached to the lid or the like is made of silver-palladium, and the surface of the silver-palladium is easily oxidized. When an oxide film is formed on the surface, the wettability with the solder is greatly deteriorated, and the bonding strength between the metal layer applied to the insulating base and the lid and the solder as a sealing material is reduced, and finally, Has a disadvantage that it is difficult to firmly join the lid to the insulating base.

【0005】また従来の半導体素子収納用パッケージに
おいては絶縁基体に蓋体を接合させる封止材が通常、半
田から成っており、その融点が295℃と高いことから
封止材を介して絶縁基体と蓋体とを接合させる際、封止
材を加熱溶融させるための熱が内部に収容する半導体集
積回路素子に印加されると該熱によって半導体集積回路
素子に熱破壊を生じたり、特性に熱変化を招来させたり
するという欠点も有していた。
In the conventional package for accommodating a semiconductor element, the sealing material for joining the lid to the insulating base is usually made of solder, and its melting point is as high as 295 ° C., so that the insulating base is interposed through the sealing material. When the heat is applied to the semiconductor integrated circuit element housed therein to heat and melt the encapsulant when the cover and the lid are joined, the heat may cause thermal destruction of the semiconductor integrated circuit element, or may cause thermal damage to the characteristics. It also has the disadvantage of causing change.

【0006】[0006]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は絶縁基体に蓋体を封止材を介して強固に
接合させ、絶縁基体と蓋体とから成る容器内部に半導体
集積回路素子を気密に封止して半導体集積回路素子を長
期間にわたり正常、且つ安定に作動させることができる
半導体素子収納用パッケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object the purpose of firmly joining a lid to an insulating base via a sealing material and providing the lid inside a container comprising the insulating base and the lid. An object of the present invention is to provide a package for housing a semiconductor element capable of operating the semiconductor integrated circuit element normally and stably for a long period of time by hermetically sealing the semiconductor integrated circuit element.

【0007】[0007]

【課題を解決するための手段】本発明は絶縁基体と蓋体
とから成り、絶縁基体に被着させた金属層と蓋体に被着
させた金属層とを封止材を介し接合させることによって
内部に半導体素子を気密に封止する半導体素子収納用パ
ッケージであって、前記少なくとも蓋体に被着された金
属層が銀ー白金から成り、且つ封止材が錫2.0 乃至6.0
重量%、ビスマス2.0 乃至10.0重量%、インジウム1.5
重量%未満、銀1.5 重量%未満と残部が鉛の合金から成
ることを特徴とするものである。
SUMMARY OF THE INVENTION The present invention comprises an insulating base and a lid, and joins a metal layer adhered to the insulating base and a metal layer adhered to the lid via a sealing material. A semiconductor element housing package for hermetically sealing a semiconductor element therein, wherein at least the metal layer applied to the lid is made of silver-platinum, and the sealing material is tin 2.0 to 6.0.
Wt%, bismuth 2.0 to 10.0 wt%, indium 1.5
Less than 1.5% by weight of silver and less than 1.5% by weight of silver, with the balance being a lead alloy.

【0008】[0008]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 は本発明の半導体素子収納用パッケージの一実
施例を示し、1 は電気絶縁材料から成る絶縁基体、2 は
同じく電気絶縁材料から成る蓋体である。この絶縁基体
1 と蓋体2 とで半導体集積回路素子4 を収容するための
容器3 が構成される。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base made of an electrically insulating material, and 2 is a lid made of the same electrically insulating material. This insulating substrate
The container 1 for accommodating the semiconductor integrated circuit element 4 is composed of the lid 1 and the lid 2.

【0009】前記絶縁基体1 はその上面中央部に半導体
素子4 を収容するための空所を形成する段状の凹部1aが
設けてあり、該凹部1a底面には半導体集積回路素子4 が
ガラス、樹脂、ロウ材等の接着剤を介して接着固定され
る。
The insulating base 1 is provided with a stepped recess 1a at the center of the upper surface thereof to form a space for accommodating the semiconductor element 4, and the semiconductor integrated circuit element 4 is made of glass, It is bonded and fixed via an adhesive such as resin or brazing material.

【0010】また前記絶縁基体1 には凹部1aの段状周辺
より容器3 の外部にかけて導出する複数個のメタライズ
配線層5 が形成されており、該メタライズ配線層5 の凹
部1a段状周辺部は半導体集積回路素子4 の各電極がボン
ディングワイヤ6 を介して電気的に接続され、また容器
3 の外部に導出された部位には外部電気回路と接続され
る外部リード端子7 が銀ロウ等のロウ材8 を介し取着さ
れる。
A plurality of metallized wiring layers 5 are formed on the insulating base 1 so as to extend from the stepped periphery of the concave portion 1a to the outside of the container 3. The metallized wiring layer 5 has a stepped peripheral portion of the concave portion 1a. Each electrode of the semiconductor integrated circuit device 4 is electrically connected via a bonding wire 6 and
An external lead terminal 7 connected to an external electric circuit is attached to a portion led out of 3 through a brazing material 8 such as silver brazing.

【0011】前記絶縁基体1 は例えば、アルミナセラミ
ックス等の電気絶縁材料から成り、アルミナ(Al 2 O
3 ) 、シリカ(SiO2 ) 、マグネシア(MgO) 、カルシア
(CaO) 等の原料粉末に適当な有機溶剤、溶媒を添加混合
して泥漿状となすとともにこれをドクターブレード法や
カレンダーロール法を採用することによってセラミック
グリーンシート( セラミック生シート) を形成し、しか
る後、前記セラミックグリーンシートに適当な打ち抜き
加工を施すとともに複数枚積層し、高温( 約1600℃) で
焼成することによって製作される。
The insulating substrate 1 is made of, for example, an electrically insulating material such as alumina ceramics, and is made of alumina (Al 2 O).
3 ), silica (SiO 2 ), magnesia (MgO), calcia
An appropriate organic solvent and a suitable organic solvent are added to the raw material powder such as (CaO) to form a slurry by adding and mixing a solvent and forming a ceramic green sheet (ceramic raw sheet) by employing a doctor blade method or a calendar roll method, Thereafter, the ceramic green sheet is manufactured by subjecting the ceramic green sheet to appropriate punching, laminating a plurality of sheets, and firing at a high temperature (about 1600 ° C.).

【0012】また前記メタライズ配線層5 はタングステ
ン、モリブデン、マンガン等の高融点金属粉末から成
り、該タングステン等の高融点金属粉末に適当な有機溶
剤、溶媒を添加混合して得た金属ペーストを絶縁基体1
となるセラミックグリーンシートに予め従来周知のスク
リーン印刷法により所定パターンに印刷塗布しておくこ
とによって絶縁基体1 の凹部1a段状周辺から容器3 の外
部に導出するように被着形成される。
The metallized wiring layer 5 is made of a high melting point metal powder such as tungsten, molybdenum, manganese or the like. The metal paste obtained by adding an appropriate organic solvent or solvent to the high melting point metal powder such as tungsten is mixed. Substrate 1
The ceramic green sheet to be formed is printed and applied in a predetermined pattern by a conventionally well-known screen printing method, so that the ceramic green sheet is adhered and formed so as to be led out of the container 3 from the periphery of the stepped portion 1a of the insulating substrate 1 to the outside.

【0013】尚、前記メタライズ配線層5 はその露出す
る外表面にニッケル、金等の耐蝕性に優れ、且つロウ材
と濡れ性の良い金属をメッキ法により1.0 乃至20.0μm
の厚みに層着させておくとメタライズ配線層5 の酸化腐
食を有効に防止することができるとともにメタライズ配
線層5 とボンディングワイヤ6 との接続及びメタライズ
配線層5 と外部リード端子とのロウ付け取着を極めて強
固なものとなすことができる。従って、メタライズ配線
層5 の酸化腐食を防止し、メタライズ配線層5とボンデ
ィングワイヤ6 との接続及びメタライズ配線層5 と外部
リード端子7 とのロウ付けを強固なものとするにはメタ
ライズ配線層5 の露出外表面にニッケル、金等を1.0 乃
至20.0μm の厚みに層着させておくことが好ましい。
The metallized wiring layer 5 is coated on its exposed outer surface with a metal having excellent corrosion resistance such as nickel and gold and a good wettability with a brazing material by a plating method of 1.0 to 20.0 μm.
The metallized wiring layer 5 can be effectively prevented from being oxidized and corroded, and the connection between the metallized wiring layer 5 and the bonding wires 6 and the brazing between the metallized wiring layer 5 and the external lead terminals can be effectively prevented. The wear can be made very strong. Therefore, in order to prevent the metallized wiring layer 5 from being oxidized and corroded and to make the connection between the metallized wiring layer 5 and the bonding wires 6 and the brazing between the metallized wiring layer 5 and the external lead terminals 7 firm, It is preferable that nickel, gold or the like is layered on the exposed outer surface to a thickness of 1.0 to 20.0 μm.

【0014】更に前記メタライズ配線層5 に銀ロウ等の
ロウ材を介して取着される外部リード端子7 は内部に収
容する半導体集積回路素子4 を外部電気回路に接続する
作用を為し、外部リード端子7 を外部電気回路に接続す
ることによって内部に収容される半導体集積回路素子4
はメタライズ配線層5 及び外部リード端子7 を介し外部
電気回路に電気的に接続されることとなる。
An external lead terminal 7 attached to the metallized wiring layer 5 via a brazing material such as silver brazing serves to connect the semiconductor integrated circuit element 4 housed therein to an external electric circuit. The semiconductor integrated circuit device 4 accommodated therein by connecting the lead terminals 7 to an external electric circuit.
Are electrically connected to an external electric circuit via the metallized wiring layer 5 and the external lead terminals 7.

【0015】前記外部リード端子7 はコバール金属( 鉄
ーニッケルーコバルト合金) や42アロイ( 鉄ーニッケル
合金) 等の金属材料から成り、コバール金属等のインゴ
ット( 塊) を圧延加工法や打ち抜き加工法等、従来周知
の金属加工法を採用することによって所定の形状に形成
される。
The external lead terminals 7 are made of a metal material such as Kovar metal (iron-nickel-cobalt alloy) or 42 alloy (iron-nickel alloy). For example, a predetermined shape is formed by employing a conventionally known metal working method.

【0016】また前記外部リード端子7 はその外表面に
ニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ性の
良い金属をメッキ法により1.0 乃至20.0μm の厚みに層
着させておくと外部リード端子7 の酸化腐食を有効に防
止することができるとともに外部リード端子7 と外部電
気回路との電気的接続を良好となすことができる。その
ため外部リード端子7 はその外表面にニッケル、金等を
1.0 乃至20.0μm の厚みに層着させておくことが好まし
い。
The external lead terminal 7 is preferably formed by plating a metal having excellent corrosion resistance, such as nickel and gold, and a good wettability with a brazing material to a thickness of 1.0 to 20.0 μm on the outer surface thereof by a plating method. The oxidation corrosion of the external lead terminal 7 can be effectively prevented, and the electrical connection between the external lead terminal 7 and the external electric circuit can be made good. Therefore, the external lead terminals 7 should be coated with nickel, gold, etc.
It is preferable to coat the layer to a thickness of 1.0 to 20.0 μm.

【0017】前記絶縁基体1 は更にその上面に金属層9
が被着されており、該金属層9 には蓋体2bが封止材A を
介して接合され、これによって容器3 の内部に半導体集
積回路素子4 が気密に封入される。
The insulating substrate 1 further has a metal layer 9 on its upper surface.
A lid 2b is bonded to the metal layer 9 via a sealing material A, whereby the semiconductor integrated circuit element 4 is hermetically sealed in the container 3.

【0018】前記絶縁基体1 の上面に被着させた金属層
9 は、例えばタングステン、モリブデン、マンガン等の
高融点金属粉末から成り、該高融点金属粉末に有機溶
剤、溶媒を添加混合して得た金属ペーストを絶縁基体1
となるセラミックグリーンシートに従来周知のスクリー
ン印刷法等を採用することによって印刷塗布しておき、
セラミックグリーンシートを高温で焼成し、絶縁基体1
となす際に同時に絶縁基体1 の上面に被着される。
A metal layer deposited on the upper surface of the insulating substrate 1
9 is made of a high melting point metal powder such as tungsten, molybdenum, manganese or the like, and an organic solvent and a solvent obtained by adding and mixing the high melting point metal powder to the insulating base 1
The ceramic green sheet is printed and applied by adopting a conventionally known screen printing method, etc.
The ceramic green sheet is fired at a high temperature,
At the same time, it is adhered to the upper surface of the insulating base 1.

【0019】尚、前記金属層9 の表面には封止材A との
濡れ性を改善するためにニッケルから成る層と金から成
る層が順次層着されている。
A layer made of nickel and a layer made of gold are sequentially formed on the surface of the metal layer 9 in order to improve the wettability with the sealing material A.

【0020】また前記絶縁基体1 の上面に接合される蓋
体2 はアルミナセラミックス等の電気絶縁材料から成
り、その下面外周部に予め金属層10を被着させておき、
該金属層10を絶縁基体1 上面の金属層9 に封止材A を介
し接合させることによって蓋体2 は絶縁基体1 に接合さ
れることとなる。
The lid 2 joined to the upper surface of the insulating base 1 is made of an electrically insulating material such as alumina ceramics, and a metal layer 10 is previously applied to the outer periphery of the lower surface thereof.
By joining the metal layer 10 to the metal layer 9 on the upper surface of the insulating base 1 via the sealing material A, the lid 2 is bonded to the insulating base 1.

【0021】前記蓋体2 は、例えばアルミナ(Al 2 O
3 ) 、シリカ(SiO2 ) 、マグネシア(MgO) 、カルシア
(CaO) 等に適当な有機溶剤、溶媒を添加混合した原料粉
末をプレス型内に充填するとともに一定圧力で押圧して
成形し、しかる後、前記成形品を約1500℃の温度で焼成
することによって製作される。
The lid 2 is made of, for example, alumina (Al 2 O
3 ), silica (SiO 2 ), magnesia (MgO), calcia
(CaO) A suitable organic solvent, a raw material powder obtained by adding and mixing a solvent is filled in a press mold and pressed at a constant pressure to be molded, and then, the molded article is fired at a temperature of about 1500 ° C. Produced by

【0022】また前記蓋体2 の下面外周部に被着される
金属層10は銀80.0乃至98.0重量%、白金2.0 乃至20.0重
量%の銀ー白金から成り、銀と白金の粉末に有機溶剤、
溶媒を添加混合して得た金属ペーストを蓋体2 の下面外
周部に従来周知のスクリーン印刷法等により印刷塗布
し、しかる後、これを高温で焼き付けることによって蓋
体2 の下面外周部に厚み10μm 以上に被着される。
The metal layer 10 attached to the outer periphery of the lower surface of the lid 2 is composed of silver-platinum of 80.0 to 98.0% by weight of silver and 2.0 to 20.0% by weight of platinum.
A metal paste obtained by adding and mixing a solvent is printed and applied to the outer peripheral portion of the lower surface of the lid 2 by a conventionally known screen printing method or the like, and then baked at a high temperature so that the outer peripheral portion of the lower surface of the lid 2 has a thickness. Deposited over 10 μm.

【0023】前記銀ー白金から成る金属層10は、酸化し
難い白金が含まれているため表面に酸化物膜が形成され
ることは殆ど無く、その結果、金属層10と封止材A との
接合強度が強固となり、これによって蓋体2 を絶縁基体
1 に封止材A を介し強固に接合させることが可能とな
る。
Since the metal layer 10 made of silver-platinum contains platinum which is hardly oxidized, almost no oxide film is formed on the surface. As a result, the metal layer 10 and the sealing material A The bonding strength of the
1 can be firmly joined via the sealing material A.

【0024】更に前記絶縁基体1 の上面に蓋体2 を接合
させる封止材A は錫2.0 乃至6.0 重量%とビスマス2.0
乃至10.0重量%とインジウム1.5 重量%未満と銀1.5 重
量%未満と残部が鉛の合金から成り、該封止材A は絶縁
基体1 及び蓋体2 に被着等させた金属層9 、10のいずれ
とも濡れ性が良く、絶縁基体1 上面に蓋体2 を強固に接
合させて容器3 の気密封止を完全となすことができる。
Further, the sealing material A for bonding the lid 2 to the upper surface of the insulating base 1 is composed of 2.0 to 6.0% by weight of tin and 2.0% by weight of bismuth.
To 10.0% by weight, less than 1.5% by weight of indium, less than 1.5% by weight of silver, and the balance of lead, and the sealing material A is made of the metal layers 9 and 10 adhered to the insulating base 1 and the lid 2. Both have good wettability, and the lid 2 can be firmly joined to the upper surface of the insulating base 1 to completely seal the container 3 hermetically.

【0025】前記錫2.0 乃至6.0 重量%とビスマス2.0
乃至10.0重量%とインジウム1.5 重量%未満と銀1.5 重
量%未満と残部が鉛の合金から成る封止材A はまたその
融点が280 ℃と従来の半田に比べ10%程度低く、そのた
め封止材A によって絶縁基体1 と蓋体2 とを接合させる
際、封止材A を加熱溶融させる熱が内部に収容する半導
体集積回路素子4 に印加されたとしても半導体集積回路
素子4 は熱破壊することも、特性に熱変化を招来するこ
ともなく、その結果、半導体集積回路素子4 を長時間に
わたって正常、且つ安定に作動させることが可能とな
る。
The tin 2.0 to 6.0% by weight and bismuth 2.0
The encapsulant A, which is composed of an alloy of about 10.0% by weight, less than 1.5% by weight of indium, less than 1.5% by weight of silver, and less than 1.5% by weight of silver, and the balance being lead, also has a melting point of 280 ° C., which is about 10% lower than conventional solder, When the insulating base 1 and the lid 2 are joined by A, even if heat for heating and melting the sealing material A is applied to the semiconductor integrated circuit element 4 housed therein, the semiconductor integrated circuit element 4 is thermally broken. However, no thermal change is caused in the characteristics, and as a result, the semiconductor integrated circuit element 4 can be operated normally and stably for a long time.

【0026】尚、前記封止材A に含有される錫(Sn)は、
絶縁基体1 及び蓋体2 に被着させた金属層9 、10に対す
る封止材A の濡れ性を改善するための成分であり、その
含有量が2.0 重量%未満であると封止材A と絶縁基体1
及び蓋体2 に被着させた金属層9 、10との接合強度が弱
くなって容器3 の気密封止の信頼性が大幅に劣化してし
まい、また6.0 重量%を越えると封止材A の加熱溶融温
度が高くなって絶縁基体1 と蓋体2 とを接合させる際に
内部に収容する半導体集積回路素子4 に熱破壊等を発生
させてしまう。従って、前記封止材A に含有される錫(S
n)はその含有量が2.0 乃至6.0 重量%の範囲に特定され
る。
The tin (Sn) contained in the sealing material A is
It is a component for improving the wettability of the sealing material A with respect to the metal layers 9 and 10 adhered to the insulating base 1 and the lid 2, and if the content is less than 2.0% by weight, the sealing material A Insulating substrate 1
In addition, the bonding strength between the metal layers 9 and 10 attached to the lid 2 is weakened, and the reliability of the hermetic sealing of the container 3 is greatly deteriorated. When the insulating base 1 and the lid 2 are joined to each other, the heat melting temperature of the semiconductor integrated circuit element 4 becomes high, and the semiconductor integrated circuit element 4 housed therein may cause thermal destruction or the like. Therefore, the tin (S
n) is specified in the range of 2.0 to 6.0% by weight.

【0027】また前記封止材A に含有されるビスマス(B
i)は封止材A の加熱溶融温度を下げる成分であり、その
含有量が2.0 重量%未満であると封止材A の加熱溶融温
度が高くなって絶縁基体1 と蓋体2 とを接合させる際に
内部に収容する半導体集積回路素子4 に熱破壊等を発生
させてしまい、また10.0重量%を越えると封止材A に粒
界が形成されて強度が低下し、絶縁基体1 と蓋体2 とを
強固に接合させることが不可となる。従って、前記封止
材A に含有されるビスマスはその量が2.0 乃至10.0重量
%の範囲に特定される。
The bismuth (B) contained in the sealing material A
i) is a component that lowers the heat-melting temperature of the sealing material A. If the content is less than 2.0% by weight, the heat-melting temperature of the sealing material A increases, and the insulating base 1 and the lid 2 are joined. In this case, the semiconductor integrated circuit element 4 accommodated therein causes thermal destruction and the like. If the content exceeds 10.0% by weight, a grain boundary is formed in the sealing material A, and the strength is reduced. It becomes impossible to firmly join the body 2. Therefore, the amount of bismuth contained in the sealing material A is specified in the range of 2.0 to 10.0% by weight.

【0028】更に前記封止材A に含有されるインジウム
(In)は封止材A の加熱溶融温度を下げる成分であり、そ
の含有量が1.5 重量%を越えると封止材A の酸化を促進
し、封止材A の耐熱衝撃性に劣化を招来するためその含
有量は1.5 重量%未満に特定される。
Further, indium contained in the sealing material A
(In) is a component that lowers the heat melting temperature of the sealing material A. If the content exceeds 1.5% by weight, the oxidation of the sealing material A is accelerated, and the thermal shock resistance of the sealing material A is deteriorated. Content is specified to be less than 1.5% by weight.

【0029】また更に前記封止材A に含有される銀(Ag)
は絶縁基体1 及び蓋体2 に被着させた金属層9 、10に対
する封止材A の濡れ性を改善するとともにその接合強度
を向上させるための成分であり、その含有量が1.5 重量
%を越えると封止材A が蓋体2 に被着させた金属層10に
対し濡れ性が悪くなり、絶縁基体1 上に蓋体2 を封止材
A を介して強固に接合させるのが不可となって容器3 の
気密封止の信頼性が大幅に劣化してしまうためその含有
量は1.5 重量%未満に特定される。
Further, silver (Ag) contained in the sealing material A
Is a component for improving the wettability of the sealing material A with respect to the metal layers 9 and 10 adhered to the insulating base 1 and the lid 2 and for improving the bonding strength. The content is 1.5% by weight. If it exceeds, the sealing material A becomes poor in wettability with respect to the metal layer 10 adhered to the lid 2, and the lid 2 is placed on the insulating substrate 1.
Since it becomes impossible to make a strong connection via A and the reliability of hermetic sealing of the container 3 is greatly deteriorated, its content is specified to be less than 1.5% by weight.

【0030】前記封止材A はまた絶縁基体1 と蓋体2 と
の接合の作業性を容易とするために蓋体2 に被着させた
金属層10に予め接合されており、該封止材A の蓋体2 に
被着させた金属層10への接合は封止材A を構成する合金
粉末に有機溶剤、溶媒を添加混合して得たペーストを蓋
体2 に被着させた金属層10上に従来周知のスクリーン印
刷法により印刷塗布し、しかる後、これを約350 ℃の温
度で焼成して封止材Aを金属層10表面に溶融被着させる
ことによって行われる。
The sealing material A is previously bonded to a metal layer 10 attached to the lid 2 in order to facilitate the workability of bonding between the insulating base 1 and the lid 2. The joining of the material A to the metal layer 10 adhered to the cover 2 is performed by adding a paste obtained by adding an organic solvent and a solvent to the alloy powder constituting the sealing material A and applying the paste to the cover 2. Printing is performed on the layer 10 by a conventionally known screen printing method, and thereafter, the resultant is baked at a temperature of about 350 ° C. to melt-adhere the sealing material A to the surface of the metal layer 10.

【0031】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹部1a底面に半導体集積回路
素子4 を接着剤を介して接着固定するとともに半導体集
積回路素子4 の各電極をメタライズ配線層5 にボンディ
ングワイヤ6 を介して電気的に接続し、しかる後、絶縁
基体1 の上面に蓋体2 を封止材A により接合させ、容器
3 の内部に半導体集積回路素子4 を気密に封入すること
によって製品としての半導体装置が完成する。
Thus, according to the semiconductor device housing package of the present invention, the semiconductor integrated circuit device 4 is bonded and fixed to the bottom surface of the concave portion 1a of the insulating base 1 with an adhesive, and each electrode of the semiconductor integrated circuit device 4 is metallized wiring layer. 5 via a bonding wire 6, and then a lid 2 is joined to the upper surface of the insulating base 1 with a sealing material A,
A semiconductor device as a product is completed by hermetically enclosing the semiconductor integrated circuit element 4 inside 3.

【0032】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば絶縁基体1 の上面に被着
する金属層9 を蓋体2 の下面外周部に被着させた金属層
10と同じ材質で形成してもよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, the metal deposited on the upper surface of the insulating substrate 1 can be modified. Metal layer with layer 9 applied to the outer periphery of the lower surface of lid 2
It may be formed of the same material as 10.

【0033】[0033]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、少なくとも蓋体に被着された金属層を銀ー白金
で形成したことから該金属層の表面に酸化物膜が形成さ
れることは殆ど無く、その結果、蓋体の金属層と封止材
との接合強度が強固となり、これによって蓋体を絶縁基
体に封止材を介し強固に接合させることが可能となる。
According to the package for accommodating a semiconductor element of the present invention, since at least the metal layer attached to the lid is formed of silver-platinum, an oxide film is formed on the surface of the metal layer. As a result, the bonding strength between the metal layer of the lid and the sealing material is increased, and thus the lid can be firmly bonded to the insulating base via the sealing material.

【0034】また封止材を錫2.0 乃至6.0 重量%とビス
マス2.0 乃至10.0重量%とインジウム1.5 重量%未満と
銀1.5 重量%未満と残部が鉛の合金から成る融点が低
く、絶縁基体及び蓋体に被着させた金属層と濡れ性が良
い合金で形成したことから絶縁基体に被着させた金属層
と蓋体に被着させた金属層とを封止材を介して接合させ
る際、封止材を加熱溶融させる熱が内部に収容する半導
体集積回路素子に印加されたとしても半導体集積回路素
子は熱破壊したり、特性に熱変化を招来することは殆ど
なく、その結果、半導体集積回路素子を長期間にわたり
正常、且つ安定に作動させることが可能となる。
The sealing material may be composed of an alloy of tin 2.0 to 6.0% by weight, bismuth 2.0 to 10.0% by weight, indium less than 1.5% by weight, silver less than 1.5% by weight, and the balance of lead. When the metal layer adhered to the insulating base and the metal layer adhered to the lid are joined via a sealing material, the metal Even if heat for heating and melting the stopper material is applied to the semiconductor integrated circuit element housed therein, the semiconductor integrated circuit element hardly causes thermal destruction or changes in characteristics, and as a result, the semiconductor integrated circuit The element can be operated normally and stably for a long period of time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 2・・・・蓋体 3・・・・容器 4・・・・半導体集積回路素子 5・・・・メタライズ配線層 7・・・・外部リード端子 9・・・・絶縁基体に被着させた金属層 10・・・・蓋体に被着させた金属層 A・・・・封止材 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Container 4 ... Semiconductor integrated circuit element 5 ... Metallized wiring layer 7 ... External lead terminal 9 ... Metal layer applied to insulating substrate 10 Metal layer applied to lid A Sealing material

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁基体と蓋体とから成り、絶縁基体に被
着させた金属層と蓋体に被着させた金属層とを封止材を
介し接合させることによって内部に半導体素子を気密に
封止する半導体素子収納用パッケージであって、前記少
なくとも蓋体に被着された金属層が銀ー白金から成り、
且つ封止材が錫2.0 乃至6.0 重量%、ビスマス2.0 乃至
10.0重量%、インジウム1.5 重量%未満、銀1.5 重量%
未満と残部が鉛の合金から成ることを特徴とする半導体
素子収納用パッケージ。
The semiconductor element is hermetically sealed by joining a metal layer adhered to the insulating substrate and a metal layer adhered to the lid via a sealing material. A semiconductor element storage package to be sealed in, wherein the metal layer applied to at least the lid is made of silver-platinum,
And the sealing material is tin 2.0 to 6.0% by weight, bismuth 2.0 to
10.0% by weight, indium less than 1.5% by weight, silver 1.5% by weight
A package for accommodating a semiconductor element, wherein less than and the remainder are made of a lead alloy.
JP5025195A 1993-02-15 1993-02-15 Package for storing semiconductor elements Expired - Fee Related JP2750256B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5025195A JP2750256B2 (en) 1993-02-15 1993-02-15 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5025195A JP2750256B2 (en) 1993-02-15 1993-02-15 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH06244297A JPH06244297A (en) 1994-09-02
JP2750256B2 true JP2750256B2 (en) 1998-05-13

Family

ID=12159185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5025195A Expired - Fee Related JP2750256B2 (en) 1993-02-15 1993-02-15 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2750256B2 (en)

Also Published As

Publication number Publication date
JPH06244297A (en) 1994-09-02

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