JPH1154695A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1154695A
JPH1154695A JP20653397A JP20653397A JPH1154695A JP H1154695 A JPH1154695 A JP H1154695A JP 20653397 A JP20653397 A JP 20653397A JP 20653397 A JP20653397 A JP 20653397A JP H1154695 A JPH1154695 A JP H1154695A
Authority
JP
Japan
Prior art keywords
semiconductor chip
solder
chip
semiconductor
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20653397A
Other languages
Japanese (ja)
Other versions
JP3545171B2 (en
Inventor
Hideo Kunii
秀雄 国井
Makoto Tsubonoya
誠 坪野谷
Eiichi Kobayashi
栄一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP20653397A priority Critical patent/JP3545171B2/en
Publication of JPH1154695A publication Critical patent/JPH1154695A/en
Application granted granted Critical
Publication of JP3545171B2 publication Critical patent/JP3545171B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PROBLEM TO BE SOLVED: To easily constitute a semiconductor device in a face-down two-storied structure, by fixing a second semiconductor chip on a first semiconductor chip in a face-down state, by soldering and using solder having a melting point which is higher than that of the solder used on the first semiconductor chip side on the second semiconductor chip side. SOLUTION: A first semiconductor chip 50 is die-bonded onto the island 55 of a lead frame with an adhesive insulating material 56, and a second semiconductor chip 51 is fixed on the first chip 50 in such a face-down state that the second chip 51 is faced oppositely to the first chip 50 and electrically connected to the first chip 50 through solder bumps 53 and 54. The solder bumps 54 on the second chip 51 are formed by using solder having a melting point which is higher than that of the solder bumps 53 used on the first chip 50 side, so that the solder bumps 54 may not fall down by melting. Therefore, a semiconductor device can be constituted easily in a face-down two-storied structure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、外形寸法の薄型化
が可能な半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device whose external dimensions can be reduced.

【０００２】[0002]

【従来の技術】半導体装置の封止技術として最も普及し
ているのが、半導体チップの周囲を熱硬化性のエポキシ
樹脂で封止するトランスファーモールド技術である。半
導体チップの支持素材としてリードフレームを用いてお
り、リードフレームのアイランドに半導体チップをダイ
ボンドし、半導体チップのボンディングパッドとリード
をワイヤでワイヤボンドし、所望の外形形状を具備する
金型内にリードフレームをセットし、金型内にエポキシ
樹脂を注入、これを硬化させることにより製造される。2. Description of the Related Art A transfer molding technique for sealing the periphery of a semiconductor chip with a thermosetting epoxy resin is most widely used as a sealing technique for a semiconductor device. A lead frame is used as a support material for the semiconductor chip, the semiconductor chip is die-bonded to the island of the lead frame, the bonding pads of the semiconductor chip and the leads are wire-bonded with wires, and the leads are placed in a mold having a desired external shape. It is manufactured by setting a frame, injecting an epoxy resin into a mold, and curing the epoxy resin.

【０００３】一方、各種電子機器に対する小型、軽量化
の波はとどまるところを知らず、これらに組み込まれる
半導体装置にも、一層の大容量、高機能、高集積化が望
まれている。そこで、以前から発想としては存在してい
た（例えば、特開昭５５ー１１１１５１７号）、１つの
パッケージ内に複数の半導体チップを封止する技術が注
目され、実現化する動きが出てきた。つまり、アイラン
ド上に第１の半導体チップを固着し、第１の半導体チッ
プの上に第２の半導体チップを固着し、対応するボンデ
ィングパッドとリードとをボンディングワイヤで接続
し、樹脂で封止したものである。On the other hand, the wave of miniaturization and weight reduction of various electronic devices is unavoidable, and semiconductor devices incorporated therein are desired to have higher capacity, higher function, and higher integration. Therefore, a technique for sealing a plurality of semiconductor chips in a single package, which has existed as an idea (for example, Japanese Patent Application Laid-Open No. 55-1111517), has been attracting attention, and a move toward realization has emerged. That is, the first semiconductor chip was fixed on the island, the second semiconductor chip was fixed on the first semiconductor chip, the corresponding bonding pads and leads were connected by bonding wires, and sealed with resin. Things.

【０００４】[0004]

【課題を解決するための手段】この構造は、コストアッ
プになるにも拘わらず、複数のチップを一体化させるこ
とにより、軽薄短小化が実現できるものである。しかし
ながら、半導体チップには、その表面に形成した回路素
子の支持基板としてある程度の機械的強度を持たせる必
要性から、最低でも約２００μ程度の厚みが必須とな
り、樹脂には、半導体装置の耐湿性の点、およびボンデ
ィングワイヤのループ高さ等の点で、半導体チップの上
方に最低でも約２００μ程度の肉厚を確保したい。これ
ら製造上から要求される厚みを全て取り込み、且つ２つ
以上のチップを重ね合わせることは、結局樹脂の外形寸
法を大型化させることになり、従来より準備されている
パッケージの外形寸法に収まらないと言う欠点があっ
た。This structure can realize a reduction in weight and thickness by integrating a plurality of chips, despite the increase in cost. However, since a semiconductor chip needs to have a certain mechanical strength as a support substrate for a circuit element formed on the surface thereof, a thickness of at least about 200 μ is indispensable. It is desirable to secure a thickness of at least about 200 μ above the semiconductor chip in terms of the above point and the loop height of the bonding wire. Incorporating all of the required thicknesses from the manufacturing perspective and overlapping two or more chips eventually increases the outer dimensions of the resin and does not fit into the outer dimensions of the conventionally prepared package. There was a drawback to say.

【０００５】[0005]

【課題を解決するための手段】本発明は、前述の課題に
鑑みてなされ、第１に、第２の半導体チップを、第１の
半導体チップの上にフェイスダウンで半田固着し、前記
第２の半導体チップ側の半田を第１の半導体チップ側の
半田よりも高融点にすることで解決するものである。ワ
イヤボンドする必要が無くなるために、金属細線に必要
な高さまで樹脂厚を要求されない。従ってその分樹脂の
厚みを薄くでき、且つフェイスダウンする側のチップに
形成された半田ボールを高融点にすることで、半田溶融
時、半田ボールが落下せずに済む。そのため、簡単にフ
ェイスダウンの２階建て構造が実現できる。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and firstly, a second semiconductor chip is soldered face-down on the first semiconductor chip by the face-down soldering method. The problem is solved by making the solder on the semiconductor chip side higher in melting point than the solder on the first semiconductor chip side. Since the need for wire bonding is eliminated, the resin thickness is not required to the height required for the fine metal wires. Accordingly, the thickness of the resin can be reduced accordingly, and the solder ball formed on the chip on the face-down side has a high melting point, so that the solder ball does not fall when the solder is melted. Therefore, a face-down two-story structure can be easily realized.

【０００６】第２として、第２の半導体チップを、第１
の半導体チップの上にフェイスダウンで半田固着し、第
２の半導体チップ側の半田は、第１の半導体チップ側の
半田よりも高融点とし、第２の半導体チップが前記第１
の半導体チップよりも外側に突出して非重畳部を形成
し、この突出した非重畳部に対応する第２の半導体チッ
プの裏面と当接し、前記第２の半導体チップを支持する
第１の支持リードを設けることで解決するものである。
第１の課題で述べた効果以外に、リードフレームのアイ
ランドを省略しているため、更に封止樹脂の厚みを減ら
すことができる。Second, the second semiconductor chip is replaced with the first semiconductor chip.
The second semiconductor chip has a higher melting point than the first semiconductor chip, and the second semiconductor chip has a higher melting point than the first semiconductor chip.
Forming a non-overlapping portion protruding outside of the semiconductor chip of the first semiconductor chip, and contacting the back surface of the second semiconductor chip corresponding to the protruding non-overlapping portion to support the second semiconductor chip. This can be solved by providing
In addition to the effect described in the first problem, since the lead frame island is omitted, the thickness of the sealing resin can be further reduced.

【０００７】[0007]

【発明の実施の形態】以下に本発明の一実施の形態を図
１（図２のＡ−Ａ断面図）および図２を参照して詳細に
説明する。図中、５０、５１は各々第１と第２の半導体
チップを示している。第１と第２の半導体チップ５０、
５１のシリコン表面には、前工程において各種の能動、
受動回路素子が形成され、更に第１の半導体チップ５０
の周辺部分に外部接続用のボンディングパッド５２が形
成されている。そのボンディングパッド５２を被覆する
ようにシリコン窒化膜、シリコン酸化膜、ポリイミド系
絶縁膜などのパッシベーション皮膜が形成され、ボンデ
ィングパッド５２の上部は電気接続のために開口されて
いる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIG. 1 (sectional view taken along the line AA in FIG. 2) and FIG. In the figure, reference numerals 50 and 51 denote first and second semiconductor chips, respectively. First and second semiconductor chips 50,
On the silicon surface of 51, various active,
A passive circuit element is formed, and the first semiconductor chip 50
Bonding pads 52 for external connection are formed in the peripheral portion of. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide-based insulating film is formed so as to cover the bonding pad 52, and an upper portion of the bonding pad 52 is opened for electrical connection.

【０００８】また半田バンプ５３、５４が形成されてい
る。例えば第１の半導体チップ５０（一層メタル製品）
に於いて、第１層目のＡｌ電極は、半導体層表面に形成
された熱酸化やＣＶＤによるシリコン酸化膜の上に配置
され、更に全面にグラス膜、シリコン窒化膜、シリコン
酸化膜、ＴＥＯＳ膜またはＰＩＸ等の第２層目の絶縁膜
（パシベーション被膜）が形成されている。またこの第
２層目の絶縁膜がエッチングされ、前記第１層目のＡｌ
電極（第２の半導体チップとの接続が必要な部分）が露
出され、ここには少なくとも表面が半田接続可能なバリ
アメタルが形成され、この上に半田バンプ５３形成され
ている。二層メタル製品では、第２層目のＡｌ電極の上
に前記パシベーション膜が形成され、この開口部から露
出された部分に半田バンプが形成されている。Further, solder bumps 53 and 54 are formed. For example, the first semiconductor chip 50 (one-layer metal product)
In the above, the first layer Al electrode is disposed on a silicon oxide film formed on the surface of the semiconductor layer by thermal oxidation or CVD, and a glass film, a silicon nitride film, a silicon oxide film, and a TEOS film are further formed on the entire surface. Alternatively, a second insulating film (passivation film) such as PIX is formed. The second insulating film is etched, and the first Al film is etched.
Electrodes (portions that need to be connected to the second semiconductor chip) are exposed, and at least a surface thereof is formed with a barrier metal that can be soldered, and a solder bump 53 is formed thereon. In the case of a two-layer metal product, the passivation film is formed on the second-layer Al electrode, and a solder bump is formed on a portion exposed from the opening.

【０００９】第２の半導体チップ５１でも同様に、第１
の半導体チップと電気的接続が必要な部分に前述したよ
うな構造で半田バンプ５４が形成されている。前記第１
の半導体チップ５０はリードフレームのアイランド５５
上に接着性絶縁材料５６によりダイボンドされ、更に第
２の半導体チップ５１は第１の半導体チップ５０と面対
向されて前記半田バンプ５３、５４を介して接続されて
いる。In the second semiconductor chip 51, the first
Solder bumps 54 are formed in portions that need to be electrically connected to the semiconductor chip with the above-described structure. The first
Semiconductor chip 50 is a lead frame island 55
The semiconductor chip 51 is die-bonded thereon with an adhesive insulating material 56, and the second semiconductor chip 51 is connected to the first semiconductor chip 50 via the solder bumps 53 and 54 so as to face the first semiconductor chip 50.

【００１０】半導体チップ５０の周囲のボンディングパ
ッド５７には、金線等のボンディングワイヤ５８の一端
がワイヤボンドされており、ボンディングワイヤ５８の
他端は外部導出用のリード端子５９の先端部にワイヤボ
ンドされている。これで、各々のボンディングパッド５
７と各リード５９とを電気的に接続している。半導体チ
ップ５０、５１、リード端子５９の先端部、およびワイ
ヤ５８を含む主要部は、周囲をエポキシ系の熱硬化樹脂
６０でモールドされ、パッケージ化される。リード端子
５９は、パッケージ側壁から外部に導出される。また樹
脂６０の外部に導出されたリード端子５９は一端下方に
曲げられ、再度曲げられてＺ字型にフォーミングされて
いる。このフォーミング形状は、リード端子５９の裏面
側固着部分をプリント基板に形成した導電パターンに対
向接着する、表面実装用途の為の形状である。One end of a bonding wire 58 such as a gold wire is wire-bonded to a bonding pad 57 around the semiconductor chip 50, and the other end of the bonding wire 58 is connected to the tip of a lead terminal 59 for external lead-out. Bonded. Thus, each bonding pad 5
7 and each lead 59 are electrically connected. The main parts including the semiconductor chips 50 and 51, the tip of the lead terminal 59, and the wire 58 are molded around the periphery with an epoxy-based thermosetting resin 60 and packaged. The lead terminal 59 is led out from the side wall of the package. The lead terminal 59 led out of the resin 60 is bent downward at one end, bent again, and formed into a Z-shape. This forming shape is a shape for surface mounting use in which the fixed portion on the back side of the lead terminal 59 is opposed to the conductive pattern formed on the printed circuit board.

【００１１】本発明の特徴は、前記半田バンプにある。
つまり第１の半導体チップ５０が固着されたアイランド
５５を加熱して半田バンプを接続するが、第２の半田バ
ンプ５４の融点が第１の半田バンプよりも高いため、融
けて半田の自重により落下することが無くなる。例え
ば、半田リフローに於いて、第１の半田バンプ融点と第
２の半田バンプ融点の間の温度に加熱することで、両者
の半田バンプ接触部は融けて接続される。A feature of the present invention resides in the solder bump.
That is, the island 55 to which the first semiconductor chip 50 is fixed is heated to connect the solder bumps. However, the melting point of the second solder bumps 54 is higher than that of the first solder bumps. Will not be done. For example, in solder reflow, by heating to a temperature between the first solder bump melting point and the second solder bump melting point, the two solder bump contact portions are melted and connected.

【００１２】従って２つのチップの間をワイヤーで接続
する必要が無くなるので、封止樹脂６０の高さを低減で
きる。続いて第２の実施の形態について図３および図４
について説明する。図中、８０、８１は各々第１と第２
の半導体チップを示している。第１の半導体チップ８０
のシリコン表面には、前工程において各種の能動、受動
回路素子が形成され、更にはチップの周辺部分に外部接
続用のボンディングパッド８２が形成されている。その
ボンディングパッド８２を被覆するようにシリコン窒化
膜、シリコン酸化膜、ポリイミド系絶縁膜などのパッシ
ベーション皮膜が形成され、ボンディングパッド８２の
上部は電気接続のために開口されている。Therefore, it is not necessary to connect the two chips with a wire, so that the height of the sealing resin 60 can be reduced. 3 and 4 for the second embodiment.
Will be described. In the figure, 80 and 81 are the first and second, respectively.
1 shows a semiconductor chip. First semiconductor chip 80
On the silicon surface, various active and passive circuit elements are formed in the previous process, and further, bonding pads 82 for external connection are formed on the periphery of the chip. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide-based insulating film is formed so as to cover the bonding pad 82, and an upper portion of the bonding pad 82 is opened for electrical connection.

【００１３】第２の半導体チップ８１は第１の半導体チ
ップ８０と半田バンプ８３、８４を介して固着されてい
る。ここで第１の半導体チップ８０と第２の半導体チッ
プ８１は、そのサイズが異なり、少なくとも第２の半導
体チップ８１の左右の側辺が第１の半導体チップ８０の
側辺から突出し、非重畳部を形成している。つまり第２
の半導体チップ８１の左右の側辺およびその近傍に対応
する裏面は、第１の半導体チップ８０が存在せず空間と
なっている。The second semiconductor chip 81 is fixed to the first semiconductor chip 80 via solder bumps 83 and 84. Here, the first semiconductor chip 80 and the second semiconductor chip 81 are different in size, and at least the left and right sides of the second semiconductor chip 81 project from the sides of the first semiconductor chip 80, and the non-overlapping portion Is formed. That is, the second
The left and right sides of the semiconductor chip 81 and the back surface corresponding to the vicinity thereof are spaces without the first semiconductor chip 80.

【００１４】本発明の特徴は、前述同様に半田バンプに
ある。つまり第１の半導体チップ８０を加熱して半田バ
ンプを接続するが、第２の半田バンプ８４の融点が第１
の半田パンプ８３よりも高いため、融けて半田の自重に
より落下することが無くなる。例えば半田リフローに於
いて、第１の半田バンプ融点と第２の半田バンプ融点の
間に加熱することで、両者の半田バンプ接触部は、共晶
して融けて接続される。The feature of the present invention resides in the solder bump as described above. That is, the first semiconductor chip 80 is heated to connect the solder bumps.
Is lower than the solder pump 83, so that the solder does not melt and drop due to its own weight. For example, in solder reflow, by heating between the melting point of the first solder bump and the melting point of the second solder bump, both solder bump contact portions are eutectically melted and connected.

【００１５】また第２の特徴として、前記非重畳部であ
る空間に支持リード８５を配置し、この支持リードをア
イランド代わりに使用し、アイランドの分だけ封止樹脂
厚を低減している所にある。具体的には先ず、第２の半
導体チップ８１の左右の側辺、特に４つの角部の近傍に
位置する領域に、第１の支持リード８５を配置すること
である。A second feature is that a support lead 85 is arranged in a space which is the non-overlapping portion, and this support lead is used instead of an island, and the sealing resin thickness is reduced by the amount of the island. is there. Specifically, first, the first support leads 85 are arranged on the left and right sides of the second semiconductor chip 81, particularly in the region located near the four corners.

【００１６】ここで支持リードは、２階建ての半導体チ
ップが支えられれば良く、左右に１本づつでもよいし、
一方の側辺に２本他方の側辺に１本の３本で支えても良
い。また本願では４本であるが、それ以上で支えても良
い。また支持リードと第２の半導体チップ８１裏面と
は、相互の固着を考慮して接着剤が塗布されている。し
かし塗布されなくても良い。支持リードは、単にチップ
を支えていれば良く、ボンディング時にも２階建てのチ
ップは、ボンダーの治具で支えることが可能であるから
である。またワイヤーボンディングが終了すれば、チッ
プはワイヤーでも支えられることになる。Here, the support leads need only support a two-story semiconductor chip, and may be one on each side.
It may be supported by two on one side and three by one on the other side. In the present application, the number is four, but more than four may be supported. An adhesive is applied to the support leads and the back surface of the second semiconductor chip 81 in consideration of mutual fixation. However, it may not be applied. This is because the support leads need only support the chip, and the two-story chip can be supported by the bonder jig even during bonding. When the wire bonding is completed, the chip can be supported by wires.

【００１７】支持リードは、非重畳部に位置する第２の
半導体チップ８１の裏面に延在されているので、別途ア
イランドを設けなくともすむ。また支持リードの厚みを
第１の半導体チップ５０の厚みと同じか、それよりも薄
く形成することで、支持リードが封止樹脂から露出され
るのを防止できる。つづいて半導体チップ８０、８１表
面のボンディングパッド８２には、金線等のボンディン
グワイヤ８６の一端がワイヤボンドされており、ボンデ
ィングワイヤ８６の他端は外部導出用のリード端子８７
の先端部にワイヤボンドされている。これで、各々のボ
ンディングパッド８２と各リード８７とを電気的に接続
している。Since the support leads extend on the back surface of the second semiconductor chip 81 located at the non-overlapping portion, there is no need to provide an additional island. In addition, by forming the thickness of the support lead to be equal to or smaller than the thickness of the first semiconductor chip 50, it is possible to prevent the support lead from being exposed from the sealing resin. Subsequently, one end of a bonding wire 86 such as a gold wire is wire-bonded to the bonding pad 82 on the surface of the semiconductor chips 80 and 81, and the other end of the bonding wire 86 is connected to an external lead terminal 87.
Is wire-bonded to the tip. Thus, each bonding pad 82 and each lead 87 are electrically connected.

【００１８】半導体チップ８０、８１、リード端子の先
端部８７、およびワイヤ８６を含む主要部は、周囲をエ
ポキシ系の熱硬化樹脂８８でモールドされ、パッケージ
化される。The main parts including the semiconductor chips 80 and 81, the leading end portions 87 of the lead terminals, and the wires 86 are molded around with an epoxy-based thermosetting resin 88 and packaged.

【００１９】[0019]

【発明の効果】以上に説明した通り、本発明によれば、
第１に、第２の半導体チップを半田ボールを用いたフェ
イスダウン構造で接続して、封止樹脂厚を低減する構造
に於いて、第２の半導体チップの半田ボールを高融点に
することで、第１の半導体チップへの半田落下を防止す
ることができる。従って歩留まりの向上された封止樹脂
厚の薄いパッケージが実現できる。As described above, according to the present invention,
First, in a structure in which the second semiconductor chip is connected by a face-down structure using solder balls to reduce the thickness of the sealing resin, the solder balls of the second semiconductor chip are made to have a high melting point. In addition, it is possible to prevent the solder from falling onto the first semiconductor chip. Therefore, a package having a reduced thickness of the sealing resin with improved yield can be realized.

【００２０】第２に、突出した非重畳部に対応する第２
の半導体チップの裏面に第１の支持リードを当接させ、
２階建てのチップをこの支持リードで支持することによ
り、第２の半導体チップを支持でき、従来用いていたア
イランドを省略することができる。そのため半田ボール
を使用すること、支持リードを使用してアイランドの厚
み分を減らせ、パッケージの厚みを更に薄くすることが
できる。Second, the second portion corresponding to the protruding non-overlapping portion
The first support lead is brought into contact with the back surface of the semiconductor chip of
By supporting the two-story chip with the support leads, the second semiconductor chip can be supported, and the conventionally used island can be omitted. Therefore, the use of solder balls and the use of support leads can reduce the thickness of the island and further reduce the thickness of the package.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態を説明するための半
導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device for describing a first embodiment of the present invention.

【図２】図１に対応した平面図である。FIG. 2 is a plan view corresponding to FIG.

【図３】本発明の第２の実施の形態を説明するための半
導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device for explaining a second embodiment of the present invention.

【図４】図３に対応した平面図である。FIG. 4 is a plan view corresponding to FIG.

【図５】従来例を説明するための平面図である。FIG. 5 is a plan view for explaining a conventional example.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 アイランド上に固着された第１の半導体
チップと、 前記第１の半導体チップの上に固着された第２の半導体
チップと、 前記第１の半導体チップまたは前記第２の半導体チップ
の周囲にその一端が延在されたリードと、 前記リードと前記半導体チップとを電気的に接続する接
続手段と、 前記第１の半導体チップ、第２の半導体チップ、リード
および接続手段を封止する樹脂とを備え、 前記第２の半導体チップは、前記第１の半導体チップの
上にフェイスダウンで半田固着され、前記第２の半導体
チップ側の半田は、第１の半導体チップ側の半田よりも
高融点の半田が用いられていることを特徴とした半導体
装置。A first semiconductor chip fixed on the island; a second semiconductor chip fixed on the first semiconductor chip; the first semiconductor chip or the second semiconductor chip A lead extending at one end around the periphery of the lead, connecting means for electrically connecting the lead and the semiconductor chip, and sealing the first semiconductor chip, the second semiconductor chip, the lead and the connecting means. The second semiconductor chip is solder-fixed face-down on the first semiconductor chip, and the solder on the second semiconductor chip side is smaller than the solder on the first semiconductor chip side. A semiconductor device characterized by using a high melting point solder. 【請求項２】 第１の半導体チップと、 この第１の半導体チップの上に固着された第２の半導体
チップと、 少なくとも前記第１の半導体チップの相対向する一方の
側辺対の近傍まで延在されるリードと、 前記リードと前記第１の半導体チップを電気的に接続す
る接続手段と、 前記第１の半導体チップ、第２の半導体チップ、リード
および接続手段を封止する樹脂とを備え、 前記第２の半導体チップは、前記第１の半導体チップの
上にフェイスダウンで半田固着され、前記第２の半導体
チップ側の半田は、第１の半導体チップ側の半田よりも
高融点の半田が用いられ、他方の側辺対に対応する位置
には、前記第２の半導体チップが前記第１の半導体チッ
プよりも外側に突出して非重畳部を形成し、この突出し
た非重畳部に対応する第２の半導体チップの裏面と当接
し、前記第２の半導体チップを支持する第１の支持リー
ドが設けられていることを特徴とした半導体装置。2. A first semiconductor chip, a second semiconductor chip fixed on the first semiconductor chip, and at least up to the vicinity of one of the opposed side pairs of the first semiconductor chip. Extending leads, connecting means for electrically connecting the leads and the first semiconductor chip, and resin for sealing the first semiconductor chip, the second semiconductor chip, the leads and the connecting means. Wherein the second semiconductor chip is solder-fixed face-down on the first semiconductor chip, and the solder on the second semiconductor chip has a higher melting point than the solder on the first semiconductor chip. At the position corresponding to the other side pair, the second semiconductor chip projects outside the first semiconductor chip to form a non-overlapping portion, and a non-overlapping portion is formed at the position corresponding to the other side pair. Corresponding second semi-conductor Contact with the rear surface of the chip those, semiconductor device, characterized in that the first supporting leads for supporting the second semiconductor chip is provided.
JP20653397A 1997-07-31 1997-07-31 Semiconductor device Expired - Fee Related JP3545171B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20653397A JP3545171B2 (en) 1997-07-31 1997-07-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20653397A JP3545171B2 (en) 1997-07-31 1997-07-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH1154695A true JPH1154695A (en) 1999-02-26
JP3545171B2 JP3545171B2 (en) 2004-07-21

Family

ID=16524953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20653397A Expired - Fee Related JP3545171B2 (en) 1997-07-31 1997-07-31 Semiconductor device

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Country Link
JP (1) JP3545171B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552419B2 (en) 2001-01-25 2003-04-22 Sharp Kabushiki Kaisha Semiconductor device and liquid crystal module using the same
GB2382217A (en) * 2001-07-20 2003-05-21 Carsem Semiconductor Sdn Bhd Flip-chip on lead frame
WO2004057668A3 (en) * 2002-12-20 2004-08-12 Koninkl Philips Electronics Nv Electronic device and method of manufacturing same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552419B2 (en) 2001-01-25 2003-04-22 Sharp Kabushiki Kaisha Semiconductor device and liquid crystal module using the same
GB2382217A (en) * 2001-07-20 2003-05-21 Carsem Semiconductor Sdn Bhd Flip-chip on lead frame
WO2004057668A3 (en) * 2002-12-20 2004-08-12 Koninkl Philips Electronics Nv Electronic device and method of manufacturing same
CN100382298C (en) * 2002-12-20 2008-04-16 Nxp股份有限公司 Electronic device and method of manufacturing same

Also Published As

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