JPS6025900Y2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6025900Y2 JPS6025900Y2 JP17332480U JP17332480U JPS6025900Y2 JP S6025900 Y2 JPS6025900 Y2 JP S6025900Y2 JP 17332480 U JP17332480 U JP 17332480U JP 17332480 U JP17332480 U JP 17332480U JP S6025900 Y2 JPS6025900 Y2 JP S6025900Y2
- Authority
- JP
- Japan
- Prior art keywords
- metallized layer
- semiconductor element
- stem
- fixed
- brazing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置に関し、特にステム等の基体上への
半導体素子の固着構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure for fixing a semiconductor element onto a base such as a stem.
トランシタ・ダイオード等の半導体装置の製作にあたっ
ては、銅、鉄−ニッケル合金あるいはコバール等の金属
から構成されるステム上に、トランジスタ素子等の半導
体素子個片（チップ）を半田、金−錫、金−シリコンあ
るいは金−ゲルマニウム等のろう材を用い固着すること
が行なわれる。When manufacturing semiconductor devices such as transistors and diodes, semiconductor elements (chips) such as transistor elements are placed on stems made of metals such as copper, iron-nickel alloys, or Kovar by soldering, gold-tin, or gold. - Fixation is performed using a brazing material such as silicon or gold-germanium.
かかるろう材を用いての固着の際、ろう材の一部は半導
体素子個片の側面に這い上がり、固着強度が増大する。During bonding using such a brazing material, a portion of the brazing material creeps up to the side surfaces of the individual semiconductor element pieces, increasing the bonding strength.
しかしながら前記半導体素子がいわゆるメサ型素子であ
る場合には、該素子に形成されたＰＮ接合が該素子の側
面に表出されているため、前記ろう材の這い上がりによ
り耐圧の低下あるいは短絡等を招き易い。However, when the semiconductor element is a so-called mesa type element, the PN junction formed in the element is exposed on the side surface of the element, so the creeping up of the brazing material may cause a drop in breakdown voltage or a short circuit. Easy to invite.
本考案は、前述の如きろう材の這い上がりを抑制腰前記
メサ型半導体素子を固着する場合であっても耐圧の低下
、短絡等を招くことのない固着構造を提供しようとする
ものである。The present invention aims to provide a fixing structure that prevents the brazing filler metal from creeping up as described above and does not cause a drop in withstand voltage or short circuit even when fixing the mesa type semiconductor element.
このため、本考案によれば、ステムと一方の主面に形成
された金属化層が前記ステムに固着され且つ貫通孔を通
して前記金属化層に連続して他方の主面に形成されて素
子固着用金属化層が形成された絶縁体と、前記絶縁体の
素子固着用金属化層に固着された半導体素子とを備え、
前記素子固着用金属化層は前記半導体素子の被固着部と
相似の形状を有し且つ前記半導体素子の被固着部よりも
若干中さな面積とされてなる半導体装置が提供される。Therefore, according to the present invention, a stem and a metallized layer formed on one main surface are fixed to the stem, and are formed on the other main surface continuously to the metallized layer through a through hole to fix the element. an insulator on which a metallized layer is formed, and a semiconductor element fixed to the element fixing metallized layer of the insulator,
A semiconductor device is provided in which the element fixing metallized layer has a similar shape to the fixed part of the semiconductor element and has a slightly smaller area than the fixed part of the semiconductor element.
以下本考案を実施例をもって詳細に説明する。The present invention will be explained in detail below with reference to examples.
図面は本考案による半導体装置の実施例の要部を示す。The drawings show essential parts of an embodiment of a semiconductor device according to the present invention.
同図において、１１は銅（Ｃｕ）から構成されるステム
、１２はアルミナ（Ａ１□０３ ）から構成される絶縁
板、１３は前記絶縁板１２のほぼ中央部に設けられた貫
通孔１４を通して前記絶縁板１２の一方の主面全面から
他方の主面の一部に連続して形成されたモリブデン（Ｍ
ｏ）−マンガン（Ｍｎ ）メタライズ層、１５は半田か
らなるろう材でなる。In the same figure, 11 is a stem made of copper (Cu), 12 is an insulating plate made of alumina (A1□03), and 13 is a stem made of alumina (A1□03), and 13 is a stem made of copper (Cu). Molybdenum (M
o) - Manganese (Mn) metallized layer 15 is a brazing filler metal made of solder.
また１６はサイリスク等の半導体素子である。Further, 16 is a semiconductor element such as Cyrisk.
このような構造において、前記絶縁板１２の他方の主面
（上面）に配設されるメタライズ層１３−ｂはその形成
される形状、大きさが、半導体素子１６の被固着面と相
似であって且つ若干中さな面積とされる。In such a structure, the shape and size of the metallized layer 13-b disposed on the other main surface (upper surface) of the insulating plate 12 are similar to the surface to be fixed of the semiconductor element 16. It is said to have a somewhat medium area.
したがって前記メタライズ層１３−ｂ上に予め付着され
るろう材１５の量は制限され、よってかかるろう材１５
が半導体素子１６の側面に這い上がり例えばＰＮ接合１
６−ａを短絡すること等が防止される。Therefore, the amount of brazing material 15 deposited on the metallized layer 13-b in advance is limited, and therefore the amount of brazing material 15 deposited on the metallized layer 13-b is limited.
creeps up the side of the semiconductor element 16, for example, the PN junction 1
6-a is prevented from being short-circuited.
また前記絶縁板１２の一方の主面（下面）全面に配設さ
れるメタライズ層１３−ａは、ろう材１５によってステ
ム１１上面に強固に固着される。Further, the metallized layer 13-a disposed on the entire surface of one main surface (lower surface) of the insulating plate 12 is firmly fixed to the upper surface of the stem 11 by a brazing material 15.
したがって前記半導体素子１６から発生した熱は、前記
ろう材１５、メタライズ層１３及び絶縁板１２を通して
有効にステム１１に伝導され、前記半導体素子１６の熱
放散、冷却がなされる。Therefore, the heat generated from the semiconductor element 16 is effectively conducted to the stem 11 through the brazing material 15, the metallized layer 13, and the insulating plate 12, and the semiconductor element 16 is dissipated and cooled.
更に前記半導体素子の電極の一つは前記ろう材１５、メ
タライズ層１３によってステム１１に電気的に接続され
る。Further, one of the electrodes of the semiconductor element is electrically connected to the stem 11 through the brazing material 15 and the metallized layer 13.
このような半導体装置を形成する手順としては、まずス
テム１１上に既にメタライズ層１３が形成された絶縁板
１２をろう材によって固着し、次いて前記絶縁板１２表
面のメタライズ層１３−ｂ上にろう材によって半導体素
子１６を固着する方法、あるいはまず既にメタライズ層
１３が形成された絶縁板１２表面の前記メタライズ層１
３−ｂにろう材によって半導体素子１６を固着し、次い
で前記絶縁板１２をろう材によってステム１１上に固着
する方法等をとることができる。The procedure for forming such a semiconductor device is to first fix the insulating plate 12 on which the metallized layer 13 has already been formed on the stem 11 with a brazing material, and then fix the metallized layer 13-b on the surface of the insulating plate 12. A method of fixing the semiconductor element 16 with a brazing material, or first of all, a method of fixing the semiconductor element 16 with a brazing material, or first of all, fixing the metallized layer 1 on the surface of the insulating plate 12 on which the metallized layer 13 has already been formed.
3-b, the semiconductor element 16 is fixed with a brazing material, and then the insulating plate 12 is fixed onto the stem 11 with a brazing material.
このような方法において、最初の固着処理に使用される
ろう材の融点を次の固着処理に使用されるろう材の融点
よりも高くすることにより当該固着処理の作業性を高め
ることができる。In such a method, the workability of the fixing process can be improved by making the melting point of the brazing filler metal used in the first fixing process higher than that of the brazing filler metal used in the next fixing process.
このようにしてステム１１上に配置された半導体素子１
６の電極１６−ｂ、１６−ｃ等は、ステム１１あるいは
キャップ（図示せず）にガラス、セラミック等によって
絶縁されて植立された外部接続端子（図示せず）にリー
ド線（図示せず）によって接続される。Semiconductor element 1 placed on stem 11 in this way
The electrodes 16-b, 16-c, etc. of No. 6 are connected to lead wires (not shown) to external connection terminals (not shown) that are insulated and planted with glass, ceramic, etc. on the stem 11 or the cap (not shown). ) connected by
そして前記半導体素子１６は当該半導体素子１６を覆っ
てステム１１に溶着される前記キャップによって気密封
止される。The semiconductor element 16 is hermetically sealed by the cap that covers the semiconductor element 16 and is welded to the stem 11.
以上のような本考案によれば、前述の如く半導体素子が
固着される金属化された領域は、前記半導体素子の被固
着面と相似の形状を有し且つ前記半導体素子の被固着面
よりも若干中さな面積とされる。According to the present invention as described above, the metallized region to which the semiconductor element is fixed has a similar shape to the fixed surface of the semiconductor element and is larger than the fixed surface of the semiconductor element. It is said to have a slightly medium area.
したがって前記金属化された領域に付着されるろう材の
量は制限を受け、当該金属化された領域に固着される前
記半導体素子の側面にろう材の這い上がりを生じること
がない。Therefore, the amount of brazing material deposited on the metallized region is limited, and the brazing material does not creep up onto the side surface of the semiconductor element fixed to the metallized region.
以上のように本考案によれば、製造歩留り、信頼性の高
い半導体装置が提供される。As described above, according to the present invention, a semiconductor device with high manufacturing yield and high reliability is provided.
なお、本考案に適用される半導体素子、ステム材料、絶
縁体材料、メタライズ層材料、ろう材等は前記実施例に
限定されない。Note that the semiconductor element, stem material, insulator material, metallized layer material, brazing material, etc. applied to the present invention are not limited to the above embodiments.
図面は本考案による半導体装置の構造を示す要部断面図
である。
図において、１１・・・・・・ステム、１２・・・・・
・絶縁板、１３・・・・・・メタライズ層、１４・・・
・・・貫通孔、１５・・・・・・ろう材、１６・・・・
・・半導体素子、である。The drawing is a sectional view of a main part showing the structure of a semiconductor device according to the present invention. In the figure, 11... stem, 12...
・Insulating plate, 13...Metallized layer, 14...
...Through hole, 15...Brazing material, 16...
...Semiconductor element.
Claims (1)
ステムに固着され、且つ貫通孔を通して前記メタライズ
層に連続して他方の主面に形成されて素子固着用メタラ
イズ層が形成された絶縁体と、前記絶縁体の素子固着用
メタライズ層に固着された半導体素子とを備え、前記素
子固着用メタライズ層は前記半導体素子の被固着部と相
似の形状を有し、且つ前記半導体素子の被固着部よりも
若干中さな面積とされてなることを特徴とする半導体装
置。An insulator comprising a stem, a metallized layer formed on one main surface fixed to the stem, and a metallized layer for element fixing formed on the other main surface continuously to the metallized layer through a through hole. and a semiconductor element fixed to the element fixing metallized layer of the insulator, the element fixing metallized layer has a shape similar to the fixed part of the semiconductor element, and the semiconductor element fixed to the fixed part. A semiconductor device characterized in that the area is slightly smaller than that of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17332480U JPS6025900Y2 (en) | 1980-12-03 | 1980-12-03 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17332480U JPS6025900Y2 (en) | 1980-12-03 | 1980-12-03 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5794944U JPS5794944U (en) | 1982-06-11 |
| JPS6025900Y2 true JPS6025900Y2 (en) | 1985-08-03 |
Family
ID=29531556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17332480U Expired JPS6025900Y2 (en) | 1980-12-03 | 1980-12-03 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6025900Y2 (en) |
-
1980
- 1980-12-03 JP JP17332480U patent/JPS6025900Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5794944U (en) | 1982-06-11 |
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