JPS6352461B2 - - Google Patents

Info

Publication number
JPS6352461B2
JPS6352461B2 JP54146249A JP14624979A JPS6352461B2 JP S6352461 B2 JPS6352461 B2 JP S6352461B2 JP 54146249 A JP54146249 A JP 54146249A JP 14624979 A JP14624979 A JP 14624979A JP S6352461 B2 JPS6352461 B2 JP S6352461B2
Authority
JP
Japan
Prior art keywords
layer
gold
germanium
ceramic body
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54146249A
Other languages
Japanese (ja)
Other versions
JPS5669839A (en
Inventor
Shigeo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP14624979A priority Critical patent/JPS5669839A/en
Publication of JPS5669839A publication Critical patent/JPS5669839A/en
Publication of JPS6352461B2 publication Critical patent/JPS6352461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明はセラミツクパツケージに半導体チツプ
を接着またはマウントする方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of bonding or mounting semiconductor chips to a ceramic package.

半導体装置を製造するためには、半導体素子を
形成した半導体チツプを担体上に接着する必要が
ある。かかる担体のひとつにセラミツクパツケー
ジがある。従来、このセラミツク体の一主面上に
モリブデンまたはタングステン層、ニツケル層及
び金層を順次形成するか若しくはガラス−金の焼
結層を形成し、この上にシリコン半導体チツプを
載せた後加熱処理して金−シリコン共晶による接
着をおこなつている。 In order to manufacture a semiconductor device, it is necessary to adhere a semiconductor chip on which a semiconductor element is formed onto a carrier. One such carrier is a ceramic package. Conventionally, a molybdenum or tungsten layer, a nickel layer, and a gold layer are sequentially formed on one main surface of this ceramic body, or a glass-gold sintered layer is formed, and a silicon semiconductor chip is placed on top of this, followed by heat treatment. Adhesion is performed using gold-silicon eutectic.

しかし、セラミツク体は通常の金属パツケージ
の金属体よりもはるかに平滑性が悪く、チツプを
接着すべき主面には相当大きな反りが存在する。
従つて、チツプ裏面全体が金−シリコン共晶によ
り接着されずに１部のみで接着していることが多
い。この場合、電気的接地が不十分で電気抵抗が
増大したり、チツプからの発熱の吸収または伝導
が不十分となるばかりか、チツプ裏面に少数キヤ
リヤが発生する等の欠点が発生する。更に、セラ
ミツク体の主面にガラス−金焼結層が形成されて
いる場合には、この焼結層の機械的強度が弱いた
めに接着時のチツプのスクラブによりガラス−金
焼結層が破られ、端に押しのけられてしまう。こ
の結果、チツプの接着は増々部分的になつてしま
う。 However, the smoothness of the ceramic body is much worse than that of the metal body of a normal metal package, and there is considerable warpage on the main surface to which the chip is to be bonded.
Therefore, the entire back surface of the chip is often not bonded by the gold-silicon eutectic, but only a portion thereof is bonded. In this case, there are disadvantages such as insufficient electrical grounding, increased electrical resistance, insufficient absorption or conduction of heat from the chip, and generation of minority carriers on the back surface of the chip. Furthermore, if a glass-gold sintered layer is formed on the main surface of the ceramic body, the mechanical strength of this sintered layer is weak, so the glass-gold sintered layer may be broken by the scrubbing of the chip during bonding. He is pushed aside and pushed aside. As a result, the bonding of the chips becomes increasingly partial.

本発明の目的は平滑性の劣るセラミツク体に対
して半導体チツプの裏面全体を接着することが出
来る改良された接着方法を提供することである。 SUMMARY OF THE INVENTION An object of the present invention is to provide an improved bonding method capable of bonding the entire back surface of a semiconductor chip to a ceramic body having poor smoothness.

本発明によれば、半導体チツプの裏面に金層を
形成し、該金層とセラミツク体の一主面の間に金
−ゲルマニウムのフオイルを介在させ、この集合
体を加熱してセラミツク体に半導体チツプを接着
することを含む、半導体装置の製法が提供され
る。この第１の製法による半導体装置においては
セラミツク体とチツプとは金−ゲルマニウム層に
より接着またはマウントされる。 According to the present invention, a gold layer is formed on the back surface of a semiconductor chip, a gold-germanium foil is interposed between the gold layer and one main surface of a ceramic body, and this aggregate is heated to form a semiconductor into a ceramic body. A method of manufacturing a semiconductor device is provided that includes bonding a chip. In the semiconductor device according to the first manufacturing method, the ceramic body and the chip are bonded or mounted using a gold-germanium layer.

第２の半導体装置の製法によれば、半導体装置
の裏面にバナジウム層を形成し、その上にニツケ
ル層を形成し、その上に金層を形成し、この金層
とセラミツク体の一主面との間に金−ゲルマニウ
ムのフオイルを介在させ、この集合体を加熱して
セラミツク体に半導体チツプを接着することを含
む半導体装置の製法が提供される。この第２の製
法による半導体装置では、セラミツク体とチツプ
はニツケル−金−ゲルマニウム層で接着またはマ
ウントされる。 According to the second method for manufacturing a semiconductor device, a vanadium layer is formed on the back surface of the semiconductor device, a nickel layer is formed on the vanadium layer, a gold layer is formed on top of the vanadium layer, and the gold layer and one main surface of the ceramic body are formed on the vanadium layer. A method for manufacturing a semiconductor device is provided, which includes interposing a gold-germanium foil between the ceramic body and the ceramic body, and heating the assembly to bond a semiconductor chip to a ceramic body. In the semiconductor device according to this second manufacturing method, the ceramic body and the chip are bonded or mounted with a nickel-gold-germanium layer.

次に実施例により本発明を更に詳しく説明す
る。第１図および第２図に示す第１の実施例は上
記第１の製法に関するものである。まず、シリコ
ン半導体チツプ１の裏面に金層２を蒸着する。金
層２の厚さは1000Å以上、好ましくは1000〜3000
Åである。金層２が厚すぎると後の接着のための
加熱温度が上昇してしまう。他方、セラミツクパ
ツケージ４の主面（マウント部）には通常の方法
に従つて金粉とガラス粉と塗布して焼結した金−
ガラス焼結層７が形成されている。この金−ガラ
ス焼結層７の代りに下記第２の実施例のように金
層を用いてもよい。このマウント部の金−ガラス
焼結層７の上に金−ゲルマニウムフオイル８を置
き、その上に裏面の金層２が接するように半導体
ペレツト１を載置する（第１図）。金−ゲルマニ
ウムフオイルはハンダの役割を果すものであるか
ら、ペレツト及びパツケージの寸法に応じて大き
さを調節する。通常は、３×５mmのペレツトに対
して３×３mmで厚さ30μｍ〜50μｍのフオイルを
使用するのが好ましい。また、金−ゲルマニウム
フオイルの組成は５〜12重量％のゲルマニウム含
有量が使用できるが、ゲルマニウム含有量が多く
なる程加工性が低下する。最も好ましくは約7.4
重量％のゲルマニウムを含む金−ゲルマニウムの
フオイルである。次に、第１図のように積み重ね
た集合体を350〜380℃の温度に加熱し、金−ゲル
マニウムフオイル８を熔融し、ペレツトの金層２
及びセラミツクパツケージの金−ガラス焼結層７
中の金と合金化させることによつて接着する。ペ
レツト１とセラミツクパツケージ４を結合してい
る層９は金−ゲルマニウムからなる（第２図）。
この実施例を示す第１図及び第２図ではセラミツ
クパツケージ４が凹状に反つている場合を図示し
た。この反り量は平均約20〜60μｍであることが
一般的である。金−ゲルマニウムフオイルは比較
的低融点であるため350〜380℃で熔融し、ペレツ
ト裏面の金層と容易に合金化する。しかも両者の
ぬれ性が良いため第２図に示すようにペレツト１
の裏面全体に層９が接触してペレツト１を固定す
る。 Next, the present invention will be explained in more detail with reference to Examples. The first embodiment shown in FIGS. 1 and 2 relates to the first manufacturing method described above. First, a gold layer 2 is deposited on the back surface of a silicon semiconductor chip 1. The thickness of the gold layer 2 is 1000 Å or more, preferably 1000 to 3000 Å
It is Å. If the gold layer 2 is too thick, the heating temperature for subsequent adhesion will increase. On the other hand, the main surface (mounting part) of the ceramic package 4 is coated with gold powder and glass powder and sintered using a conventional method.
A glass sintered layer 7 is formed. Instead of this gold-glass sintered layer 7, a gold layer may be used as in the second embodiment below. A gold-germanium foil 8 is placed on top of the gold-glass sintered layer 7 of the mount section, and a semiconductor pellet 1 is placed thereon so that the gold layer 2 on the back side is in contact with it (FIG. 1). Since the gold-germanium foil plays the role of solder, its size is adjusted according to the dimensions of the pellet and package. Usually, it is preferable to use a foil measuring 3 x 3 mm and having a thickness of 30 µm to 50 µm for a 3 x 5 mm pellet. Furthermore, although a germanium content of 5 to 12% by weight can be used for the composition of the gold-germanium foil, the processability decreases as the germanium content increases. Most preferably around 7.4
Gold-germanium foil containing % germanium by weight. Next, the stacked aggregate as shown in Fig. 1 is heated to a temperature of 350 to 380°C to melt the gold-germanium film 8 and remove the gold layer 2 of the pellet.
and gold-glass sintered layer 7 of ceramic package
It is bonded by alloying it with the gold inside. The layer 9 connecting the pellet 1 and the ceramic package 4 consists of gold-germanium (FIG. 2).
1 and 2 showing this embodiment, the ceramic package 4 is warped in a concave manner. The amount of warpage is generally about 20 to 60 μm on average. Since the gold-germanium foil has a relatively low melting point, it melts at 350-380°C and easily alloys with the gold layer on the back side of the pellet. Moreover, since the wettability of both is good, as shown in Figure 2, pellet 1
A layer 9 contacts the entire back surface of the pellet to fix the pellet 1.

第２の実施例は第２の製法に関するものであ
り、セラミツクパツケージが凸状に反つている場
合を図示した。この実施例においては、シリコン
半導体ペレツト１０の裏面にまずバナジウム層１
１を蒸着し、次にニツケル層１２を蒸着またはメ
ツキし、その後金層１３を蒸着またはメツキす
る。バナジウム層１１はシリコンとの密着性が良
いので密着強度の向上に役立つと共に、ペレツト
１０のシリコンの金層１３または層１９への拡散
及び合金化を阻止する。このバナジウム層１１の
厚さは300〜600Åが適当である。ニツケル層１２
はハンダの役割を果すと同時にバナジウム層１１
と同様にシリコン−金合金化に対するバリヤー層
となる。このニツケル層の厚さは3500〜4500Åが
適当である。金層１３は上記第１の実施例の場合
と同様である。他方、セラミツクパツケージ１４
の主面（マウント部）には通常の方法に従つて、
モリブデンまたはタングステン層１５、この上に
ニツケル層１６及びこの上に金層１７が形成され
ている。このセラミツクパツケージ１４の主面上
に金−ゲルマニウムフオイル１８を載置し、その
上に裏面の金層１３が接するようにペレツト１０
を載せる（第３図）。金−ゲルマニウムフオイル
１８は上記第１の実施例と同一である。このよう
に構成した集合体を350〜380℃で加熱すればペレ
ツト１０のニツケル層１２及び金層１３、パツケ
ージ１４の金層１７及び場合によつてはニツケル
層１６、並びに金−ゲルマニウムフオイル１８が
合金化して層１９が形成される（第４図）。層１
９はニツケル−金−ゲルマニウムからなり、ペレ
ツト１０の裏面全体に接触している。顕微鏡での
断面観察によればペレツト１０の裏面にはバナジ
ウム層１１が残つており、シリコンの拡散及び合
金化を完全に防止していることが判つた。 The second embodiment relates to the second manufacturing method, and illustrates a case in which the ceramic package is warped in a convex shape. In this embodiment, a vanadium layer 1 is first formed on the back surface of the silicon semiconductor pellet 10.
1, then a nickel layer 12 is deposited or plated, and then a gold layer 13 is deposited or plated. Since the vanadium layer 11 has good adhesion to silicon, it helps to improve the adhesion strength, and also prevents diffusion and alloying of the silicon in the pellet 10 into the gold layer 13 or layer 19. The appropriate thickness of this vanadium layer 11 is 300 to 600 Å. Nickel layer 12
plays the role of solder and at the same time the vanadium layer 11
Similarly, it serves as a barrier layer against silicon-gold alloying. The appropriate thickness of this nickel layer is 3500 to 4500 Å. The gold layer 13 is the same as in the first embodiment. On the other hand, the ceramic package 14
On the main surface (mount part) of the
A layer of molybdenum or tungsten 15 is formed thereon, a layer of nickel 16 and a layer of gold 17 thereon. A gold-germanium foil 18 is placed on the main surface of the ceramic package 14, and a pellet 10 is placed on top of it so that the gold layer 13 on the back surface is in contact with the gold-germanium foil 18.
(Figure 3). The gold-germanium foil 18 is the same as in the first embodiment above. When the assembly thus constructed is heated at 350 to 380°C, the nickel layer 12 and the gold layer 13 of the pellet 10, the gold layer 17 of the package 14 and in some cases the nickel layer 16, and the gold-germanium foil 18 are formed. are alloyed to form layer 19 (FIG. 4). layer 1
9 is made of nickel-gold-germanium and is in contact with the entire back surface of the pellet 10. A cross-sectional observation under a microscope revealed that the vanadium layer 11 remained on the back surface of the pellet 10, completely preventing diffusion and alloying of silicon.

また、第２図及び第４図に示すように、金−ゲ
ルマニウムフオイル８，１８は熔融してパツケー
ジ４，１４の凸状または凹状の反りを完全に補填
しうる層９，１９となる。従つて、セラミツクパ
ツケージの悪い平滑性にもかかわらずペレツト裏
面全体を固定することが出来る。セラミツクパツ
ケージの主面に機械的に弱い金−ガラス焼結層が
ある場合でもこの層を破壊することなくペレツト
を固定できる。 Further, as shown in FIGS. 2 and 4, the gold-germanium foils 8, 18 are melted to form layers 9, 19 that can completely compensate for the convex or concave warpage of the packages 4, 14. Therefore, the entire back side of the pellet can be fixed despite the poor smoothness of the ceramic package. Even if there is a mechanically weak gold-glass sintered layer on the main surface of the ceramic package, the pellets can be fixed without destroying this layer.

本発明によれば、上記のごとくペレツト裏面全
体が接着され且つパツケージの電気伝導部及び熱
伝導部の欠損が全くなくなるので半導体装置の特
性が改良される。例えば、MOSトランジスタの
PN接合に即ちソースまたはドレイン電極とパツ
ケージの電気伝導部（金層または金−ガラス焼結
層）の間に順方向電流を流し、その時の電圧降下
Vifを測定した。従来の装置では２〜8V、平均
5Vで偏σ1.0Vであつたのに対し、本発明による装
置では約1.3V、平均1.3V、偏差σ0.15Vであつた。
このように電圧降下が非常に少なくしかもバラツ
キが少ないことはダイナミツクランダムアクセス
メモリー等のMOSメモリーの回路に極めて有効
である。従つて、不良品発生率は従来10〜20％で
あつたのに対し、本発明によれば０〜0.5％と大
巾に改良された。 According to the present invention, as described above, the entire back surface of the pellet is bonded and there is no damage to the electrically conductive portions and thermally conductive portions of the package, so that the characteristics of the semiconductor device are improved. For example, MOS transistor
When a forward current is passed through the PN junction, that is, between the source or drain electrode and the electrically conductive part of the package (gold layer or gold-glass sintered layer), the voltage drop at that time is
Vif was measured. 2-8V with conventional equipment, average
At 5V, the deviation was σ1.0V, whereas in the device according to the present invention, it was about 1.3V, average 1.3V, and deviation σ0.15V.
This very low voltage drop and low variation is extremely effective for MOS memory circuits such as dynamic random access memory. Therefore, the incidence of defective products was conventionally 10 to 20%, but according to the present invention, it was greatly improved to 0 to 0.5%.

また、本方法によれば金−ゲルマニウムフオイ
ルの共晶点がガラスの融点よりも低い為、ガラス
で固定されたリード線の位置が狂うことがなく、
後のワイヤボンデイングが容易である。 In addition, according to this method, since the eutectic point of the gold-germanium foil is lower than the melting point of glass, the position of the lead wire fixed with glass will not go out of order.
Later wire bonding is easy.

更にまた、半導体ペレツトの接着時に金−ゲル
マニウムフオイルのスクラツチ物が発生したとし
ても、後の封止工程における温度条件（450〜460
℃）で金−ガラス焼結層中に吸収される。従つ
て、このスクラツチ物が異なる電極または導線間
を短縮するなどの危険性はない。 Furthermore, even if scratches of gold-germanium foil are generated during bonding of semiconductor pellets, the temperature conditions (450 to 460
℃) into the gold-glass sintered layer. Therefore, there is no risk that this scratch material will shorten the distance between different electrodes or conductors.

尚、上記実施例では金−ゲルマニウムフオイル
をチツプとセラミツク体の間にはさむ具体例を説
明したが、このフオイルを予めチツプ裏面の金層
に融着される場合も本発明の範囲内に含まれる。 Incidentally, in the above embodiment, a specific example in which a gold-germanium film is sandwiched between a chip and a ceramic body has been described, but a case in which this film is fused in advance to a gold layer on the back side of a chip is also included within the scope of the present invention. It will be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図は第１の発明の具体例を示
す断面図であり、第３図および第４図は第２の発
明の具体例を示す断面図である。 １，１０……半導体チツプ、４，１４……セラ
ミツクパツケージ、８，１８……金−ゲルマニウ
ムフオイル。 1 and 2 are sectional views showing a specific example of the first invention, and FIGS. 3 and 4 are sectional views showing a specific example of the second invention. 1, 10... Semiconductor chip, 4, 14... Ceramic package, 8, 18... Gold-germanium foil.

Claims (1)

【特許請求の範囲】 １ Si半導体チツプの裏面にバナジウム層を形成
し、その上にニツケル層を形成し、その上に金層
を形成し、この金層とセラミツク体の一主面との
間に金−ゲルマニウムのフオイルを介在させ、こ
の集合体を350°〜380℃で加熱してセラミツク体
に半導体チツプを一体化することを含む半導体装
置の製造方法。 ２ 上記セラミツク体の一主面には金層またはガ
ラス−金焼結層が形成される特許請求の範囲第１
項記載の半導体装置の製造方法。[Claims] 1. A vanadium layer is formed on the back surface of a Si semiconductor chip, a nickel layer is formed on top of the vanadium layer, a gold layer is formed on top of the vanadium layer, and between this gold layer and one main surface of the ceramic body. A method for manufacturing a semiconductor device, which comprises interposing a gold-germanium foil in a ceramic body and heating the assembly at 350° to 380°C to integrate a semiconductor chip into a ceramic body. 2. Claim 1, wherein a gold layer or a glass-gold sintered layer is formed on one main surface of the ceramic body.
A method for manufacturing a semiconductor device according to section 1.
JP14624979A 1979-11-12 1979-11-12 Semiconductor device and manufacture thereof Granted JPS5669839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14624979A JPS5669839A (en) 1979-11-12 1979-11-12 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14624979A JPS5669839A (en) 1979-11-12 1979-11-12 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS5669839A JPS5669839A (en) 1981-06-11
JPS6352461B2 true JPS6352461B2 (en) 1988-10-19

Family

ID=15403457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14624979A Granted JPS5669839A (en) 1979-11-12 1979-11-12 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5669839A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2567442B2 (en) * 1988-02-22 1996-12-25 住友電気工業株式会社 Semiconductor device and manufacturing method thereof
JP3372511B2 (en) * 1999-08-09 2003-02-04 ソニーケミカル株式会社 Semiconductor element mounting method and mounting device

Also Published As

Publication number Publication date
JPS5669839A (en) 1981-06-11

Similar Documents

Publication Publication Date Title
TW419761B (en) Chip size package and method of fabricating the same
US6164523A (en) Electronic component and method of manufacture
JP3420703B2 (en) Method for manufacturing semiconductor device
US20070085201A1 (en) Power semiconductor device in lead frame technology with a vertical current path
JPH08181392A (en) Bonding material and bonding method of electric element
US4042951A (en) Gold-germanium alloy contacts for a semiconductor device
JPH0936186A (en) Power semiconductor module and its mounting method
EP0090566B1 (en) Semiconductor device package
GB2138633A (en) Bonding semiconductor chips to a lead frame
JPH06501816A (en) Synthetic hybrid semiconductor structures
US20020095784A1 (en) Bumping process for chip scale packaging
US3480842A (en) Semiconductor structure disc having pn junction with improved heat and electrical conductivity at outer layer
JPS6352461B2 (en)
JPS5850021B2 (en) Manufacturing method for semiconductor devices
JPS61181136A (en) Die bonding
JPH1084011A (en) Semiconductor device, manufacture thereof and semiconductor device mounting method
JP3446829B2 (en) Semiconductor device
JP3645391B2 (en) Manufacturing method of semiconductor integrated circuit device
JPH02168640A (en) Connection structure between different substrates
US20220045031A1 (en) Semiconductor device and method for fabricating the same
JPH0525182B2 (en)
JP2986661B2 (en) Method for manufacturing semiconductor device
JPH1032275A (en) Semiconductor device and manufacture thereof
JPH03208355A (en) Semiconductor device and manufacture thereof
JPS6025900Y2 (en) semiconductor equipment