JPS58157147A - Hybrid integrated circuit substrate - Google Patents
Hybrid integrated circuit substrateInfo
- Publication number
- JPS58157147A JPS58157147A JP57039905A JP3990582A JPS58157147A JP S58157147 A JPS58157147 A JP S58157147A JP 57039905 A JP57039905 A JP 57039905A JP 3990582 A JP3990582 A JP 3990582A JP S58157147 A JPS58157147 A JP S58157147A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- electrode conductor
- hybrid integrated
- insulating substrate
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はフリップ・チツプエ０などの半導体素子を実
装するための混成集積回路基板の改良に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in hybrid integrated circuit boards for mounting semiconductor devices such as flip chips.
電子機器の小形化に伴ない、セラミックなどの材料よシ
なる絶縁性基板上にマルチ・バンプを有する多数の７リ
ツプ・チツプエＣを高密度で実装するための混成集積回
路基板に対する要求が近年特に著しい。この混成集積回
路基板の高密度化に伴ない生産性、特に歩留シ向上が最
大の問題点となっている。With the miniaturization of electronic devices, there has been a particular demand in recent years for hybrid integrated circuit boards for mounting multiple 7-lip chips with multi-bumps at high density on insulating substrates made of materials such as ceramics. Significant. As the density of hybrid integrated circuit boards increases, the biggest problem is improving productivity, especially yield.
仁の糧の用途には、従来第１図の断面図に示すような混
成集積回路基板が用いられていた。図において（１）は
セラミックなどの材料よりなる絶縁性基板、（２）は銀
−パラジウム、銀−バラジウム−白金、金メッキされた
モリブデン又はタングステンなどの金属材料よりなる電
極導体、（３）は、ハンダ・ボール（４）の流れを防止
するための絶縁性ダムでガラスなどの無機材料で形成さ
れ開口部（３ａ）を有している。電極導体（２）、絶縁
性ダム（３）は厚膜技術により形成される。（４）はハ
ンダ・ボールで、電極導体（２）上にハンダ・フラック
スなどで固定される。Conventionally, a hybrid integrated circuit board as shown in the cross-sectional view of FIG. In the figure, (1) is an insulating substrate made of a material such as ceramic, (2) is an electrode conductor made of a metal material such as silver-palladium, silver-valadium-platinum, gold-plated molybdenum or tungsten, and (3) is This insulating dam is made of an inorganic material such as glass and has an opening (3a) to prevent the solder balls (4) from flowing. The electrode conductor (2) and the insulating dam (3) are formed by thick film technology. (4) is a solder ball, which is fixed onto the electrode conductor (2) with solder flux or the like.
第２図は、第１図に示した混成集積回路基板にフリップ
［株］チップエＣを実装した状態を示す断面図で（４ａ
）はハンダ・バンプ、（６）は７リツプφチツプエ０、
（７）はフリップ・チツプエ０（６）の電極バンプであ
る。Figure 2 is a cross-sectional view showing a state in which the Flip Chip E C is mounted on the hybrid integrated circuit board shown in Figure 1 (4a
) is solder bump, (6) is 7 lip φ chip 0,
(7) is the electrode bump of flip chip 0 (6).
フリップΦチツプエＣ（６）の絶縁性基板（１）への実
装は、フリップ・チップエ０の電極パッド（７）をハン
ダ・ボール（４）と所定の位置関係でもって接して配置
し、ハンダ・リフロー法により上記電極パッド（７）と
ハンダ・ボール（４）とを熱融着してハンダ・バンプ（
４ａ）・を形成する事、によりなされるので、ハンダ・
ボール（４Ｌ 電極導体（２）及び絶縁性ダム（３）
とで囲まれる空隙部（５）に上記熱融着工種において、
ハンダ・ボール（４）を電極導体（２）に固定するため
のハンダ・７ラツクスのガスが充満し、このガス圧によ
って上記ハンダ・パンダ（４ａ）の高さが不均一になる
結果、クリップ拳チップエＣ（６）が絶縁性基板（１）
Ｋ歩留り良く実装されず且つその信頼性が悪い欠点があ
った。The flip chip C (6) is mounted on the insulating substrate (1) by placing the electrode pad (7) of the flip chip 0 in contact with the solder ball (4) in a predetermined positional relationship, and then applying the solder. Solder bumps (
4a). Since it is done by forming a solder
Ball (4L electrode conductor (2) and insulating dam (3)
In the above-mentioned heat fusion work type, the cavity (5) surrounded by
The solder panda (4a) is filled with gas for fixing the solder ball (4) to the electrode conductor (2), and the height of the solder panda (4a) becomes uneven due to the gas pressure. Chip E C (6) is an insulating substrate (1)
K had the disadvantage that it could not be implemented with a high yield and its reliability was poor.
特に、ハンダ番ボールの直径が５０−２００μｍでその
数が数十個に及ぶ場合には、７リツプ・チップ（６）の
絶縁性基板（１）への実装は事実上不可能であった。Particularly, when the diameter of the solder balls is 50-200 μm and the number thereof is several dozen, it is virtually impossible to mount the 7-lip chip (6) on the insulating substrate (1).
又、厚膜技術を用いて絶縁性ダム（３）に直敷が′”５
Ｏ−１００μｍの穴を数千個形成する事は性能上および
信、 この発明は上記のような従来のものの欠点を除去
するためになされたもので、所定パターンの電極導体と
複数個の凹部が設けられた絶縁性基板と、上記凹部に対
応した位置に開口部を有する絶縁性ダムと、上記凹部お
よび開口部に配置されたハンダ・ボールとで構成するこ
とにより、生産性が良く且つ信頼性の高い混成集積回路
基板を提供する事を目的としている。Also, using thick film technology, the insulating dam (3) is directly laid.
Forming several thousand holes of O-100 μm is important for performance and reliability. The structure consists of an insulating substrate provided, an insulating dam having an opening at a position corresponding to the recess, and solder balls arranged in the recess and opening, resulting in good productivity and reliability. The objective is to provide a hybrid integrated circuit board with high performance.
以下この発明の一実施例を第３図を用いて説明する。−
において、αＱはセラミックなどの材料よシなる絶縁性
基板、（１０ａ）はレーザ法などの手法により絶縁性基
板（イ）Ｋ設けられた凹部、（１）は所定パターンで形
成された電極導体、に）はハンダ−ボール（４）の流れ
を防止するための絶縁性ダムで、ポリイミド々どの樹脂
よシ々ゐ感光性フィルムを写真製版技術などの手法によ
り上記凹部（１０ａ）に対応し喪位置に開口部（３０ａ
）が設けられている。電極導体（ホ）は、従来と同種の
材料を用いて厚膜技術、写真製版技術などの手法によシ
形成される。An embodiment of the present invention will be described below with reference to FIG. −
, (10a) is an insulating substrate made of a material such as ceramic, (10a) is an insulating substrate (a) K is a recess provided by a method such as a laser method, (1) is an electrode conductor formed in a predetermined pattern, 2) is an insulating dam to prevent the solder ball (4) from flowing, and a photosensitive film such as polyimide or other resin is placed in the recessed portion (10a) using a method such as photolithography. opening (30a
) is provided. The electrode conductor (E) is formed using the same type of material as in the past, using techniques such as thick film technology and photolithography.
第１図に示した絶縁性ダム（３）、電極導体（２）及び
ハンダ書ポール（４）とで囲まれる空隙部（５）が上記
第３図では発生せず、第２図に示し九ハンダ・バンプ（
４ａ）の高さが均一になる結果、フリップ・チップＩＯ
の絶縁性基板ＧＯへの実装における歩留シおよび信頼性
が飛躍°的に向上する。又、絶縁性基板ａりの凹部αＯ
ａ）をレーザ法により形成すると共に、絶縁性ダム−〇
開口部−）を感光性フィルムを用い九写真製版技術によ
シ形成しているので、例えば絶縁性基板ＱＯ上に直径が
５０−２００μｍのハンダ・ボール（４）を数十個配置
する事は比較的容易である。The gap (5) surrounded by the insulating dam (3), electrode conductor (2), and soldering pole (4) shown in FIG. 1 does not occur in FIG. Solder bump (
4a) uniform height results in flip-chip IO
The yield and reliability of mounting on the insulating substrate GO are dramatically improved. Also, the recess αO in the insulating substrate a
a) is formed by a laser method, and an insulating dam (〇opening)) is formed by photolithography using a photosensitive film. It is relatively easy to arrange several dozen solder balls (4).
第４図はこの発明の他の実施例を示す混成集積回路基板
の断面図で、第３図の実施例では電極導体−を絶縁性基
板αＱの凹部αＯａ）にも設けたのに対【７、この実施
例では絶縁性基板ＱＯＯ上に電極導体（ハ）を形成した
後レーザ法により、この電極導体（ハ）および絶縁性基
板ＱＯに凹部（１０ａ）を同時に形成する事によシ生産
性向上及び集積密度の向上を図ったものである。尚、絶
縁性基板ＱＯに凹部（１０ａ）を設けた後、との凹部（
１０ａ）を除いて電極導体（２）を形成しても良い。FIG. 4 is a sectional view of a hybrid integrated circuit board showing another embodiment of the present invention. In the embodiment of FIG. In this example, productivity is increased by forming an electrode conductor (c) on an insulating substrate QOO and then simultaneously forming a recess (10a) on the electrode conductor (c) and the insulating substrate QO using a laser method. The aim is to improve the storage capacity and integration density. Note that after providing the recess (10a) in the insulating substrate QO, the recess (10a) is
The electrode conductor (2) may be formed except for 10a).
嬉５図は、第４図に示した混成集積回路基板に７リツプ
拳チツプエＣ（６）を従来と同様の手法によシハンダ・
バンプ←ａ）によシ実装した状態を示す断面図である。Figure 5 shows how 7 lip chips C (6) are soldered onto the hybrid integrated circuit board shown in Figure 4 using the same method as before.
FIG. 4 is a cross-sectional view showing a state in which the bump is mounted on the bump ←a).
第３図および第４図の実施例では絶縁性基板αＱの凹１
１１（ＩＯＩＬ）をレーザ法で形成したが、サンド・プ
ラスト法、グリーン拳シート法などの手法によシ形成し
ても良い事は勿論である。In the embodiments of FIGS. 3 and 4, the recess 1 of the insulating substrate αQ is
11 (IOIL) was formed by a laser method, but it goes without saying that it may be formed by a method such as a sand-plast method or a green fist sheet method.
以上のように、この発明によれば絶縁性基板に形成され
た凹部に位置合せして感光性フィルムに開口部を設け、
上記凹部および開口部にハンダ・ボールを配置するよう
に構成したので、混成集積回路基板に多数の７リツプ・
チップエＯを高密度で歩留り良く、高信頼度で実装でき
る効果がある。As described above, according to the present invention, an opening is provided in a photosensitive film in alignment with a recess formed in an insulating substrate,
Since the configuration is such that solder balls are placed in the recesses and openings, a large number of 7-lip chips can be placed on the hybrid integrated circuit board.
This has the effect of allowing ChipE-O to be mounted with high density, high yield, and high reliability.
第１図線従来の混成集積回路基板を示す断面図、第２図
線第１図の混成集積回路基板にフリップφチップエＣを
実装した状態を示す断面図、第３図はこの発明の一実施
例による混成集積回路基板を示す断面図、第４図はこの
発明の他の実施例を示す断面図、第５図は第４図の混成
集積回路基板に７シツプ・チツプエＣを実装した状態を
示す断面図である。
図において、（１）−絶縁性基板、（２）、勾、＠］）
−電極導体、（３ＬＨ−絶縁性ダＡ 、（３ａ） 、
（３０ａ）−関口部、（４）−ハンダΦボール、（４＆
）−バンダーバンプ（５）−空隙部、（６） −７リツ
プ・チツプエ０、（７）−電極パッド、←０ａ）−凹部
である。
なお、図中同一符号は同−又は和尚部分を示ブ代理人
葛野信−
第１閏
第２図Fig. 1 is a sectional view showing a conventional hybrid integrated circuit board, Fig. 2 is a sectional view showing a state in which a flip φ chip E C is mounted on the hybrid integrated circuit board of Fig. 1, and Fig. 3 is an embodiment of the present invention. FIG. 4 is a sectional view showing another embodiment of the present invention, and FIG. 5 shows a state in which a 7-ship chip C is mounted on the hybrid integrated circuit board of FIG. 4. FIG. In the figure, (1) - insulating substrate, (2), slope, @])
- electrode conductor, (3LH-insulating da A, (3a),
(30a) - Sekiguchi part, (4) - Solder Φ ball, (4&
) - bander bump (5) - void, (6) - 7 lip chip 0, (7) - electrode pad, ←0a) - recess. In addition, the same reference numerals in the drawings indicate the same or priest parts.
Shin Kuzuno - 1st Leap 2nd Figure
Claims (3)
上に所定パターンで形成された電極導体、この電極導体
の一部を覆い、上記凹部に対応した位置に開口部を有す
る絶縁性ダム、上記凹部および開口部に配置され九ハン
ダ・ボール、とを備えたことを特徴とする混成集積回路
基板。(1) an insulating substrate having a plurality of recesses, an electrode conductor formed in a predetermined pattern on this substrate, an insulating dam covering a portion of the electrode conductor and having an opening at a position corresponding to the recess; nine solder balls disposed in the recess and the opening.
特徴とする特許請求Ｏ蛎囲第１項記龍Ｏ偽成集積回路基
板。(2) The synthetic integrated circuit board set forth in claim 1, wherein the insulating dam is formed of a photosensitive film.
ことを特徴とする特許請求の範囲第１項記載の混成集積
回路基板。(3) The hybrid integrated circuit board according to claim 1, wherein the electrode conductor is formed on the insulating substrate and in the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57039905A JPS58157147A (en) | 1982-03-12 | 1982-03-12 | Hybrid integrated circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57039905A JPS58157147A (en) | 1982-03-12 | 1982-03-12 | Hybrid integrated circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58157147A true JPS58157147A (en) | 1983-09-19 |
Family
ID=12565968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57039905A Pending JPS58157147A (en) | 1982-03-12 | 1982-03-12 | Hybrid integrated circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58157147A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6178140A (en) * | 1984-09-26 | 1986-04-21 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS63121448U (en) * | 1987-01-31 | 1988-08-05 | ||
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| JP2016157900A (en) * | 2015-02-26 | 2016-09-01 | ローム株式会社 | Electronic device |
-
1982
- 1982-03-12 JP JP57039905A patent/JPS58157147A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6178140A (en) * | 1984-09-26 | 1986-04-21 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPH0695543B2 (en) * | 1984-09-26 | 1994-11-24 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| JPS63121448U (en) * | 1987-01-31 | 1988-08-05 | ||
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
| JP2016157900A (en) * | 2015-02-26 | 2016-09-01 | ローム株式会社 | Electronic device |
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