JP2004146728A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out flip chip connection adequately for constituting a COC type system-in package. <P>SOLUTION: In a semiconductor device having a laminated structure, in which a chip 1 is provided with flip chip connection on a chip 2, the chip 1 has an element board 3 having a circuit in an effective element region on the main face, a connecting pad 4 for connecting with the chip 2 electrically, and a measuring pad 5 for measuring electric characteristics of the circuit. In this structure, the measuring pad 5 is formed at a layer lower than the connecting pad 4 in the thickness direction of the element board 3, so the height position of a solder bump 24 formed on the measuring pad 5 is restricted low. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a laminated structure in which a semiconductor element is flip-chip connected on a circuit board, and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, SIP (system-in-package) has attracted attention in maintaining an improvement in the price-to-performance ratio of LSIs. SIP is a package technology that integrates the functions of each chip by combining a plurality of chips (semiconductor elements) and connecting them at high density. According to the SIP, it is possible to well-balance the demands of the system side such as cost reduction, high functionality, low power consumption, small size and light weight, and flexibility in specification.
[0003]
SIPs are classified into four types, namely, COC (chip-on-chip) type, chip stack type, package lamination type, and substrate connection type, depending on their structural differences. Of these, the COC type has a structure in which another chip is stacked on a chip serving as a base, and has a feature that it is easy to cope with high speed because the wiring length between circuits is short. In this COC type, the circuit surfaces of the chips face each other and are connected by flip chips via bumps. As a chip bonding technique in this case, a technique employing flip-chip connection via an Au (gold) bump is known (for example, see Non-Patent Document 1).
[0004]
[Non-patent document 1]
“Nikkei Micro Device”, Nikkei BP, March 2001, p. 125-127
[0005]
[Problems to be solved by the invention]
However, flip-chip connection using Au bumps is generally not suitable for SIP flip-chip connection because a load (bonding load) required at the time of bump bonding is high. That is, in the SIP, bumps are formed on an effective element area (active area) of a chip for reasons such as a degree of freedom in circuit design and a reduction in wiring length. Therefore, when a high load is applied to the circuit surface during bump bonding, the circuit may be damaged. Therefore, it is conceivable to adopt flip-chip connection using solder bumps as a device that can be connected with a lower load than Au bumps. In the flip chip connection using the bumps, since the melting point of the solder is low, the chips can be electrically connected at a low temperature and a low load.
[0006]
On the other hand, on a main surface of a chip constituting the SIP, in addition to an electrode pad for electrically connecting the chips (hereinafter also referred to as a “connection pad”), a circuit (IC, An electrode pad (hereinafter, also referred to as a “measurement pad”) for measuring electrical characteristics of an LSI or the like is formed. The connection pad and the measurement pad differ in pad size, pad arrangement, and the like according to the purpose of forming each electrode pad. Therefore, the connection pad and the measurement pad can be distinguished from these elements.
[0007]
Specifically, the connection pads are formed in an area on the effective element region (circuit surface) of the chip, while the measurement pads are formed collectively on the outer peripheral portion (4 sides, 2 sides) of the chip. You. The connection pad is formed smaller in pad size than the measurement pad. For example, in the case of a measurement pad, the pad size is set to about 70 μm because the probe needle of the probe card needs to be brought into contact with the pad surface at the time of measurement, whereas in the case of the connection pad, the number of pins must be increased. The pad size is set to 40 μm, 20 μm, or 10 μm. Further, when the chips are connected to each other, the connection pads are connected to the partner chip, whereas the measurement pads are not connected. In addition, since the number of measurement pads required for measuring the electrical characteristics is formed, the number of connection pads is larger than the number of measurement pads when comparing the number of pads on the chip.
[0008]
By the way, regarding the pad size, the pad size of the measurement pad may be reduced to the same level as the pad size of the connection pad due to the improvement of the probe card and the proposal of a new connection method in the future. It is presumed that the connection state of the pads and the number of pads will not change in the future. The wiring portion (pattern) on the chip connected to the measurement pad is physically or electrically cut after the electrical measurement in the wafer state is actually completed.
[0009]
When a chip in which connection pads and measurement pads are mixed as described above is mounted on another chip by flip-chip connection using the solder bumps described above, the following problems may occur. That is, when a solder bump is formed on a chip, an electroless nickel (Ni) / gold (Au) plating is applied to an electrode pad made of aluminum as a pretreatment, and then solder is supplied. A bump bump is formed on the electrode pad. In this case, by forming a Ni / Au plating layer on the electrode pad, it is possible to improve the wettability of the solder and suppress the diffusion of the solder. In addition, as a solder supply method, a printing method or a dipping method (dip method) can be considered. However, the printing method requires a special screen mask corresponding to a pad size and a pad arrangement, and furthermore, bumps are formed on fine pads. Because of the difficulty, the immersion method is currently preferred.
[0010]
However, as shown in FIG. 6, Ni / Au plating layers 53 and 54 are uniformly formed (deposited) on the connection pads 51 and the measurement pads 52 formed on the chip. When the solder is supplied by an immersion method after the plating process, the solder bumps 55 are formed not only on the connection pads 51 where the bumps need to be formed but also on the measurement pads 52 where the bumps are not necessary. Is formed.
[0011]
In such a case, since the measurement pad 52 has a larger pad size than the connection pad 51, the solder bump 56 on the measurement pad 52 becomes larger than the solder bump 55 on the connection pad 51. Therefore, when comparing the height positions of the solder bumps 55 and 56 formed on the respective electrode pads (51 and 52), the solder bumps 56 on the measurement pads 52 are larger than the solder bumps 55 on the connection pads 51. It is arranged at a position higher (projected position) by a predetermined dimension F.
[0012]
As a result, in flip-chip connection using solder bumps, when a bump-formed chip is to be mounted on another chip serving as an interposer, the solder bumps 55 on the connection pads 51 come into contact with the mating bump of the connection destination. Before the solder bumps 56 on the measurement pads 52 come into contact with the interposer, the bumps that should be connected may not be connected.
[0013]
[Means for Solving the Problems]
A semiconductor device according to the present invention has a laminated structure in which a semiconductor element is flip-chip connected on a circuit board, and the semiconductor element includes an element substrate having a circuit formed in an effective element region on a main surface; A first electrode pad formed on the main surface of the substrate; a second electrode pad formed on the main surface of the element substrate; and a second electrode pad formed in the thickness direction of the element substrate. It is configured to be disposed below the one electrode pad.
[0014]
In the semiconductor device having the above configuration, the first electrode pad and the second electrode pad are arranged in the same layer (most layer) by arranging the second electrode pad below the first electrode pad in the thickness direction of the element substrate. The height position (protruding state) of the protruding electrode formed on the second electrode pad can be suppressed lower than when it is formed on the upper layer). Therefore, when mounting the semiconductor element on the circuit board, it is possible to perform flip-chip connection with the protruding electrodes formed on the second electrode pads separated from the circuit board.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a side sectional view showing an example of a configuration of a semiconductor device (SIP) according to an embodiment of the present invention and a mounting structure thereof. In FIG. 1, a chip 1 which is a semiconductor element and another chip 2 which is also a semiconductor element are connected in a flip-chip manner, whereby a SIP semiconductor device having a COC type laminated structure (two-layer structure) is obtained. It is configured. The chip 2 serves as an interposer when the chip 1 is mounted by flip-chip connection, and its outer dimensions are set larger than the chip 1.
[0017]
The chip 1 is a semiconductor element configured based on an element substrate 3 such as a silicon substrate, for example, and a circuit having a predetermined function (for example, a memory function) is formed in an effective element area on a main surface thereof. . A plurality of connection pads 4 made of aluminum or the like and a plurality of measurement pads 5 also made of aluminum or the like are formed on the main surface of the chip 1.
[0018]
The connection pad 4 corresponds to the “first electrode pad” in the present invention, and is formed on the main surface of the chip 1 in the effective element region (on the circuit surface). The measuring pad 5 corresponds to the “second electrode pad” in the present invention, and is formed on the main surface of the chip 1 at a position (outer peripheral portion) surrounding the effective element region. The manner of distinguishing the connection pads 4 and the measurement pads 5 on the chip 1 is as described above.
[0019]
The chip 2 is, for example, a semiconductor element configured based on an element substrate 6 such as a silicon substrate in the same manner as described above, and a predetermined function (for example, a logic function) different from that of the chip 1 is provided in an effective element area on a main surface thereof. Is formed. A plurality of connection pads 7 made of aluminum or the like and a plurality of mounting pads 8 also made of aluminum or the like are formed on the main surface of the chip 2.
[0020]
The connection pad 7 is formed on the main surface of the chip 2 in the effective element region (on the circuit surface). The connection pads 7 are formed corresponding to the connection pads 4 of the chip 1, and the pad size and pad arrangement are set so as to match the connection pads 4. The mounting pad 8 is formed on the main surface of the chip 2 at a position (outer peripheral portion) surrounding the effective element region. The mounting pad 8 is for mounting the multilayer chip (1, 2) having the COC structure, which is flip-chip connected, on the mother substrate 9. The chip 2 has a configuration in which the mounting pads 8 also serve as measurement pads.
[0021]
The chip 1 and the chip 2 are electrically and mechanically connected by flip-chip connection using solder bumps, which will be described later, with the circuit surfaces of the chips 1 and 2 facing each other (facing each other). The space between the chip 1 and the chip 2 is filled with a sealing material 10. The sealing material 10 is filled so as to cover the flip chip connection part (solder joint part). A solder electrode 11 is formed on the mounting pad 8 of the chip 2. The solder electrode 11 is connected to a land 12 of the mother board 9. The mother board 9 is configured by a printed wiring board made of, for example, glass epoxy as a base material.
[0022]
Here, a feature of the configuration of the semiconductor device according to the present invention is a stacking relationship between the connection pads 4 and the measurement pads 5 formed on the chip 1. That is, on the main surface of the chip 1, the connection pads 4 are formed in the uppermost layer, whereas the measurement pads 5 are formed in a lower layer than the uppermost connection pads 4. Specifically, for example, as shown in FIG. 2, when the wiring layer of the chip 1 has a two-layer structure, the measurement pads 5 are arranged on the first layer (lower layer), and the measurement pads 5 are formed on the second layer (upper layer). The configuration is such that connection pads 4 are arranged.
[0023]
Subsequently, a method for manufacturing the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS.
[0024]
First, as shown in FIG. 3A, an insulating film 13 made of, for example, SiO ₂ (silicon dioxide) is formed on an element substrate (silicon substrate) 3 serving as a base. Next, as shown in FIG. 3B, a first wiring layer is formed on the insulating film 13 of the element substrate 3 using a metal wiring material made of, for example, aluminum, and the first wiring layer is patterned. Thereby, the first wiring patterns 14A and 14B are formed on the insulating film 13.
[0025]
Next, as shown in FIG. 3C, an interlayer insulating film 15 made of, for example, SiO ₂ is formed on the insulating film 13 so as to cover the first wiring patterns 14A and 14B (lamination). Via holes (conduction paths) 16 leading to the first wiring pattern 14B are formed on the insulating film 15.
[0026]
Next, as shown in FIG. 3D, a second wiring layer is formed on the interlayer insulating film 15 by using a metal wiring material made of, for example, aluminum, and the second wiring layer is patterned to form an interlayer. A second wiring pattern 17 is formed on the insulating film 15. The second wiring pattern 17 formed at this time is electrically connected (conductive) to the first wiring pattern 14B via the via hole 16. In addition, as the metal wiring material, a metal other than aluminum (for example, copper) can be used.
[0027]
Subsequently, as shown in FIG. 4A, a passivation film 18 made of, for example, SiN (silicon nitride) is formed (laminated) on the interlayer insulating film 15 so as to cover the second wiring pattern 17.
[0028]
Next, a resist pattern (not shown) is formed on the passivation film 18 and an etching process is performed using the resist pattern as a mask, thereby forming a pad opening communicating with the first wiring pattern 14A as shown in FIG. A pad opening 20 communicating with 19 and the second wiring pattern 17 is formed on the passivation film 18. Of these, the portion exposed by the pad opening 19 on the second wiring pattern 17 becomes the connection pad 4, and the portion exposed by the pad opening 20 on the first wiring pattern 14A becomes the measurement pad 5. That is, the connection pads 4 are formed by the second wiring patterns 17, and the measurement pads 5 are formed by the first wiring patterns 14A.
[0029]
At this time, assuming that aluminum is used as the metal wiring material and dry etching is adopted as a specific method of the etching process, the etching rate of aluminum becomes lower than that of the interlayer insulating film (SiO ₂ ) 15 and the passivation film (SiN) 18. Since the etching speed is extremely slow compared to the etching rate, the pad openings 19 and 20 communicating with the connection pad 4 and the measurement pad 5 can be formed simultaneously by one etching process. The gas used at that time is a mixed gas of Ar, CHF3, CF4 and the like.
[0030]
Next, as shown in FIG. 4C, plating layers 21 and 22 are formed on the connection pads 4 and the measurement pads 5, respectively, by electroless plating of Ni / Au. The plating layers 21 and 22 serve as a base metal, that is, an under bump metal when forming a protruding electrode (a solder bump in this embodiment) on each of the electrode pads (4, 5). In the chip 1, the surface on which the plating layers 21 and 22 are directly formed serves as a pad surface, and those forming this pad surface serve as the connection pads 4 and the measurement pads 5.
[0031]
At this time, the thickness of the plating layer 22 is appropriately adjusted on the measurement pad 5 so that the uppermost surface of the plating layer 22 is formed at a position slightly recessed from the surface of the passivation film 18. Thus, a step D is formed between the passivation film 18 and the plating layer 22 on the measurement pad 5 so that the surface of the plating layer 22 is lower than the surface of the passivation film 18. The pad opening 19 leading to the connection pad 4 and the pad opening 20 leading to the measurement pad 5 correspond to the interlayer difference between the electrode pads (4, 5) (in this example, one layer by the interlayer insulating film 15). Then, the heights of the uppermost positions P1 and P2 of the plating layers 21 and 22 change. That is, the plating layer 21 on the connection pad 4 is arranged and formed at a position higher than the plating layer 22 on the measurement pad 5.
[0032]
Subsequently, solder bumps 23 and 24 are formed on the connection pads 4 and the measurement pads 5 via the plating layers 21 and 22, respectively, by supplying solder by an immersion method, as shown in FIG. . At this time, comparing the height positions of the solder bumps 23, 24 in the thickness direction of the element substrate 3, the solder bump 24 formed on the measuring pad 5 is better than the solder bump formed on the connecting pad 4. It is arranged at a position lower than 23 (a concave position). Therefore, on the element substrate 3, a step E is provided between the solder bumps 23 and 24 in accordance with the level difference therebetween.
[0033]
The plating layer 21 is formed on the connection pad 4 so as to slightly protrude from the pad opening 19, whereas the plating layer 22 is formed on the measurement pad 5 without protruding from the pad opening 20. As a result, on the measurement pad 5, the formation area of the plating layer 22 is suppressed within the opening area of the pad opening 20, and accordingly, the height of the solder bump 24 is also suppressed low. Incidentally, when the plating layer 22 is formed so as to protrude from the pad opening 20, the height of the solder bump 24 is also increased by enlarging the formation area of the plating layer 22.
[0034]
Through the above steps, the chip 1 having the structure shown in FIG. 2 is obtained. After the chip 1 is manufactured in a semiconductor wafer state, it is divided into individual pieces by dicing or the like.
[0035]
On the other hand, the chip 2 serving as the interposer is manufactured in a different process from the chip 1. By this chip manufacturing process, the connection pads 7 and the mounting pads 8 are formed on the main surface of the chip 2, and the plating layers (Ni, Au) of the electroless plating of Ni / Au are formed on the respective electrode pads (7, 8). A solder bump is formed via the under bump metal).
[0036]
After that, the chip 1 is mounted on the chip 2. Specifically, as shown in FIG. 5A, after supplying an appropriate amount of the sealing material 10 using a dispenser or the like into a region where the chip 1 is mounted on the chip 2, the chip 2 is turned upward, With the chip 1 facing down and the circuit surfaces facing each other, the solder bumps (not shown) of the chips 1 and 2 are brought into contact with each other in this state, and they are connected (flip chip connection) by heating and pressing. At this time, the solder bumps 24 on the measuring pads 5 of the chip 1 are arranged at positions sufficiently retracted from the chip 2 because the measuring pads 5 are formed below the uppermost layer. Therefore, at the time of flip-chip connection, the solder bumps 24 on the measurement pads 5 are kept away from the chip 2. Therefore, when the SIP having the COC structure is configured using the chips 1 and 2, the contact of the solder bumps 24 with the chip 2 can be reliably prevented.
[0037]
Thereafter, as shown in FIG. 5B, a solder ball 26 is fixed on the mounting pad 8 of the chip 2 with a flux 25. Next, as shown in FIG. 5C, the solder is melted by reflow to form a spherical solder electrode 11. The solder electrodes 11 serve as connection electrodes when the laminated structure of the chips 1 and 2 is mounted on the mother board 9. When the solder electrodes 11 are formed, the solder is supplied (pre-coated) on the mounting pads 8 of the chip 2 in a chip manufacturing process (solder bump forming process) in advance. And sufficient wettability can be obtained. Therefore, the solder electrodes 11 can be formed on the mounting pads 8 with sufficient adhesion (bonding strength). The diameter of the solder electrode 11 is made larger than the mounting height of the chip 1 with respect to the main surface of the chip 2 by appropriately setting the diameter of the solder ball 26 supplied on the mounting pad 8. . The semiconductor module (laminated structure) thus obtained is mounted on the mother substrate 9 in an upside-down state as shown in FIG.
[0038]
In the semiconductor device obtained by the above-described manufacturing method, in the manufacturing process of the chip 1, the connection pads 4 are formed by the second wiring patterns 17, and the measurement pads 5 are formed by the second wiring patterns 17. By forming the first wiring pattern 14A in the lower layer, the configuration is such that the measuring pad 5 is disposed below the connecting pad 4. Therefore, when the solder bumps 23 and 24 are formed on the connection pad 4 and the measurement pad 5 via the plating layers (under bump metal) 21 and 22, respectively, the interlayer between the connection pad 4 and the measurement pad 5 is formed. Due to the difference, the height position of the solder bump 24 is kept low. Thus, when the chip 1 is mounted on the chip 2, it is possible to flip-chip connect the chips 1 and 2 with the solder bumps 24 on the measurement pads 5 separated from the chip 2. .
[0039]
Regarding the height relationship between the solder bumps 23 and 24, if there is no problem when the chips 1 and 2 are flip-chip connected (that is, the solder bumps 24 do not come into contact with the surface of the chip 2), The solder bumps 24 may be arranged at substantially the same height as the solder bumps 23. However, in consideration of the reliability of flip-chip connection, the solder bumps 24 may be arranged at a lower position (lower position) than the solder bumps 23. desirable.
[0040]
Further, in the above embodiment, the case where the wiring layer on the chip 1 has a two-layer structure has been described as an example. However, the connection pads 4 are formed on the uppermost layer, and the measurement pads 5 are formed on the lower layer. For example, when the number of wiring layers on the chip 1 is four, the measurement pads 5 are formed on the first layer (lowest layer), the second layer, or the third layer, and the connection pads 4 are formed on the fourth layer. (Top layer). In particular, if the interlayer difference between the connection pad 4 and the measurement pad 5 is large, the height difference between the pad lamination positions is correspondingly large, which greatly contributes to the improvement of the reliability of flip chip connection.
[0041]
【The invention's effect】
As described above, according to the present invention, as a configuration of a semiconductor device having a laminated structure in which a semiconductor element is flip-chip connected on a circuit board, a second electrode pad is arranged in the thickness direction of the element substrate from the first electrode pad. By arranging them also in the lower layer, the height position of the protruding electrodes formed on the second electrode pads can be kept low, and good flip-chip connection can be performed.
[Brief description of the drawings]
FIG. 1 is a side sectional view showing an example of a configuration of a semiconductor device according to an embodiment of the present invention and a mounting structure thereof.
FIG. 2 is an enlarged sectional view of a main part of the semiconductor element.
FIG. 3 is a diagram (part 1) for explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention.
FIG. 4 is a view (No. 2) for explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention.
FIG. 5 is a view (No. 3) explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIG. 6 is a diagram illustrating a problem of the present invention.
[Explanation of symbols]
1, 2, chips (semiconductor elements), 3, 6, element substrates, 4, connection pads (first electrode pads), 5, measurement pads (second electrode pads), 14A, 14B, first Wiring pattern, 15 interlayer insulating film, 17 second wiring pattern, 18 passivation film, 19, 20 pad opening, 21, 22 plating layer (under bump metal), 23, 24 solder bump (protruding electrode) )

Claims (10)

A semiconductor device having a laminated structure in which a semiconductor element is flip-chip connected on a circuit board,
The semiconductor element is formed on an element substrate having a circuit formed in an effective element region on a main surface, a first electrode pad formed on the main surface of the element substrate, and formed on a main surface of the element substrate. A second electrode pad, and wherein the second electrode pad is arranged below the first electrode pad in a thickness direction of the element substrate. 2. The semiconductor device according to claim 1, wherein the circuit board is formed of another semiconductor element different from the semiconductor element. 2. The semiconductor device according to claim 1, wherein said first electrode pad is formed on a main surface of said element substrate for electrical connection with said circuit board. 2. The semiconductor device according to claim 1, wherein said second electrode pad is formed on a main surface of said element substrate for measuring electrical characteristics of said circuit. 2. The semiconductor device according to claim 1, wherein said first electrode pad is arranged in said effective element region on a main surface of said element substrate. The semiconductor element has a laminated structure in which a semiconductor element is flip-chip connected on a circuit board, and the semiconductor element is formed on an element substrate in which a circuit is formed in an effective element region on a main surface and on the main surface of the element substrate. A first electrode pad, and a second electrode pad formed on a main surface of the element substrate, wherein the second electrode pad is separated from the first electrode pad in a thickness direction of the element substrate. Is also a method of manufacturing a semiconductor device arranged in a lower layer,
As a manufacturing process of the semiconductor element,
A first step of forming a first wiring pattern on the element substrate;
A second step of forming an interlayer insulating film on the element substrate so as to cover the first wiring pattern;
A third step of forming a second wiring pattern on the interlayer insulating film or above the interlayer insulating film;
A fourth step of forming a passivation on the element substrate so as to cover the second wiring pattern;
By forming a pad opening communicating with the first wiring pattern and the second wiring pattern on the passivation film, the first wiring pattern forms the first electrode pad and the second wiring pattern. And a fifth step of forming the second electrode pad using a wiring pattern. 7. The method according to claim 6, further comprising a sixth step of forming a protruding electrode on each of the first electrode pad and the second electrode pad. In the sixth step, the first electrode pad and the second electrode pad are arranged such that the projecting electrode on the second electrode pad is lower than the projecting electrode on the first electrode pad. 8. The method according to claim 7, wherein the protruding electrodes are formed respectively. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the sixth step, solder bumps are formed as the protruding electrodes on the first electrode pad and the second electrode pad, respectively. 10. The manufacturing of a semiconductor device according to claim 9, wherein, in the sixth step, the solder bump is formed on the first electrode pad and the second electrode pad via an under bump metal, respectively. Method.

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