JPH0695543B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0695543B2 JPH0695543B2 JP59199565A JP19956584A JPH0695543B2 JP H0695543 B2 JPH0695543 B2 JP H0695543B2 JP 59199565 A JP59199565 A JP 59199565A JP 19956584 A JP19956584 A JP 19956584A JP H0695543 B2 JPH0695543 B2 JP H0695543B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- insulating film
- film
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明は、半導体装置及びその製造方法に係り、特に、
フリップ・チップ方式による半導体装置の製造方法に適
用して有効な技術に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
The present invention relates to a technique effective when applied to a semiconductor device manufacturing method by a flip chip method.
フリップ・チップ方式による半導体装置の製造方法は、
例えば保護膜として厚さ３乃至４μｍの石英スパッタ膜
を大規模集積回路（LSI）配線上に被着し、その後電極
部が形成される部分にホトエッチング法で穴（スルーホ
ール）あけを行い、アルミニウム（Al）接続用配線（パ
ツド）を露出している。The method of manufacturing a semiconductor device by the flip chip method is
For example, a quartz sputter film having a thickness of 3 to 4 μm is deposited on a large-scale integrated circuit (LSI) wiring as a protective film, and then a hole (through hole) is formed in a portion where an electrode portion is formed by a photoetching method. The aluminum (Al) connection wiring (pad) is exposed.
しかしながら、このようなフリップ・チップ方式による
半導体装置の製造方法では、エッチング時間が約60分も
かかるため、穴（スルーホール）ダレ幅は、片側で４乃
至20μｍのばらつきが発生し、微細化の適用が困難であ
るであることを、本発明者は発見した。However, in such a method of manufacturing a semiconductor device by the flip chip method, it takes about 60 minutes for etching, so that the width of the sag of the hole (through hole) varies from 4 to 20 μm on one side, resulting in miniaturization. The present inventor has found that the application is difficult.
なお、フリップ・チップ技術については、馬場玄式著、
「最新・電子デバイス事典」昭和51年３月20日発行、P3
63〜P364に記載されている。Regarding the flip chip technology, Baba Genshiki,
"Latest Electronic Device Encyclopedia," published March 20, 1976, P3
63 to P364.
本発明の目的は、半導体装置において、突起電極が微細
化しても突起電極と接続用配線とが電気的に良好に接続
可能とし、かつ半導体装置の信頼性を向上させることが
可能な技術を提供することにある。An object of the present invention is to provide a technique capable of electrically connecting a protruding electrode and a connection wiring in a good condition even in the case where the protruding electrode is miniaturized in the semiconductor device, and improving the reliability of the semiconductor device. To do.
本発明の他の目的は、半導体装置製造方法において、突
起電極の形成時間が短縮でき、かつ半導体装置の信頼性
の向上をはかることができる技術を提供することにあ
る。Another object of the present invention is to provide a technique capable of shortening the formation time of the protruding electrode and improving the reliability of the semiconductor device in the semiconductor device manufacturing method.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。The typical ones of the inventions disclosed in the present application will be outlined below.
すなわち、半導体装置において、突起電極の下地金属膜
と電気的に接続される接続用配線を、配線基板又は半導
体チップ保護用絶縁膜の表面と同じ高さの位置に形成す
ることにより、突起電極が微細化しても突起電極と接続
用配線とが電気的に良好に接続して半導体装置の信頼性
を向上させるようにしたものである。That is, in the semiconductor device, by forming the connection wiring electrically connected to the underlying metal film of the protruding electrode at the same height position as the surface of the wiring board or the insulating film for protecting the semiconductor chip, the protruding electrode is formed. Even when miniaturized, the protruding electrode and the connecting wiring are electrically connected well and the reliability of the semiconductor device is improved.
また、半導体装置製造方法において、接続用配線の上に
接続用配線と異なる金属からなる分離金属膜を形成し、
保護用絶縁膜を形成した後、前記分離金属膜をエッチン
グして保護用絶縁膜に穴（スルーホール）を形成するこ
となく、接続用配線を露出することにより、突起電極の
形成時間を短縮でき、かつ半導体装置の信頼性の向上を
はかることができるようにしたものである。Further, in the semiconductor device manufacturing method, a separation metal film made of a metal different from the connection wiring is formed on the connection wiring,
After forming the protective insulating film, by exposing the connecting wiring without etching the isolation metal film to form a hole (through hole) in the protective insulating film, the formation time of the protruding electrode can be shortened. In addition, the reliability of the semiconductor device can be improved.
以下、本発明の構成について、実施例とともに説明す
る。Hereinafter, the configuration of the present invention will be described together with examples.
なお、全図において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。In all the drawings, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.
〔実施例〕 第１図及び第２図は、本発明をフリップ・チップ方式に
よるマルチチップ型LSIに適用した一実施例の構成を説
明するための図であり、第１図は、そのリードを省略し
た一部断面図、第２図は、第１図の○印で囲んだ部分の
断面拡大図である。[Embodiment] FIGS. 1 and 2 are views for explaining the configuration of an embodiment in which the present invention is applied to a multi-chip type LSI by a flip chip system. FIG. FIG. 2 is an enlarged cross-sectional view of a part surrounded by a circle in FIG.
第１図において、１は例えばシリコン等の半導体からな
る配線基板であり、その配線基板１の上に配線が設けら
れている。その配線の接続部の上には例えば半田バンプ
等の突起電極２を介して複数のLSIチップ３がフェース
ダウンボンディングされている。In FIG. 1, reference numeral 1 is a wiring board made of a semiconductor such as silicon, and wiring is provided on the wiring board 1. A plurality of LSI chips 3 are face-down bonded on the connection portions of the wirings via protruding electrodes 2 such as solder bumps.
第２図において、４は配線基板１上に設けられた第１配
線であり、例えばアルミニウム（Al）等を用いる。５は
第１配線４間を絶縁するための第１層間絶縁膜、６は第
１層間絶縁膜５の上に設けられた第２配線であり、第１
層間絶縁膜５に穴（スルーホール）を介して第１配線に
接続されている。第２配線６は、例えばアルミニウム等
を用いる。７は第２層間絶縁膜、８は第２配線６の上に
設けられた接続用配線（パッド）、９は第２層間絶縁層
７の上に設けられた第３配線であり、それぞれ例えばア
ルミニウム等を用いる。10は分離用金属膜であり、接続
用配線８の高さを半導体チップ保護用絶縁膜11の表面と
略同じにして平坦化するためのものである。半導体チッ
プ保護用絶縁膜11は例えば石英スパッタ技術により被着
した石英膜を用いる。12は突起電極を形成するための下
地金属膜であり、例えばCr/Cr＋Cu/Cu/Auを用いる。２
は突起電極であり、例えば半田バンプを用いる。In FIG. 2, reference numeral 4 is a first wiring provided on the wiring board 1, and, for example, aluminum (Al) or the like is used. Reference numeral 5 is a first interlayer insulating film for insulating between the first wirings 4, and 6 is a second wiring provided on the first interlayer insulating film 5.
The interlayer insulating film 5 is connected to the first wiring through a hole (through hole). The second wiring 6 uses, for example, aluminum or the like. Reference numeral 7 is a second interlayer insulating film, 8 is a connecting wiring (pad) provided on the second wiring 6, and 9 is a third wiring provided on the second interlayer insulating layer 7. Etc. are used. Reference numeral 10 denotes a separating metal film for making the height of the connecting wiring 8 substantially the same as the surface of the semiconductor chip protecting insulating film 11 and flattening it. As the semiconductor chip protection insulating film 11, for example, a quartz film deposited by a quartz sputtering technique is used. Reference numeral 12 is a base metal film for forming the bump electrode, and for example, Cr / Cr + Cu / Cu / Au is used. Two
Is a bump electrode, for example, a solder bump is used.
次に、本実施例のマルチチップ型LSIの製造方法につい
て説明する。Next, a method of manufacturing the multi-chip type LSI of this embodiment will be described.
第３図乃至第５図は、本実施例のマルチチップ型LSIの
製造方法の各工程における要部断面図である。FIG. 3 to FIG. 5 are cross-sectional views of essential parts in each step of the method of manufacturing a multi-chip LSI of this embodiment.
本実施例のマルチチップ型LSI製造方法は、まず、第３
図に示すように、配線基板１の上に第１配線４を形成す
る。例えばシリコンウエハー表面にアルミニウムを直流
スパッタ技術により膜厚１μｍを被着し、その後ホトエ
ッチング技術により所定形状に加工して形成する。The multi-chip type LSI manufacturing method according to the present embodiment firstly includes a third method.
As shown in the figure, the first wiring 4 is formed on the wiring board 1. For example, aluminum is deposited on the surface of a silicon wafer by a DC sputtering technique to a film thickness of 1 μm, and then processed into a predetermined shape by a photoetching technique.
次に、第１層間絶縁膜５を配線基板１の上に形成する。
例えば化学的気相析出（CVD）技術によりシリコンウエ
ハー表面に酸化シリコン（SiO2）膜を堆積させ、その後
ホトエッチング技術により所定の位置に穴あけを行い、
アルミニウム配線の接続部分を露出させる。Next, the first interlayer insulating film 5 is formed on the wiring board 1.
For example, a chemical vapor deposition (CVD) technique is used to deposit a silicon oxide (SiO 2 ) film on the surface of a silicon wafer, and then a photoetching technique is used to make holes at predetermined positions.
The connection part of the aluminum wiring is exposed.
次に、第２配線６を第１配線４と同様の手法で加工して
形成する。例えばアルミニウム配線を形成する。Next, the second wiring 6 is processed and formed in the same manner as the first wiring 4. For example, aluminum wiring is formed.
次に、第４図に示すように、第２配線６の上に第２層間
絶縁膜７を形成する。例えば高周波（Rf）スパッタ技術
により、石英膜の絶縁層を第２アルミニウム配線の表面
に被着させる。その後に、ホトエッチング技術により所
定の位置に穴あけして、第２配線６の接続部分を露出さ
せる。Next, as shown in FIG. 4, a second interlayer insulating film 7 is formed on the second wiring 6. An insulating layer of quartz film is deposited on the surface of the second aluminum wiring by, for example, a radio frequency (Rf) sputtering technique. After that, a hole is formed at a predetermined position by a photoetching technique to expose the connection portion of the second wiring 6.
次に、第２配線６の接続部分及び第２層間絶縁膜７の上
に接続用配線８及び第３アルミニウム配線９をそれぞれ
形成する。例えば直流スパッタ技術によりアルミニウム
膜厚２μｍを被着する。Next, the connection wiring 8 and the third aluminum wiring 9 are formed on the connection portion of the second wiring 6 and the second interlayer insulating film 7, respectively. For example, an aluminum film having a thickness of 2 μm is deposited by the DC sputtering technique.
次に、接続用配線８及び第３配線９の上に分離用金属膜
10を形成する。例えば直流スパッタ技術により、タンタ
ル（Ta）膜を膜厚0.1〜0.2μｍ被着する。Next, a separation metal film is formed on the connection wiring 8 and the third wiring 9.
Forming 10. For example, a tantalum (Ta) film is deposited to a thickness of 0.1 to 0.2 μm by the DC sputtering technique.
次に、例えば、ポジ系のホトレジストを２μｍ塗布し、
通常のホトリソ技術を用いてマスク13を形成する処理
（感光〜現像）を行う。その後、プラズマエッチング技
術により、四フッ化炭素（CF4）ガスに４〜８％の酸素
（O2）を混合した混合ガスで分離用金属膜10をエッチン
グする。Next, for example, a positive photoresist is applied to a thickness of 2 μm,
Processing (photosensitization to development) for forming the mask 13 is performed by using a normal photolithography technique. After that, the separation metal film 10 is etched by a plasma etching technique with a mixed gas in which carbon tetrafluoride (CF 4 ) gas is mixed with 4 to 8% of oxygen (O 2 ).
次に、四塩化炭素（Ccl4）ガスに４〜８％の酸素を混合
した混合ガスで第３層配線用アルミニウム膜をエッチン
グして接続用配線８及び第３配線９を形成する。その後
ホトレジスト膜のマスク13を剥離剤で除去する。Next, the third layer wiring aluminum film is etched with a mixed gas in which carbon tetrachloride (Ccl 4 ) gas is mixed with 4 to 8% oxygen to form the connection wiring 8 and the third wiring 9. After that, the mask 13 of the photoresist film is removed with a release agent.
次に、第５図に示すように、半導体チップ保護用絶縁膜
11例えば石英膜を、基板バイアス型の高周波スパッタ技
術により、２〜３μｍ被着すると、例えば、接続用配線
８の線幅が第３配線９の線幅により小さく、その比率が
約10分の１であると、接続用配線８の上の石英膜は第３
配線９の上の膜厚よりも薄くなり、接続用配線８の肩部
が露出する。Next, as shown in FIG. 5, an insulating film for protecting the semiconductor chip
11 For example, when a quartz film is deposited by 2 to 3 μm by the substrate bias type high frequency sputtering technique, for example, the line width of the connection wiring 8 is smaller than the line width of the third wiring 9, and the ratio thereof is about 1/10. Then, the quartz film on the connection wiring 8 is the third
It becomes thinner than the film thickness on the wiring 9, and the shoulder portion of the connection wiring 8 is exposed.
次に、フッ酸：フッ化アンモニウム：水＝1:20:7の容積
比で混合されたフッ酸・フッ化アンモニウム・水のエッ
チング液でソフトエッチングを行い、確実に接続用配線
８の肩部を露出させる。Next, soft etching is performed with an etching solution of hydrofluoric acid / ammonium fluoride / water mixed at a volume ratio of hydrofluoric acid: ammonium fluoride: water = 1: 20: 7, and the shoulder portion of the connection wiring 8 is surely removed. Expose.
次に、フッ酸：硝酸＝1:20の容積比で混合されたフッ酸
・硝酸混合液のエッチング液により、接続用配線８の上
の分離用金属膜10であるタンタル膜14をエッチングす
る。これにより分離用金属10の上に形成されている絶縁
膜（保護用絶縁膜11の形成時に形成された絶縁膜）15を
除去され、接続用配線８が露出される。Next, the tantalum film 14, which is the separating metal film 10 on the connection wiring 8, is etched with an etching solution of a hydrofluoric acid / nitric acid mixed solution mixed at a volume ratio of hydrofluoric acid: nitric acid = 1: 20. As a result, the insulating film (the insulating film formed when the protective insulating film 11 is formed) 15 formed on the separating metal 10 is removed, and the connection wiring 8 is exposed.
次に、第２図に示すように、配線基板１と半導体チップ
３とを接続するための半田バンプ下地金属膜12及び突起
電極２を形成し、この突起電極２を介して半導体チップ
３を配線基板１に電気的に接続してマルチチップ型LSI
が完成する。Next, as shown in FIG. 2, a solder bump base metal film 12 for connecting the wiring substrate 1 and the semiconductor chip 3 and a protruding electrode 2 are formed, and the semiconductor chip 3 is wired via the protruding electrode 2. A multi-chip type LSI that is electrically connected to the substrate 1
Is completed.
なお、配線基板１の保護用絶縁膜11のスパッタ、例えば
石英の高周波スパッタ技術におけるバイアス条件によっ
ては、保護用絶縁膜11の穴（スルーホール）あけ用のホ
トレジストを用いたマスク形成工程をなくすることがで
き、直接石英スパッタのソフトエッチングするだけで、
接続用配線を露出さることもできる。Incidentally, depending on the bias condition in the sputtering of the protective insulating film 11 of the wiring substrate 1, for example, the high frequency sputtering technique of quartz, the mask forming process using the photoresist for forming the hole (through hole) of the protective insulating film 11 is eliminated. You can do it by just soft etching quartz spatter directly.
The connecting wiring can be exposed.
以上の説明からわかるように、この実施例によれば、配
線基板１と半導体チップ３とを接続する際に、配線基板
１の保護用絶縁膜11に穴（スルーホール）を形成しない
ので、穴形状寸法のダレ幅のバラツキをなくすることが
でき、かつ突起電極２間の寸法を約30μｍ程度縮小でき
る。また、突起電極２の径も約30μｍ程度小さくするこ
とができるので、突起電極２の高集積化がはかれる。As can be seen from the above description, according to this embodiment, no hole (through hole) is formed in the protective insulating film 11 of the wiring board 1 when the wiring board 1 and the semiconductor chip 3 are connected. It is possible to eliminate the variation in the sagging width of the geometrical dimension and reduce the dimension between the protruding electrodes 2 by about 30 μm. Further, since the diameter of the bump electrode 2 can be reduced by about 30 μm, the bump electrode 2 can be highly integrated.
また、配線基板１の保護用絶縁膜11のエッチング作業の
短縮時間はバッチ当り約50〜60分短縮することができ
る。また、これにより配線の電気的特性の変化を低減し
て安定した電気的特性を得ることができる。In addition, the shortening time of the etching operation of the protective insulating film 11 of the wiring board 1 can be shortened by about 50 to 60 minutes per batch. In addition, this makes it possible to reduce changes in the electrical characteristics of the wiring and obtain stable electrical characteristics.
また、接続部の接続用配線８を複数個に分割して形成す
ることにより、たとえ一つ接続用配線が接続不良であっ
て全体としては電気的に接続されているので、接続部の
信頼性を向上させることができる。Further, since the connecting wiring 8 of the connecting portion is formed by being divided into a plurality of portions, even if one connecting wiring has a poor connection and is electrically connected as a whole, the reliability of the connecting portion is improved. Can be improved.
以上説明したよに、本願で開示した新規な技術によれ
ば、次に述べるような効果を得ることができる。As described above, according to the novel technique disclosed in the present application, the following effects can be obtained.
（１）配線基板と半導体チップとを接続する際に、配線
基板及び半導体チップの保護用絶縁膜に穴（スルーホー
ル）を形成しないので、穴形状寸法のダレ幅のバラツキ
をなくすることができる。(1) Since no hole (through hole) is formed in the protective insulating film of the wiring board and the semiconductor chip when connecting the wiring board and the semiconductor chip, it is possible to eliminate the variation in the sagging width of the hole shape dimension. .
（２）前記（１）により、突起電極間の寸法を縮小でき
る。(2) Due to the above (1), the dimension between the protruding electrodes can be reduced.
（３）前記（１）により、突起電極の径を小さくするこ
とができる。(3) Due to the above (1), the diameter of the protruding electrode can be reduced.
（４）前記（１）乃至（３）により、半導体装置の電極
の高集積化をはかることができる。(4) Due to the above (1) to (3), high integration of the electrodes of the semiconductor device can be achieved.
（５）前記（１）により、配線基板又は半導体チップの
保護用絶縁膜のエッチング作業の時間を短縮することが
できる。(5) According to the above (1), it is possible to shorten the time for etching the protective insulating film of the wiring board or the semiconductor chip.
（６）接続部の接続用配線を複数個に分割して形成する
ことにより、たとえ一つ接続用配線が接続不良であって
全体としては電気的に接続されているので、接続部の信
頼性を向上させることができる。(6) By forming the connecting wiring of the connecting portion by dividing it into a plurality of pieces, even if one connecting wiring has a poor connection and is electrically connected as a whole, the reliability of the connecting portion is improved. Can be improved.
（７）前記（１）乃至（６）により、半導体装置の信頼
性の向上及び高集積化をはかることができる。(7) Due to the above (1) to (6), it is possible to improve the reliability and the degree of integration of the semiconductor device.
以上、本発明を実施例にもとずき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
はいうまでもない。The present invention has been specifically described above based on the embodiments.
It is needless to say that the present invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention.
なお、前記実施例は、本発明をマルチチップ型LSIの配
線基板の接続用配線の形成技術に適用した例について説
明したが、本発明は、半導体チップ側の接続用配線の形
成技術にも適用できることは勿論である。Although the above-described embodiments have been described with reference to the examples in which the present invention is applied to the technique for forming the wiring for connection of the wiring substrate of the multi-chip type LSI, the present invention is also applied to the technique for forming the wiring for connection on the semiconductor chip side. Of course you can.
第１図及び第２図は、本発明をフリップ・チップ方式に
よるマルチチップ型LSIに適用した一実施例の構成を説
明するための図であり、 第１図は、そのリードを省略した一部断面図、 第２図は、第１図の○印で囲んだ部分の断面拡大図、 第３図乃至第５図は、本実施例のマルチチップLSIの製
造方法の各工程における要部断面図である。 図中、１…配線基板、２…突起電極、３…LSIチップ、
４…第１配線、５…第１層間絶縁膜、６…第２配線、７
…第２層間絶縁膜、８…接続用配線、９…第３配線、10
…分離用金属膜、11…保護用絶縁膜、12…下地金属膜、
13…マスク、14…分離除去される分離用金属膜、15…分
離除去される絶縁物である。1 and 2 are views for explaining the configuration of an embodiment in which the present invention is applied to a flip-chip type multi-chip type LSI, and FIG. Sectional views, FIG. 2 is an enlarged sectional view of a portion surrounded by a circle in FIG. 1, and FIGS. 3 to 5 are sectional views of main parts in respective steps of the method for manufacturing a multi-chip LSI of this embodiment. Is. In the figure, 1 ... Wiring board, 2 ... Projection electrode, 3 ... LSI chip,
4 ... 1st wiring, 5 ... 1st interlayer insulation film, 6 ... 2nd wiring, 7
... second interlayer insulating film, 8 ... connection wiring, 9 ... third wiring, 10
… Separating metal film, 11… Protective insulating film, 12… Base metal film,
13 ... Mask, 14 ... Separation / removal metal film, 15 ... Separation / removal insulator.
Claims (4)
半導体チップにおける突起電極の下地金属膜と接続用配
線とを接着させて基板と半導体チップを電気的に接続し
た半導体装置において、前記突起電極の下地金属膜と電
気的に接続される接続用配線を、配線基板又は半導体チ
ップの保護用絶縁膜の表面と略同じ高さの位置に形成し
たことを特徴とする半導体装置。1. A semiconductor device for mounting a semiconductor chip on which a wiring is provided, or a semiconductor device in which a substrate and a semiconductor chip are electrically connected by adhering a base metal film of a protruding electrode on the semiconductor chip and a connecting wiring. A semiconductor device, wherein a connection wiring electrically connected to a base metal film of an electrode is formed at a position substantially the same height as a surface of a protective insulating film of a wiring substrate or a semiconductor chip.
特徴する特許請求の範囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, wherein the connection wiring is divided into a plurality of pieces.
上に第１配線を複数形成する工程と、該第１配線の各線
間を絶縁する第１層間絶縁膜を形成する工程と、該第１
層間絶縁膜の上に前記第１配線と電気的に接続する第２
配線を形成する工程と、該第２配線とその一端部が電気
的に接続し、その他端部が後段工程で形成される保護用
絶縁膜の表面と略同じ高さとなるように接続用配線を形
成する工程と、該接続用配線の他端部の上に接続用配線
と異なる金属からなる分離金属膜を形成する工程と、保
護用絶縁膜をその表面が前記接続用配線の高さと略同じ
になるような膜厚に形成する工程と、該工程の後前記分
離金属膜をエッチングして前記接続用配線を露出させる
工程と、該露出部に突起電極の下地金属膜を形成する工
程を具備したことを特徴とする半導体装置製造方法。3. A step of forming a plurality of first wirings on a semiconductor chip mounting substrate or a semiconductor chip; a step of forming a first interlayer insulating film for insulating between the respective lines of the first wirings;
A second electrically connected to the first wiring on the interlayer insulating film;
The connection wiring is formed so that the second wiring and one end thereof are electrically connected to each other and the other end is substantially level with the surface of the protective insulating film formed in the subsequent step. A step of forming, a step of forming an isolation metal film made of a metal different from that of the connection wiring on the other end of the connection wiring, and a surface of the protective insulating film is substantially the same as the height of the connection wiring. And a step of etching the separation metal film to expose the connection wiring, and forming a base metal film of the protruding electrode on the exposed portion. A method of manufacturing a semiconductor device characterized by the above.
を特徴とする特許請求の範囲第３項記載の半導体装置製
造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein the separation metal film is formed of tantalum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59199565A JPH0695543B2 (en) | 1984-09-26 | 1984-09-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59199565A JPH0695543B2 (en) | 1984-09-26 | 1984-09-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6178140A JPS6178140A (en) | 1986-04-21 |
| JPH0695543B2 true JPH0695543B2 (en) | 1994-11-24 |
Family
ID=16409941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59199565A Expired - Lifetime JPH0695543B2 (en) | 1984-09-26 | 1984-09-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0695543B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7952206B2 (en) * | 2005-09-27 | 2011-05-31 | Agere Systems Inc. | Solder bump structure for flip chip semiconductor devices and method of manufacture therefore |
| US7985671B2 (en) * | 2008-12-29 | 2011-07-26 | International Business Machines Corporation | Structures and methods for improving solder bump connections in semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5662398A (en) * | 1979-10-26 | 1981-05-28 | Nippon Electric Co | Method of manufacturing high density multilayer board |
| JPS58157147A (en) * | 1982-03-12 | 1983-09-19 | Mitsubishi Electric Corp | Hybrid integrated circuit substrate |
| JPS59135796A (en) * | 1983-01-24 | 1984-08-04 | 日本電気株式会社 | High density multilayer circuit board |
-
1984
- 1984-09-26 JP JP59199565A patent/JPH0695543B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5662398A (en) * | 1979-10-26 | 1981-05-28 | Nippon Electric Co | Method of manufacturing high density multilayer board |
| JPS58157147A (en) * | 1982-03-12 | 1983-09-19 | Mitsubishi Electric Corp | Hybrid integrated circuit substrate |
| JPS59135796A (en) * | 1983-01-24 | 1984-08-04 | 日本電気株式会社 | High density multilayer circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6178140A (en) | 1986-04-21 |
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