JPS6112047A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6112047A JPS6112047A JP59131876A JP13187684A JPS6112047A JP S6112047 A JPS6112047 A JP S6112047A JP 59131876 A JP59131876 A JP 59131876A JP 13187684 A JP13187684 A JP 13187684A JP S6112047 A JPS6112047 A JP S6112047A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating
- solder
- bump electrode
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01052—Tellurium [Te]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、バンプ電極を有する半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having bump electrodes.
（従来の技術）
従来、バンプ電極の形成方法に関する公知文献として、
たとえば、ＩＦＪＥＩ８１ ＣＨ１６７１−７／８１
／１００００−０１４９ページ１４９〜１５５などに記
載されている。(Prior Art) Conventionally, as a known document regarding a method for forming a bump electrode,
For example, IFJEI81 CH1671-7/81
/10000-0149 pages 149-155.
従来、半導体フリップチップ素子のハンダ電極を形成す
る方法としては、選択蒸着法、電気メツキ法およびハン
ダが−ル法、ハンダディップ法がある。Conventionally, methods for forming solder electrodes of semiconductor flip-chip devices include selective vapor deposition, electroplating, solder dipping, and solder dipping.
このうち前者の選択蒸着法は、蒸着時間が非常に長いこ
と、蒸着膜厚の制御が困難であること、および製造装置
の投資が非常にかかるなどの理由で一般には行なわれて
いない。Among these, the former selective vapor deposition method is generally not carried out because the vapor deposition time is very long, it is difficult to control the vapor deposited film thickness, and it requires a large investment in manufacturing equipment.
従来の電気メツキ法による半導体フリップチップ素子の
バンプ電極形成法の一例を第２図に示す。FIG. 2 shows an example of a method for forming bump electrodes of a semiconductor flip-chip device using the conventional electroplating method.
第２図−）に示すように、半導体基板１（以下Ｓｔ基板
と云う）上に形成された、熱酸化膜（以下Ｓｉｎ。As shown in FIG. 2-), a thermal oxide film (hereinafter referred to as "Sin") is formed on a semiconductor substrate 1 (hereinafter referred to as "St substrate").
膜と云う）２の上に、バンプ電極を形成すべき場所に、
Ａｌ電極パッド３を形成し、さらにＣＶＤ法にて、パッ
シベーション膜４を成長させた後、Ｍを極パッド３上に
スルーホールを開孔する。(referred to as the film) 2, at the place where the bump electrode is to be formed,
After forming an Al electrode pad 3 and growing a passivation film 4 by CVD, a through hole is formed on the M electrode pad 3.
次に、第２図（ｂ）に示すように、Ａ１．−Ｎｉ合金属
５、Ｎｉ層６を順次蒸着する。Next, as shown in FIG. 2(b), A1. -Ni alloy 5 and Ni layer 6 are sequentially deposited.
次に、第２図（Ｃ）に示すように、レジストなどにて、
マスキングを行なって、バンプ電極が形成される個所以
外のＮｉ層６をエツチングする。Next, as shown in FIG. 2(C), with a resist etc.
Masking is performed and the Ni layer 6 is etched in areas other than those where bump electrodes are to be formed.
次に、第２図（ｄ）に示すように、通常のホ） ＩＪソ
工程により、レジスト７にて、バンプ電極が形成される
個所以外を覆う。Next, as shown in FIG. 2(d), areas other than those where bump electrodes are to be formed are covered with resist 7 by a normal IJ process.
次に、第２図（ｅ）に示すように、Ａｌ−Ｎｉ合金層５
を電流の導電層として、電気メッキ法により、銅メッキ
層８を形成する。この銅メッキ層８は、通常１０μｍ程
度の厚さである。Next, as shown in FIG. 2(e), the Al-Ni alloy layer 5
A copper plating layer 8 is formed by electroplating using as a current conductive layer. This copper plating layer 8 usually has a thickness of about 10 μm.
その後、第２図（ｆ）に示すように、ノ・ンダメツキ９
−１を行ない、バンプ電極を形成する（９−２は後述す
る）。このハンダメッキ９−１の厚さは、４０〜６０μ
ｍ程度である。After that, as shown in FIG. 2(f), No.
-1 is performed to form bump electrodes (step 9-2 will be described later). The thickness of this solder plating 9-1 is 40 to 60μ
It is about m.
次に、第２図（ロ））に示すように、メッキ用のレジス
ト７を通常の溶剤にて除去する。その後、第２図（６）
に示すように、再度通常のホ） ＩＪソ工程によシレジ
スト７にて、バンプ電極のハンダメッキ９−１を覆うよ
うに形成する。Next, as shown in FIG. 2(b), the plating resist 7 is removed using a normal solvent. After that, Figure 2 (6)
As shown in FIG. 3, a resist 7 is formed again by the usual IJ process so as to cover the solder plating 9-1 of the bump electrode.
次に、通常のエツチング液にて、レジスト７で覆ってい
る個所以外のＡｌ−Ｎｉ合金層５を除去する。Next, the Al--Ni alloy layer 5 other than the portions covered by the resist 7 is removed using an ordinary etching solution.
次に、第２図（１）に示すように、レジスト７を溶剤に
て除去した後、通常３４０〜３５０℃の温度でハンダメ
ッキ９−１を溶解させて、円板状のパンダ電極を半球状
にさせる。ここで、中間金属層どしてのＡＩ −Ｎｉ合
金層５は、５ｉｎ２膜２およびＭ電極パッド３への密着
金属で、中間金属層としてのＮｉ層６および銅メッキ層
８は、Ｍ電極パッド３とハンダメッキ９−１との相互拡
散を防止する拡散バリヤ層である。ここでは、銅メ・ツ
キ層８を拡散バリヤメッキ層と呼ぶことにする。Next, as shown in FIG. 2 (1), after removing the resist 7 with a solvent, the solder plating 9-1 is melted at a temperature of usually 340 to 350°C, and a disk-shaped panda electrode is formed into a hemispherical shape. make it into a shape. Here, the AI-Ni alloy layer 5 as an intermediate metal layer is a metal that adheres to the 5in2 film 2 and the M electrode pad 3, and the Ni layer 6 and the copper plating layer 8 as the intermediate metal layer are the metal that adheres to the M electrode pad 3. This is a diffusion barrier layer that prevents mutual diffusion between solder plating 9-1 and solder plating 9-1. Here, the copper plating layer 8 will be referred to as a diffusion barrier plating layer.
この第２図の製造方法は、以下述べる欠点を持っている
。その一つは、第２図（６）に示すＡｌ−Ｎｉ合金層５
を除去する工程において、ノ・ンダメツキ９−１が一緒
にエツチングされてしまう点である。The manufacturing method shown in FIG. 2 has the following drawbacks. One of them is the Al-Ni alloy layer 5 shown in FIG. 2 (6).
The problem is that in the process of removing the etch marks 9-1, the marks 9-1 are etched together.
この原因は、銅メッキ層８の厚さ１０μｍ程度であり、
その上に、ハンダメッキ９−１の厚さが４０〜６０μｍ
となるので、バンプ電極の高さは、５０〜７０μｍと非
常に高くなる。The reason for this is that the thickness of the copper plating layer 8 is about 10 μm.
On top of that, the thickness of solder plating 9-1 is 40 to 60 μm.
Therefore, the height of the bump electrode is very high, 50 to 70 μm.
通常のホトリン条件では、バンプ電極全体をレジストで
覆うことは、困難であるために、ハンダメッキ９−１の
側面や上部が露出してしまうので、Ａ／Ｌ−Ｎｉ合金層
５を除去する工程において、用いられるエツチング液に
よって、前記露出したハンダメッキ９−１の部分がエツ
チングされる。ハンダメッキ９−１がエツチングされる
と第２図（ｉ）に示すハンダバンプの球状処理がうまく
行なえず、フリップチップのボンディング性に、悪影響
を与える。Under normal photolithography conditions, it is difficult to cover the entire bump electrode with resist, and the sides and top of the solder plating 9-1 are exposed, so the process of removing the A/L-Ni alloy layer 5 In this step, the exposed portion of the solder plating 9-1 is etched by the etching solution used. If the solder plating 9-1 is etched, the solder bump cannot be properly shaped into a spherical shape as shown in FIG. 2(i), which adversely affects the bonding properties of the flip chip.
このハンダメッキ９−１が、エツチングされてしまうこ
とを防止する方法として、第２図（ｆ）に示すようにハ
ンダメッキ９−１のメッキ終了後、連続して錫（Ｓｎ
）メッキ９−２を行う方法が既に考えられているが、第
２図□□□）に示すように、パン゛プ電極の底面部分は
、ハンダメッキ９−１および銅メッキ層８が露出してし
まう。As a method to prevent the solder plating 9-1 from being etched, as shown in FIG. 2(f), after the solder plating 9-1 is finished, tin (Sn
) A method of plating 9-2 has already been considered, but as shown in Fig. 2 □□□), the solder plating 9-1 and the copper plating layer 8 are exposed at the bottom of the pump electrode. I end up.
このため、たとえハンダメッキ９−１のメッキ終了後、
連続して錫（Ｓｎ ）メッキ９−２を施しても、第２図
■に示すような、ホトリソ工程は必要となる。したがっ
て、前記両者の方法では、第２図（５）に示すＡＬ −
Ｎｉ合金層５を除去する工程において、レジスト７は、
バンプ電極の下部にまで入っている。For this reason, even after completing solder plating 9-1,
Even if tin (Sn) plating 9-2 is applied continuously, a photolithography process as shown in FIG. 2 (2) is still necessary. Therefore, in both of the above methods, the AL-
In the step of removing the Ni alloy layer 5, the resist 7 is
It extends to the bottom of the bump electrode.
この状態では、レジスト７のパターンが、ノヘンダメツ
キ９−１および錫メッキ層９−２よシ外側または同程度
になっているため、ＡＬ−Ｎｉ合金層５のエツチング後
のパターンは、レジストパターンと同様にハンダメッキ
９−１、および錫メッキ層９−２よシ外側または、同程
度にパターンが形成される（第２図（６））。In this state, the pattern of the resist 7 is on the outside or on the same level as the rough plating 9-1 and the tin plating layer 9-2, so the pattern of the AL-Ni alloy layer 5 after etching is similar to the resist pattern. A pattern is formed on the outside or to the same extent as the solder plating layer 9-1 and the tin plating layer 9-2 (FIG. 2 (6)).
このように形成されたバンプ電極を第２図（ｉ）に示す
ように、レジスト７を除去し、３４０〜３５０℃の温度
で、ノ・ンダメツキ９−１、および錫メッキ層９−２を
溶解させて円板状のバンプ電極を半球状にさせると、前
記ＡＬ −Ｎｉ合金層５が、半球状になったバンプ°電
極よシ外側へ出てしまうために、バンプ電極の間隔を狭
くすると、バンプ電極間が、Ａｌ−Ｎｉ合金層５によっ
て、電気的に短絡してしまう。したがって、バンプ電極
間を狭くすることが不可能であるため、高密度のバンプ
電極を形成することができなかった。As shown in FIG. 2(i), the resist 7 is removed from the thus formed bump electrode, and the non-damaged plate 9-1 and the tin plating layer 9-2 are melted at a temperature of 340 to 350°C. If the disk-shaped bump electrode is made into a hemispherical shape, the AL-Ni alloy layer 5 will protrude to the outside of the hemispherical bump electrode. Therefore, if the spacing between the bump electrodes is narrowed, An electrical short circuit occurs between the bump electrodes due to the Al-Ni alloy layer 5. Therefore, it is impossible to narrow the distance between the bump electrodes, so it has been impossible to form high-density bump electrodes.
以上は、第２図に示したように、ハンダバンプ電極の形
成法として、Ａｌ−Ｎｉ −Ｃｕ −Ｐｂ／Ｓｎの金属
構成を示したが、その他の代表的金属構成としてＴｉ
−Ｃｕ −Ｎｉ −Ｐｂ／’Ｓｎ 、 Ｃｒ−Ｃｕ −
Ｎｉ−Ｐｂ／Ｓｎがある。As shown in FIG. 2, the metal composition of Al-Ni-Cu-Pb/Sn has been shown as a method for forming solder bump electrodes, but other typical metal compositions include Ti.
-Cu -Ni -Pb/'Sn, Cr-Cu -
There is Ni-Pb/Sn.
（発明が解決しようとする問題点）
これらの例の場合でも、Ｔｉ 、 Ｃｕ 、 Ｃｒ
をエツチングする際に、前述したようなハンダ層がエツ
チングされ、また、Ｔｉ 、 Ｃｕ 、 Ｃｒ１Ｅ半球
状化したハンダバンプ電極よシ外側へ形成されるので、
高密度のバンプ電極を得られることは不可能である。(Problems to be solved by the invention) Even in these examples, Ti, Cu, Cr
When etching, the solder layer as described above is etched, and Ti, Cu, Cr1E hemispherical solder bump electrodes are formed on the outside.
It is not possible to obtain a high density of bump electrodes.
この発明の目的は、メッキ用の電極導通層を除去する工
程において、ハンダメッキ層がエツチングされることを
除去できるとともに、′バンプ電極の底部にレジストを
挿入する工程を不要にでき、半球状化したバンプ電極□
よシ外側へメッキ用の電流導通層が、形成されない半導
体装置の製造方法を得ることにある。The purpose of this invention is to eliminate the etching of the solder plating layer in the process of removing the electrode conductive layer for plating, and also to eliminate the need for the process of inserting a resist into the bottom of the bump electrode. Bump electrode □
Another object of the present invention is to obtain a method for manufacturing a semiconductor device in which a current conductive layer for plating is not formed on the outside.
（問題点を解決するための手段）
この発明の竺一点は、ハンダメッキを形成後、メッキ保
護用のレジストを溶剤で除去した後、ハンダ組成で耐薬
品性に強い、錫をハンダメッキおよび銅メツキ層表面に
、薄く被着させることにより、メッキ用電流導通層の除
去工程に用いられるエツチング液に対してハンダメッキ
および、銅メッキ層の保護を行うことにある。(Means for Solving the Problems) The main point of this invention is that after forming solder plating, removing the resist for protecting the plating with a solvent, applying tin to the solder plate and copper, which has a strong chemical resistance due to the solder composition. By applying a thin layer to the surface of the plating layer, the solder plating and copper plating layer are protected from the etching solution used in the process of removing the current conductive layer for plating.
（作用）
このようにすれば、ハンダバンプ電極の半球状化が良好
に行われるようになり、バンプ電極の底部をレジストで
榎う工程も不要となシ、しかもメッキ用の電流導通層が
バンプ電極よυ外側へ形成されることがなくなる。(Function) By doing this, the solder bump electrode can be well formed into a hemispherical shape, and there is no need for the step of covering the bottom of the bump electrode with a resist. It will no longer form outward.
（実施例）
以下、この発明の半導体装置の製造方法の実施例につい
て図面に基づき説明す右。第１図（ａ）ないし第１図（
ｃ）はその一実施例の工程説明図である。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1(a) to Figure 1(
c) is a process explanatory diagram of one example.
この第１図仏）〜第１図（ｃ）において、第２図（ａ）
〜第２図（１）と同一部分は重複を避けるために、同一
符号を付してその説明を省略し、第２図←）〜第２図（
ｉ）と異なる部分を重点的に述べる。In this figure 1 Buddha) to figure 1 (c), figure 2 (a)
~ In order to avoid duplication, the same parts as in Figure 2 (1) are given the same reference numerals and their explanations are omitted.
I will focus on the parts that differ from i).
第２図伝）〜第２図（ロ））までの工程、すなわち、メ
ッキによシハンダメッキ層９−１を形成するところまで
の工程は、この発明の半導体装置あ製造方法と変らない
ので、説明および断面図は省略する。The steps from FIG. 2) to FIG. 2(b), that is, the steps up to forming the solder plating layer 9-1 by plating, are the same as the method for manufacturing the semiconductor device of the present invention, so they will be explained below. and cross-sectional views are omitted.
以下に述べる点が第２図（ＩＬ）〜第２図（１）と異な
シ、この実施例の特徴をなすものである。すなわち、ハ
ンダメッキ９−１を形成し、レノストを除去した後（第
２図（ｇ））第１図（ａ）に示すように電気メツキ法ま
たは無電界メッキ法などの方法を用いて、ハンダバンプ
電極の上面および側面だけでなく、ハンダメッキ９−１
の下部および銅メッキ層８、中間金属層としてのＮ１層
６の全面を錫メッキ層９−２で覆う。この錫メッキ層９
−２の厚さはハンダの組成が変化しない程度で、しかも
メッキ膜に欠陥が無い観点から、２μｍ以上から１０μ
ｍ以下の厚さが選ばれる。錫メッキ層９−２は、下地金
属の密着性よシ、選択的に、ハンダバンプ電極全面およ
び銅メッキ層８、Ｎ１層６に被着される。The following points are different from those in FIGS. 2(IL) to 2(1) and are the features of this embodiment. That is, after forming the solder plating 9-1 and removing the renost (FIG. 2(g)), solder bumps are formed using a method such as electroplating or electroless plating as shown in FIG. 1(a). Solder plating not only on the top and sides of the electrode 9-1
The lower part of the copper plating layer 8 and the entire surface of the N1 layer 6 as an intermediate metal layer are covered with a tin plating layer 9-2. This tin plating layer 9
-2 thickness is from 2μm or more to 10μm from the viewpoint that the solder composition does not change and there are no defects in the plating film.
A thickness of less than m is chosen. The tin plating layer 9-2 is selectively deposited on the entire surface of the solder bump electrode, the copper plating layer 8, and the N1 layer 6 in order to improve the adhesion of the underlying metal.
次に、第１図（ｂ）に示すように、Ａｌ−Ｎｉ合金層５
をエツチング液に浸して、バンプ電極部以外のり−Ｎｉ
合金層５を除去する。ＡＬ −Ｎｉ合金層５を除去する
エツチング液ｉ、リン酸、硝酸、氷酢酸、硫酸、水など
の混合液にてエツチングを行なう。Next, as shown in FIG. 1(b), the Al-Ni alloy layer 5
Immerse it in etching solution and remove the glue other than the bump electrode part.
Alloy layer 5 is removed. Etching is performed using an etching solution i for removing the AL-Ni alloy layer 5, a mixed solution of phosphoric acid, nitric acid, glacial acetic acid, sulfuric acid, water, and the like.
・マンプ電極全体および銅メツ岑層８、中間金属層とし
てのＮ１層６は錫メッキ層９−２で覆われておシ、錫は
リン酸、硝酸、氷酢酸、硫酸、水の混合エッチャントで
は侵されない。・The entire Mamp electrode, the copper metal layer 8, and the N1 layer 6 as an intermediate metal layer are covered with a tin plating layer 9-2, and the tin is covered with a mixed etchant of phosphoric acid, nitric acid, glacial acetic acid, sulfuric acid, and water. Not infringed.
次に、第１図（ｃ）に示すように、通常３４０〜３５０
℃の温度で、それぞれハンダメッキ９−１と錫メッキ層
９−２を溶解させて、ハンダの合金化処理を行ない、半
球状のハンダバンプ電極を形成する。Next, as shown in Fig. 1(c), normally 340 to 350
The solder plating 9-1 and the tin plating layer 9-2 are respectively melted at a temperature of .degree. C., and the solder is alloyed to form a hemispherical solder bump electrode.
（発明の効果）
この発明は以上説明したように、ハンダメッキを形成後
、ＡＩ、 −Ｎｉ合金層の除去の際にメッキ保護用のし
Ｖストを溶剤で除去した後に錫をハンダメッキおよび銅
メッキ層に薄く被着させるようにしたので、ハンダメッ
キおよび銅メッキ層、拡散防止金属層がエツチングされ
ず、ハンダバンプ電極の半球状化が良好に行うことがで
き、良好なデンディング性を示す。(Effects of the Invention) As described above, the present invention is capable of forming a solder plating layer, removing a V-stack for protecting the plating with a solvent when removing an AI, -Ni alloy layer, and then applying a tin solder plating process to a copper plate. Since the solder plating layer, the copper plating layer, and the diffusion prevention metal layer are coated thinly on the plating layer, the solder plating layer, the copper plating layer, and the diffusion prevention metal layer are not etched, and the solder bump electrode can be well formed into a hemispherical shape, showing good densability.
また、バンプ電極の底部をレジストで覆う工程が無くな
るので、通常のホトリン工程が１回省略で藪、処理工程
時間が大巾に短縮化される。Furthermore, since the step of covering the bottom of the bump electrode with resist is eliminated, one normal photorin step is omitted, and the processing time is greatly shortened.
さらに、／ｕ−Ｎｉ合金層５のエツチング後のパターン
は、中間金属としてのＮｉ層６と同程度になるので、球
状化したバンプ電極よシ外側へ張シ出すことがなくなる
。したがって、パンダ電極の間隙を短かくすることが可
能となシ、高密度のパンダ電極を半導体基板上に形成す
ることができる。Furthermore, since the etched pattern of the /u-Ni alloy layer 5 is comparable to that of the Ni layer 6 as an intermediate metal, it does not protrude outward from the spherical bump electrode. Therefore, the gap between the panda electrodes can be shortened, and panda electrodes with high density can be formed on the semiconductor substrate.
第１図（ａ）ないし第１図（０）は、この発明の半導体
装置の製造方法の一実施例の工程説明図、第２図（ａ）
ないし第２図（ｉ）は従来の半導体装置の製造方法の工
程説明図である。
１・・・半導体基板、２・・・酸化膜、３・・・アルミ
電極パッド、４・・・パッシベーション膜、５・・・Ａ
Ｌ −Ｎｉ 合金層、６・・・Ｎｉ層、７・・・レジス
ト、８・・・銅メッキ層、９−１・・・ハンダメッキ、
９−２・・・錫メッキ。
特許出願人 沖電気工業株式会社
第１図
第１図
第２図
第２図1(a) to 1(0) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2(a)
2(i) to 2(i) are process explanatory diagrams of a conventional method for manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 3... Aluminum electrode pad, 4... Passivation film, 5... A
L-Ni alloy layer, 6... Ni layer, 7... resist, 8... copper plating layer, 9-1... solder plating,
9-2...Tin plating. Patent applicant Oki Electric Industry Co., Ltd. Figure 1 Figure 1 Figure 2 Figure 2
Claims (1)
にＡｌ電極バンプを形成した後このＡｌ電極パッドが露
出するようにパッシベーション膜を形成する工程と、上
記バンプ電極を形成する個所に中間の金属層を形成する
とともに、バンプ電極を形成する個所以外をメッキ用の
レジストに覆う工程と、上記中間の金属層上に電気メッ
キ法により、銅メッキ層を形成した後ハンダメッキによ
るバンプ電極を形成する工程と、このバンプ電極形成後
上にレジストを除去して上にバンプ電極ならびに、中間
の金属層の全面を錫メッキで覆う工程とよりなる半導体
装置の製造方法。A process of forming an Al electrode bump on the oxide film on the semiconductor substrate at the location where the bump electrode is to be formed, and then forming a passivation film so that the Al electrode pad is exposed, and a step of forming an intermediate metal at the location where the bump electrode is to be formed. At the same time as forming a layer, a step of covering the area other than the part where the bump electrode is to be formed with a plating resist, and forming a copper plating layer on the intermediate metal layer by electroplating, and then forming a bump electrode by solder plating. and a step of removing the resist on top after forming the bump electrode and covering the entire surface of the bump electrode and the intermediate metal layer with tin plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131876A JPS6112047A (en) | 1984-06-28 | 1984-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131876A JPS6112047A (en) | 1984-06-28 | 1984-06-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6112047A true JPS6112047A (en) | 1986-01-20 |
Family
ID=15068204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59131876A Pending JPS6112047A (en) | 1984-06-28 | 1984-06-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6112047A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393696A (en) * | 1990-12-03 | 1995-02-28 | Grumman Aerosace Corp. | Method for forming multilayer indium bump contacts |
| US7007834B2 (en) | 2000-12-20 | 2006-03-07 | PAC Tech—Packaging Technologies GmbH | Contact bump construction for the production of a connector construction for substrate connecting surfaces |
| JP2008547207A (en) * | 2005-06-14 | 2008-12-25 | キュービック・ウエハ・インコーポレーテッド | Electronic chip contact structure |
| JP2009016857A (en) * | 2000-06-23 | 2009-01-22 | Ibiden Co Ltd | Multilayer printed wiring board, and manufacturing method thereof |
| JP2009124130A (en) * | 2007-11-16 | 2009-06-04 | Hwabeak Engineering Co Ltd | Copper pole-tin bump formed in semiconductor chip, and its forming method |
| CN103187324A (en) * | 2011-12-28 | 2013-07-03 | 中国科学院上海微系统与信息技术研究所 | Preparation method and structure of welding spot |
| US9754907B2 (en) | 2005-06-14 | 2017-09-05 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
-
1984
- 1984-06-28 JP JP59131876A patent/JPS6112047A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393696A (en) * | 1990-12-03 | 1995-02-28 | Grumman Aerosace Corp. | Method for forming multilayer indium bump contacts |
| JP2009016857A (en) * | 2000-06-23 | 2009-01-22 | Ibiden Co Ltd | Multilayer printed wiring board, and manufacturing method thereof |
| US7007834B2 (en) | 2000-12-20 | 2006-03-07 | PAC Tech—Packaging Technologies GmbH | Contact bump construction for the production of a connector construction for substrate connecting surfaces |
| JP2008547207A (en) * | 2005-06-14 | 2008-12-25 | キュービック・ウエハ・インコーポレーテッド | Electronic chip contact structure |
| US9754907B2 (en) | 2005-06-14 | 2017-09-05 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
| US10340239B2 (en) | 2005-06-14 | 2019-07-02 | Cufer Asset Ltd. L.L.C | Tooling for coupling multiple electronic chips |
| JP2009124130A (en) * | 2007-11-16 | 2009-06-04 | Hwabeak Engineering Co Ltd | Copper pole-tin bump formed in semiconductor chip, and its forming method |
| CN103187324A (en) * | 2011-12-28 | 2013-07-03 | 中国科学院上海微系统与信息技术研究所 | Preparation method and structure of welding spot |
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