JPH03190240A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03190240A JPH03190240A JP1330463A JP33046389A JPH03190240A JP H03190240 A JPH03190240 A JP H03190240A JP 1330463 A JP1330463 A JP 1330463A JP 33046389 A JP33046389 A JP 33046389A JP H03190240 A JPH03190240 A JP H03190240A
- Authority
- JP
- Japan
- Prior art keywords
- film
- pad
- resist
- contact
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000010931 gold Substances 0.000 abstract description 17
- 238000007747 plating Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000001459 lithography Methods 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 238000005260 corrosion Methods 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 238000009713 electroplating Methods 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 86
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 239000013039 cover film Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- SRCZENKQCOSNAI-UHFFFAOYSA-H gold(3+);trisulfite Chemical compound [Au+3].[Au+3].[O-]S([O-])=O.[O-]S([O-])=O.[O-]S([O-])=O SRCZENKQCOSNAI-UHFFFAOYSA-H 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
パッド上にバンプを形成する工程を含む半導体装置の製
造方法に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device including a step of forming bumps on pads.
レジスト残渣によるバンプとパッドの界面に腐食の生じ
ない簡易で高信頼度のパッドの形成方法を提供すること
を目的とし。The purpose of this invention is to provide a simple and highly reliable pad formation method that does not cause corrosion at the bump-pad interface due to resist residue.
半導体基板上に、導電膜からなるパッドを形成し、該パ
ッドを覆って該基板上に絶縁膜を被着し。A pad made of a conductive film is formed on a semiconductor substrate, and an insulating film is deposited on the substrate to cover the pad.
該パッド上の該絶縁膜に開口部を形成する工程と。forming an opening in the insulating film over the pad;
該開口部を覆って該基板上に導電膜からなるコンタクト
膜を被着する工程と、該コンタクト膜上の該開口部領域
にレジスト膜を形成し、該レジスト膜をエツチングマス
クにして該コンタクト膜をエツチング除去する工程と、
該レジスト膜を除去した後、該開口部領域に残った該コ
ンタクト膜上に導電膜を堆積して放膜からなるバンプを
形成する工程とを有するように構成する。a step of depositing a contact film made of a conductive film on the substrate to cover the opening; forming a resist film in the opening region on the contact film; using the resist film as an etching mask, etching the contact film; a step of etching away the
After the resist film is removed, a conductive film is deposited on the contact film remaining in the opening region to form a bump made of a film.
本発明はパッド上にバンプを形成する工程を含む半導体
装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device including a step of forming bumps on pads.
本発明はＴＡＢ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂ
ｏｎｄｉｎｇ）技術等に利用されるワイヤレスボンディ
ング用半導体チップのボンディング端子としてのバンプ
（突起型金属電極）形成に適用できる。The present invention is based on TAB (Tape Automated B).
It can be applied to the formation of bumps (protruding metal electrodes) as bonding terminals of semiconductor chips for wireless bonding, which are used in bonding technology and the like.
半導体装置は大規模化、高集積化が進み、それに伴いパ
ッケージは多ピン化の傾向にある。2. Description of the Related Art Semiconductor devices are becoming larger and more highly integrated, and as a result, packages tend to have more pins.
しかし、多ピン化に対応して現在のワイヤボンディング
技術では限界があり、今やＴＡＢ技術が必須の状況にあ
る。However, the current wire bonding technology has its limits in response to the increasing number of pins, and TAB technology is now indispensable.
次に、従来技術による製造方法の一例を第２図を用いて
説明する。Next, an example of a manufacturing method according to the prior art will be explained using FIG. 2.
第２図（１）〜（４）は従来例によるバンプ形成を説明
する断面図である。FIGS. 2(1) to 2(4) are cross-sectional views illustrating bump formation according to a conventional example.
第２図（１）において、化学気相成長（ＣＶＤ）法によ
り、珪素（Ｓｉ）基板ｌの上に、二酸化珪素（ＳｉＯ□
）膜等の絶縁膜２を被着し、続いてスパッタ法により。In FIG. 2 (1), silicon dioxide (SiO□
) film or the like is deposited, followed by sputtering.
純アルミニウム（ＡＩ）膜又はＳｉや銅（Ｃｕ）等を含
有するＡ１合金膜を被着し、この膜をパターニングして
パッド５を形成する。A pure aluminum (AI) film or an A1 alloy film containing Si, copper (Cu), etc. is deposited, and this film is patterned to form pads 5.
次に、 ＣＶＤ法により、基板上にカバー膜となる燐（
Ｐ）、硼素（Ｂ）等の不純物を含むＳｉＯ□膜又は純Ｓ
ｉＯ□膜３，４を被着し４通常のりソグラフィを用いて
パッド５上のこの膜を開口する。Next, using the CVD method, phosphorus (
P), SiO□ film containing impurities such as boron (B) or pure S
An iO□ film 3, 4 is deposited and an opening is opened in this film on the pad 5 using conventional lamination lithography.
次に、スパッタ法により、基板上にＡＩ膜とコンタクト
が良好な膜として例えばチタン（Ｔｉ）膜６゜Ｔｉ膜と
コンタクトが良好な膜として例えばパラジウム（Ｐｄ）
膜７を順次被着する。Next, by sputtering, a film having good contact with the AI film, such as a titanium (Ti film), and a film having good contact with the AI film, such as palladium (Pd), are deposited on the substrate.
Films 7 are applied one after the other.
第２図（２）において、リソグラフィを用いて、基板上
にパッド上の開口を持つレジスト膜９を形成する。In FIG. 2(2), a resist film 9 having an opening above the pad is formed on the substrate using lithography.
第２図（３）において、亜硫酸金液等の金（Ａｕ）を含
むメツキ液を用いて電解メツキにより、開口部にバンプ
８としてＡｕ膜を堆積する。In FIG. 2(3), an Au film is deposited as bumps 8 on the openings by electrolytic plating using a plating solution containing gold (Au) such as a gold sulfite solution.
この際、 Ａｕは縦方向だけでなく、レジスト膜９を押
し広げて横方向にも成長するため、バンプ８の周囲に庇
（ひさし）を生ずる。At this time, since Au grows not only in the vertical direction but also in the horizontal direction by spreading the resist film 9, an eave is formed around the bump 8.
第２図（４）において、剥離液を用いてレジスト膜９を
除去する。In FIG. 2(4), the resist film 9 is removed using a stripping solution.
以上の工程を経てバンプ８が形成される。Bumps 8 are formed through the above steps.
上記の従来工程により製造すると、第２図（４）に示さ
れるように、レジスト膜９がバンプ８の庇の下に残り、
このためにその後、 Ａｕバンプ８やＡＩパッド５やＰ
ｄ膜７に腐食が発生し、デバイスの信頼性の低下につな
がるといった問題があった。When manufactured using the above conventional process, the resist film 9 remains under the eaves of the bumps 8, as shown in FIG. 2(4).
For this reason, after that, Au bump 8, AI pad 5, P
There was a problem in that corrosion occurred in the d film 7, leading to a decrease in device reliability.
本発明はレジスト残渣によるバンプとパッドの界面に腐
食の生じない簡易で高信頼度のバンプの形成方法を提供
することを目的とする。An object of the present invention is to provide a simple and highly reliable method for forming bumps that does not cause corrosion at the interface between bumps and pads due to resist residue.
上記課題の解決は、半導体基板上に導電膜からなるパッ
ドを形成し、該パッドを覆って該基板上に絶縁膜を被着
し、該パッド上の該絶縁膜に開口部を形成する工程と、
該開口部を覆って該基板上に導電膜からなるコンタクト
膜を被着する工程と。The above problem can be solved by forming a pad made of a conductive film on a semiconductor substrate, depositing an insulating film on the substrate to cover the pad, and forming an opening in the insulating film on the pad. ,
a step of depositing a contact film made of a conductive film on the substrate to cover the opening;
該コンタクト膜上の該開口部領域にレジスト膜を形成し
、該レジスト膜をエツチングマスクにして該コンタクト
膜をエツチング除去する工程と、該レジスト膜を除去し
た後、該開口部領域に残った該コンタクト膜上に導電膜
を堆積して放膜からなるバンプを形成する工程とを有す
る半導体装置の製造方法により達成される。A resist film is formed in the opening region on the contact film, and the contact film is etched away using the resist film as an etching mask. After the resist film is removed, the resist film remaining in the opening region is removed. This is achieved by a method of manufacturing a semiconductor device, which includes a step of depositing a conductive film on a contact film to form a bump made of a film.
本発明はパッド上に金めつきをしてバンプを形成する際
にレジスト膜を使用しないようにして。The present invention avoids using a resist film when forming bumps by plating gold on pads.
即ち、金めつき前に、パッドを覆って全面被着されてい
るコンタクト層をパッド部分のみ残してパターニングし
、レジストの代わりに基板上に被着されている絶縁膜を
マスクにしてコンタクト層上に金めつきをすることによ
りレジスト残渣を発生させないようにしたものである。That is, before gold plating, the contact layer, which is completely deposited over the pad, is patterned leaving only the pad portion, and the insulating film deposited on the substrate is used as a mask instead of the resist to pattern the contact layer over the contact layer. By applying gold plating to the surface, resist residue is prevented from being generated.
第１図（１）〜（４）は本発明の一実施例によるバンプ
形成を説明する断面図である。FIGS. 1(1) to 1(4) are cross-sectional views illustrating bump formation according to an embodiment of the present invention.
第１図（１）において、化学気相成長（ＣＶＤ）法によ
り、珪素（Ｓｉ）基板１の上に、絶縁膜２として厚さ１
００〜５００人の二酸化珪素（ＳｉＯ□）膜を被着し、
続いてスパッタ法により、厚さ０．１−１μｍのアルミ
ニウム（Ａｌ）膜又はＳｉや銅（Ｃｕ）等を含有するＡ
１合金膜を被着し、この膜をパターニングしてパッド５
を形成する。In FIG. 1 (1), an insulating film 2 is formed on a silicon (Si) substrate 1 to a thickness of 1 by chemical vapor deposition (CVD).
Depositing silicon dioxide (SiO□) film of 00 to 500 people,
Next, by sputtering, a 0.1-1 μm thick aluminum (Al) film or an aluminum film containing Si, copper (Cu), etc.
1 alloy film is deposited and this film is patterned to form pad 5.
form.
次に、 ＣＶＤ法により、基板上にカバー膜（絶縁膜）
３，４となる燐（Ｐ）、 硼素（Ｂ）等の不純物を含
むＳｉＯ□膜又は純ＳｉＯ□膜３，４を被着し１通常の
りソグラフィを用いてパッド５上のこの膜を開口する。Next, a cover film (insulating film) is deposited on the substrate using the CVD method.
A SiO□ film containing impurities such as phosphorus (P) and boron (B) or a pure SiO□ film 3, 4 is deposited and an opening is opened in this film on the pad 5 using normal gluing lithography. .
ここで、カバー膜３の厚さは５０００〜１００００人。Here, the thickness of the cover film 3 is 5000 to 10000.
カバー膜４の厚さは１０００〜２５００Ａである。The thickness of the cover film 4 is 1000-2500A.
次に、スパッタ法により、基板上にコンタクト膜６．７
として、 Ａｌ膜とコンタクトが良好な膜として例えば
厚さ３０００人のチタン（Ｔｉ）膜６．Ｔｉ膜とコンタ
クトが良好な膜として例えば厚さ３０００人のパラジウ
ム（Ｐｄ）膜７を順次被着する。Next, a contact film 6.7 is deposited on the substrate by sputtering.
For example, a titanium (Ti) film with a thickness of 3000 mm is used as a film that has good contact with the Al film. As a film having good contact with the Ti film, a palladium (Pd) film 7 having a thickness of 3,000 yen, for example, is sequentially deposited.
第１図（２）において、リソグラフィを用いてパッド上
の領域にレジスト膜９Ａを形成する。In FIG. 1(2), a resist film 9A is formed in the region above the pad using lithography.
第１図（３）において、レジスト膜９Ａをマスクにして
コンタクト膜６．７をエツチングし、パッド上のコンタ
クト膜６，７を残して、その他の部分を除去する。In FIG. 1(3), the contact films 6 and 7 are etched using the resist film 9A as a mask, leaving the contact films 6 and 7 on the pads and removing the other portions.
この際、 Ｐｄ膜７は塩酸と硝酸の混合液、Ｔｉ膜６は
弗酸液を用いてエツチングする。At this time, the Pd film 7 is etched using a mixed solution of hydrochloric acid and nitric acid, and the Ti film 6 is etched using a hydrofluoric acid solution.
次に、剥離液を用いて、レジスト膜９Ａを除去する。Next, the resist film 9A is removed using a stripping solution.
第１図（４）において、亜硫酸金液等のＡｕを含むメツ
キ液を用いて電気メツキにより、開口部にバンプ８とし
て９例えば、厚さ２５μｍのＡｕ膜を堆積する。In FIG. 1(4), an Au film 9 having a thickness of 25 μm, for example, is deposited on the opening as a bump 8 by electroplating using a plating solution containing Au such as a gold sulfite solution.
Ａｕメツキの条件は、 Ａｕの含有量がｌＯｇ／ｌの亜
硫酸金液にウェハの表面を浸漬して行う。The conditions for Au plating are as follows: The surface of the wafer is immersed in a gold sulfite solution with an Au content of 10 g/l.
この際、 Ａｕは縦方向だけでなく、横方向にも成長す
るが、バンプ８の周囲にレジスト残渣を生ずることはな
い。At this time, although Au grows not only in the vertical direction but also in the horizontal direction, no resist residue is formed around the bumps 8.
以上の工程を経てバンプ８が形成される。Bumps 8 are formed through the above steps.
次に、実施例の効果を示す具体例を示す。Next, a specific example showing the effects of the example will be shown.
実施例により形成した構造と、従来構造とでエレクトロ
マイグレーション等の信頼ドレイン評価を行ったところ
、従来構造では初期不良が多く見られた。又、長期間に
わたる評価も両者間の有意差は明確となっている。When reliability drain evaluations such as electromigration were performed on the structure formed according to the example and the conventional structure, many initial failures were observed in the conventional structure. Furthermore, long-term evaluations also revealed a significant difference between the two.
以上説明したように本発明によれば、レジスト残渣によ
るバンプとパッドの界面に腐食の生じない簡易で高信頼
度のバンプの形成方法が得られ。As described above, according to the present invention, a simple and highly reliable method for forming bumps that does not cause corrosion at the bump-pad interface due to resist residue can be obtained.
デバイスの信頼性を向上することができた。We were able to improve the reliability of the device.
図において。In fig.
ｌは半導体基板でＳｉ基板。l is a semiconductor substrate, which is a Si substrate.
２は絶縁膜で５ｉ０２膜。2 is an insulating film and is a 5i02 film.
３．４はカバー膜（絶縁膜）で５ｉＯｚ膜。3.4 is a cover film (insulating film), which is a 5iOz film.
又はＰ、 Ｂ等の不純物を含む５ｉｎ２膜。Or a 5in2 film containing impurities such as P and B.
５はパッドでＡｌ膜 又はＳｉやＣｕ等を含有するＡ１合金膜。5 is a pad with Al film Or an A1 alloy film containing Si, Cu, etc.
６はコンタクト膜でＴｉ膜。6 is a contact film, which is a Ti film.
７はコンタクト膜でＰｄ膜。7 is a contact film, which is a Pd film.
８はバンプでＡｕ膜。8 is a bump made of Au film.
９Ａはレジスト膜9A is a resist film
第１図（１）〜（４）は本発明の一実施例によるバンプ
形成を説明する断面図。
第２図（１）〜（４）は従来例によるバンプ形成を説明
する断面図である。
芙赤例の断面図
従来ｆ１の断面図FIGS. 1 (1) to (4) are cross-sectional views illustrating bump formation according to an embodiment of the present invention. FIGS. 2(1) to 2(4) are cross-sectional views illustrating bump formation according to a conventional example. Cross-sectional view of Fuaka example Cross-sectional view of conventional f1
Claims (1)
ドを覆って該基板上に絶縁膜を被着し、該パッド上の該
絶縁膜に開口部を形成する工程と、該開口部を覆って該
基板上に導電膜からなるコンタクト膜を被着する工程と
、 該コンタクト膜上の該開口部領域にレジスト膜を形成し
、該レジスト膜をエッチングマスクにして該コンタクト
膜をエッチング除去する工程と、該レジスト膜を除去し
た後、該開口部領域に残った該コンタクト膜上に導電膜
を堆積して該膜からなるバンプを形成する工程とを有す
ることを特徴とする半導体装置の製造方法。[Claims] A step of forming a pad made of a conductive film on a semiconductor substrate, depositing an insulating film on the substrate covering the pad, and forming an opening in the insulating film on the pad. , a step of depositing a contact film made of a conductive film on the substrate to cover the opening; forming a resist film in the opening region on the contact film; and using the resist film as an etching mask, removing the contact; The method is characterized by comprising a step of etching away the film, and a step of depositing a conductive film on the contact film remaining in the opening region after removing the resist film to form a bump made of the film. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1330463A JPH03190240A (en) | 1989-12-20 | 1989-12-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1330463A JPH03190240A (en) | 1989-12-20 | 1989-12-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03190240A true JPH03190240A (en) | 1991-08-20 |
Family
ID=18232906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1330463A Pending JPH03190240A (en) | 1989-12-20 | 1989-12-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03190240A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065785A (en) * | 1992-06-24 | 1994-01-14 | Nec Corp | Fabrication of spiral inductor |
| US6251528B1 (en) | 1998-01-09 | 2001-06-26 | International Business Machines Corporation | Method to plate C4 to copper stud |
| JP2002020891A (en) * | 2000-05-09 | 2002-01-23 | Internatl Business Mach Corp <Ibm> | Selective plating process |
-
1989
- 1989-12-20 JP JP1330463A patent/JPH03190240A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065785A (en) * | 1992-06-24 | 1994-01-14 | Nec Corp | Fabrication of spiral inductor |
| US6251528B1 (en) | 1998-01-09 | 2001-06-26 | International Business Machines Corporation | Method to plate C4 to copper stud |
| US6297140B1 (en) | 1998-01-09 | 2001-10-02 | International Business Machines Corporation | Method to plate C4 to copper stud |
| USRE40983E1 (en) * | 1998-01-09 | 2009-11-17 | International Business Machines Corporation | Method to plate C4 to copper stud |
| JP2002020891A (en) * | 2000-05-09 | 2002-01-23 | Internatl Business Mach Corp <Ibm> | Selective plating process |
| KR100466139B1 (en) * | 2000-05-09 | 2005-01-13 | 인터내셔널 비지네스 머신즈 코포레이션 | Selective plating process |
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