JP2001156246A - Mounting structure and mounting method for integrated circuit chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily suppress warpage of an LSI when a plurality of LSIs are mounted on a circuit board. SOLUTION: The mounting structure of the integrated circuit chip comprises a circuit board 2 and a plurality of integrated circuit chips (LSI1) mounted on the board 2. At least one of the chips is flip-chip mounted on the main surface of the board 2, and the flip-chip mounted part is resin-sealed. Further, a plate member (flat plate 5) is adhered onto the rear surface of the board 2 oppositely to the flip-chip mounted integrated circuit chips through a resin (sealing resin 3).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure and a mounting method for an integrated circuit chip, and more particularly to a COB (Chip On Chip).
The present invention relates to a mounting structure and a mounting method of an integrated circuit chip such as a board.

[0002]

2. Description of the Related Art Conventionally, in a structure in which an integrated circuit chip (hereinafter, referred to as LSI) is flip-chip mounted on a wiring board and an LSI joint is filled with a sealing resin, a soft printed wiring board is used as a material of the wiring board. When used, L
There is a problem that the SI mounting portion is easily deformed into a convex shape on the LSI mounting side.

FIG. 17 is a perspective view showing a conventional COB. As shown in FIG.
The COB 100 is configured by mounting an active element such as I101, a driver IC 112, a passive element such as a chip capacitor 112, a tantalum capacitor 112a, and a connector 112c. A sealing resin 103 is injected into a gap between the LSI 101 and the wiring board 102, and the LSI 101
A heat sink 110 for heat dissipation is mounted on the upper side via a heat conducting member. A chip capacitor 112 functioning as a bypass capacitor of each LSI 101 is soldered on the wiring board 102. Each terminal in the connector 112c is connected to the LSI 101 or the like via wiring provided on the surface or inside of the wiring board 102. Therefore, the COB 100 is electrically connected to an external device via the connector 112c.

FIG. 18 is a sectional view showing a state where a heat sink is attached to the back surface of the LSI. As shown in the figure, when attaching a heat sink to the back surface of the LSI in this state, the thickness of the heat conducting member 9 is not uniform,
There is a problem that the distance between the heat sink 10 and the LSI 1 becomes farther toward the outer periphery and the thermal resistance becomes higher, so that the heat radiation effect is deteriorated. In addition, a phenomenon in which the warpage of the LSI increases or decreases due to a temperature change during the operation of the LSI, and peeling or protrusion of the heat conducting member 9 occurs, and when the warpage further increases, cracks may occur in the LSI. There is a risk of being destroyed by the occurrence. In order to solve this problem, it is necessary to realize a structure in which the warpage of the LSI hardly changes.

[0005]

As described above, conventionally, there have been problems such as a heat radiation effect and warpage. In order to solve such a problem, Japanese Patent Laid-Open Publication No.
No. 9102 (electronic product) discloses that another LSI is provided on the back surface of a wiring board so as to face an LSI chip mounted on the wiring board.
There is disclosed a technology for mounting a chip to prevent warpage of an LSI chip. However, this technology
This is applicable only when two LSI chips having the same shape are mounted as a set.

In general, since a large number of solder bumps of hundreds to thousands are provided on an LSI chip, when the LSI chip is mounted on both sides of a wiring board,
Similarly, electrode pads need to be provided on both sides of the wiring board. Therefore, the structure of the wiring board becomes very complicated, and the manufacturing becomes difficult. In the future, in large-scale integrated circuits such as CPUs, as the chip size becomes larger, the number of terminals tends to increase more and more. L
It is not advisable to employ it to prevent SI warpage. The present invention is to solve such a problem,
An object of the present invention is to provide a mounting structure and a mounting method of an integrated circuit chip that can easily suppress warpage of an LSI when mounting a plurality of LSIs on a wiring board.

[0007]

In order to achieve such an object, the mounting structure of the integrated circuit chip according to the present invention is as follows.
In a mounting structure of an integrated circuit chip including a wiring substrate and a plurality of integrated circuit chips mounted on the wiring substrate, at least one of the integrated circuit chips is flip-chip mounted on a main surface of the wiring substrate. While being mounted, the flip-chip mounted portion is resin-sealed, and a plate member is adhered to the back surface of the wiring board via a resin so as to face the flip-chip mounted integrated circuit chip.

Further, the present invention includes the following structure as another embodiment. That is, the plate member may have a coefficient of thermal expansion smaller than that of the wiring board and larger than that of the integrated circuit chip. Further, the plate member has a size of 80 to 80 times the outer shape of the integrated circuit chip.
It may be within 120%. Further, the material of the plate member may be any one of alumina, a 42 alloy alloy, zirconia and forsterite. Further, a heat sink may be provided on the back surface of the integrated circuit chip via a heat conducting member. Further, a plurality of chip capacitors may be provided on the wiring board between the plate member and the wiring board. Further, a plurality of chip resistors may be provided on the wiring board between the plate member and the wiring board.

[0009] Further, the plurality of chip capacitors may be arranged so as to be closer to a periphery of the integrated circuit chip than to a center of the integrated circuit chip. Further, the plurality of chip resistors may be arranged so as to be closer to a periphery of the integrated circuit chip than to a center of the integrated circuit chip. Further, the plurality of chip capacitors are disposed thin near the center of the integrated circuit chip,
Thick ones may be arranged near the periphery of the integrated circuit chip.

The plurality of chip resistors may be thin near the center of the integrated circuit chip and thick near the periphery of the integrated circuit chip. Further, the wiring substrate may be any one of a substrate made of an epoxy-based organic resin, a ceramic substrate, and a substrate having a thin film wiring layer on a ceramic substrate. Further, the connection between the integrated circuit chip and the wiring substrate is performed by connecting an Au ball bump provided on the integrated circuit chip side to a conductive resin or an I.V.
It may be realized by bonding with n / Sn-based solder or Ag / Sn-based solder.

Next, according to a method of mounting an integrated circuit chip according to the present invention, in a method of mounting a plurality of integrated circuit chips on a wiring board, at least one of the integrated circuit chips is connected to a main board of the wiring board. Flip-chip mounting is performed on the front surface, the portion on which the flip-chip is mounted is resin-sealed, and a plate member is bonded to the back surface of the wiring board via a resin in opposition to the flip-chip mounted integrated circuit chip. Things. Further, as other aspects of the present invention, the same limitations as those of the above-described mounting structure may be added.

With this configuration, the present invention provides:
The warpage of the LSI can be suppressed, and the heat conductive member provided on the joint surface between the heat sink and the LSI can be made thin and uniform, so that an LSI package structure having a high heat radiation effect can be obtained. Further, in the above structure, by arranging the chip capacitor on the wiring board in the gap between the rear flat plate and the wiring board, it is possible to suppress a sudden voltage fluctuation of the LSI and realize a high-speed operation.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. The present invention relates to a mounting structure of an integrated circuit chip applicable to the COB shown in FIG. 17, and the following mainly describes a peripheral structure of the integrated circuit chip, which is a point of the present invention.

[First Embodiment] FIG. 1 is a sectional view showing a first embodiment of the present invention. As shown in the figure, pads corresponding to the arrangement of the electrodes of the LSI 1 are provided on the wiring board 2, and the electrodes of the LSI 1 and the wiring board 2 are provided.
Pads are flip-chip connected. The electrode is L
They are arranged on the outer periphery of the SI or in a grid, and are connected by a conductive material such as solder. Further, the LSI bonding portion is filled with a sealing resin 3, which serves to mechanically reinforce the LSI bonding portion and to suppress intrusion of moisture from the outside to prevent corrosion. On the back surface of the wiring board 2 on which the LSI 1 is mounted, a flat plate 5 is arranged so as to face the LSI 1, and is fixed by a sealing resin 13. Note that the flat plate 5 disposed on the back surface of the wiring board 2 preferably has a coefficient of thermal expansion equal to or smaller than that of the wiring board 2 and an outer shape substantially equal to or larger than the size of the LSI 1. Specifically, 80 to 120 of the outer shape of the LSI 1
% Has been confirmed by experiments by the present inventor. If the LSI 1 is 20 mm square, the flat plate 5 may be 16 to 24 mm square.

Generally, the thermal expansion coefficient of the wiring board is larger than the thermal expansion coefficient of the LSI. Therefore, when the flat plate is not arranged on the back surface of the wiring board 2 as in the conventional example, the wiring board 2
Due to the difference between the thermal expansion coefficients of the LSI and LSI1, a convex warpage occurs on the LSI mounting side. By fixing a flat plate made of a material equivalent to the thermal expansion coefficient of the wiring board to the back surface of the wiring board as in the present embodiment, the apparent thickness of the wiring board is increased, and the rigidity of the board is improved. Warpage can be reduced.

Next, the manufacturing process of this embodiment will be described with reference to FIGS. FIG. 2 is a cross-sectional view showing a structure in which the LSI 1 is flip-chip mounted on the wiring board 2. As shown in FIG.
Pads having the same arrangement as the electrodes of
And is electrically connected by soldering or the like. As a construction method, a spherical solder bump (for example, Sn ₆₃ / Pb ₃₇ wt% or Sn ₅ / Pb ₉₅ w
t%), cream solder (for example, Sn ₆₃ / Pb ₃₇ wt%) is printed on the pads of the wiring board 2 in advance, and the LSI 1 is mounted such that the pads of the wiring board 2 and the solder bumps of the LSI 1 face each other. Is mounted, and a heating reflow (for example, heating at 210 ° C.) is performed by a hot air oven or the like, and the connection between the wiring board 2 and the LSI 1 is completed by cooling.

At this time, if there is a difference between the thermal expansion coefficients of the LSI 1 and the wiring board 2, a small warp 6 is generated so that the LSI mounting side has a convex shape. Since the material of the LSI is Si (silicon), the coefficient of thermal expansion is about 3 ppm / ° C., whereas the coefficient of thermal expansion of a wiring board made of an epoxy-based organic material is about 12 to 20 ppm / ° C. At the time of heating reflow in soldering, the solder is not deformed because the LSI and the wiring board are not subjected to stresses from the outside, however, the solid phase point of the solder (for example, Sn ₆₃ / Pb ₃₇ wt% When the temperature becomes lower than 183 ° C. in the case of solder), the LSI 1 and the wiring board 2 are mechanically fixed. While returning from a high temperature to a normal temperature (for example, 25 ° C.), the LSI 1 and the wiring board 2 shrink.
The thermal expansion coefficient is larger than the thermal expansion coefficient of the LSI 1, so that the amount of shrinkage is large. As the temperature decreases, a convex warpage occurs on the LSI mounting surface side. Although the thermal stress due to the difference in thermal expansion coefficient between the wiring board 2 and the LSI 1 concentrates on the LSI joint 4, in the case of the solder connection, the solder is a relatively soft material and is deformed, resulting in a small warpage. 6 will occur.

FIG. 3 is a sectional view showing a structure in which a sealing resin 3 is filled in an LSI joint 4 of a wiring board 2 on which an LSI 1 is flip-chip mounted. As shown in FIG.
After cleaning the I junction, a liquid sealing resin is filled from the outer periphery of the LSI 1. The sealing resin is an epoxy-based or thermoplastic insulating resin, and is used to fill a narrow gap between the LSI 1 and the wiring board 2 at a temperature at which the sealing resin has good fluidity (for example, 60 ° C.).
C). In order to ensure the connection reliability of the LSI joint 4, it is necessary to fill the sealing resin without any gaps.
Normally, filling is performed from one side or two adjacent sides of the LSI, and care is taken so that air bubbles do not exist at the LSI junction. After the filling is completed, heating is performed to cure the sealing resin (for example, 1
50 ° C./30 minutes). During the heating, the LSI 1 and the wiring board 2 thermally expand again, so that the existing convex warpage on the LSI side is reduced and becomes closer to flat. However, when the temperature returns to room temperature after curing, heat shrinkage occurs again, and the LSI 1 and the wiring board 2
Is completely fixed by the sealing resin 3 so that LS
A large convex-shaped warp 8 occurs on the I side. For example, LS
The outer shape of I is 10mm x 10mm, and the material of the wiring board is FR
4 (glass epoxy board) with a thickness of 1 mm, about 50
Warpage of about 100 μm may occur.

FIG. 4 is a cross-sectional view showing a structure in which the LSI 1 is flip-chip mounted on the wiring board 2, the LSI bonding portion 4 is filled with a sealing resin, and the flat plate 5 is arranged on the back surface of the LSI 1 mounting portion of the wiring board 2. FIG. As shown in the figure,
Turn over so that the back surface of the wiring board 2 faces the top,
The sealing resin 13 is potted at the center of the SI mounting portion, a flat plate is pressed from above, and heat curing is performed in that state. When the sealing resin 3 used for filling the LSI joint 4 is used as the material of the sealing resin 13, the heat curing temperature is 150 ° C., so that the LSI 1 and the wiring board 2 undergo thermal expansion again and reach 150 ° C. At that point, the warp approaches flat. In this state, the sealing resin 13 is hardened, so that the amount of warpage after cooling depends on the material of the flat plate.

When, for example, Si (silicon), which is the same material as the LSI 1, is used as the material of the flat plate 5, the wiring board 2 is sandwiched between two pieces of Si, so that the force in the direction in which warpage occurs is offset. And the warpage becomes almost zero. As another material of the flat plate, a material having a smaller coefficient of thermal expansion than the wiring board 2 (for example, alumina ceramics (about 7
pm / ° C) and 42 alloy (about 6 pp
m / ° C.), zirconia (about 11 ppm / ° C.), forsterite (about 10 ppm / ° C.), etc., can reduce the warpage. In addition, flat plate 5
When a material having a thermal expansion coefficient equivalent to that of the wiring board 2 is used as the material of the wiring board 2, the effect of reducing the warpage is not so large as when a material having a small thermal expansion coefficient is used, but the thickness of the wiring board becomes apparently large Thus, the rigidity of the wiring board is increased, and the effect of slightly reducing the warpage can be obtained. If the outer shape of the flat plate 5 is made smaller than the outer shape of the LSI 1, thermal stress concentrates on the outer peripheral portion of the
It is not preferable because there is a risk that a failure such as breakage of the I-joined portion 4 occurs. By making the outer shape of the flat plate 5 larger than that of the LSI 1, it is possible to improve the reliability of the LSI joint portion 4. However, the best structure is to make the outer shape of the LSI 1 and the outer shape of the flat plate 5 substantially the same.

FIG. 5 is a sectional view of a structure in which a heat sink is attached to the back surface of the LSI. The material of the heat sink 10 is preferably aluminum or the like having excellent heat radiation characteristics.
It is attached to the back surface of I1 via a heat conducting member 9. The heat conductive member 9 is made of a material having excellent heat conductivity, such as an epoxy resin containing Ag (silver) filler,
A silicone compound containing an alumina ceramic filler is used. Since the back surface of the LSI 1 has a small warpage due to the effect of the flat plate 5, the thickness of the heat conducting member for transmitting the heat of the LSI 1 to the heat sink 10 can be made thin and uniform, and an efficient heat radiation effect can be obtained. .

As is clear from the above description, in a structure in which the LSI is flip-chip mounted on the wiring board and the sealing portion is filled in the LSI bonding portion, a flat plate is arranged on the back surface of the wiring board in the LSI mounting portion. By using LSI
Of the heat sink and LS
Since the heat conducting member provided on the bonding surface of I can be made thin and uniform, an LSI package structure having a high heat radiation effect can be obtained.

Next, another embodiment of the present invention will be described. [Second Embodiment] FIG. 6 is a sectional view showing a second embodiment of the present invention. As shown in FIG.
Pads corresponding to the arrangement of the electrodes of the LSI 1 are provided on the upper side, and the electrodes of the LSI 1 and the pads of the wiring board 2 are electrically flip-chip connected. The electrodes are arranged on the outer periphery of the LSI or in a lattice, and are connected by a conductive material such as soldering. Further, the LSI bonding portion is filled with a sealing resin, and serves to mechanically reinforce the LSI bonding portion and to suppress intrusion of moisture from the outside to prevent corrosion. On the back surface of the wiring board 2 on which the LSI 1 is mounted, a pad for mounting the chip capacitor 12 is provided in an area substantially the same as the outer shape of the LSI 1, and the chip capacitor 12 is electrically connected to the pad. And the chip capacitor 12
The flat plate 5 is disposed thereon, and the gap between the wiring board 2 and the flat plate 5 is filled and fixed by the sealing resin 13. The chip capacitor 12 functions as a bypass capacitor (pass capacitor) provided to reduce a noise voltage generated in the power supply line and the ground line, and is provided between the power supply Vcc and the ground GND.

This structure has the effect of making the warpage of the LSI close to zero similarly to the structure having no chip capacitor shown in FIG. 1, and the chip capacitor is arranged directly behind the LSI mounting portion, so that the voltage fluctuation of the LSI The effect is extremely high, and the structure is suitable for high-speed operation.

In the assembling process, cream solder is printed on a chip capacitor mounting pad provided on the back surface of the wiring board 2 on the LSI mounting side, the chip capacitor 12 is mounted on the cream solder, and then heat reflow is performed. The soldering of the capacitor 12 is completed. The subsequent steps may be the same as the LSI package structure without a chip capacitor shown in FIG. As a means for suppressing voltage fluctuation during operation of the LSI, it is general to arrange a capacitor near the LSI. However, as a means for suppressing voltage fluctuation during high-speed operation, a capacitor is disposed at a position as close as possible to the LSI. The effect is higher. In a flip-chip mounting structure in which electrodes are arranged on the entire circuit surface of an LSI,
It can be said that arranging a capacitor on the back surface of the LSI mounting portion of the wiring board is the most effective.

In the structure of FIG. 6, a flat plate is arranged on the upper surface of the chip capacitor 12, but the effect of suppressing the warpage of the LSI 1 is obtained similarly as in the structure without the chip capacitor of FIG. As shown in FIG.
Also, in the structure in which the heat conductive member 9 is attached to the back surface of the LSI 1, the thickness of the heat conductive member 9 can be made thin and uniform, and an efficient heat radiation effect can be obtained. The flat plate material used here is disposed on the chip capacitor 12, so there is a danger of short-circuiting between the electrodes of the chip capacitor 12 with a conductive material, and there is a danger of insulating material (for example, alumina) or metal material. In this case, it is preferable to use a material which has been subjected to an insulating coating treatment (for example, a polyimide coat or the like).

FIG. 8 is a plan view showing a layout of a chip capacitor. Here, the layout shown in FIG. 8B will be described. Here, the outer shape of the LSI and the flat plate is 10 mm square, and the outer shape of the chip capacitor is 1.6 mm.
mm x 0.8mm and the thickness is 0.5m
m. 3 × 5 = 15 chip capacitors are arranged. The shape of the chip capacitors is all the same, and the warpage of the LSI with respect to the material of the flat plate to be attached is shown in FIG. The thickness of the flat plate is unified to 0.5 mm.

FIG. 10 is a graph showing the warpage of the LSI with respect to the thickness of the flat plate. The material of the flat plate is unified to alumina. When the thickness exceeds 0.5 mm, the rigidity increases, and the amount of warpage is in an equilibrium state.

FIG. 11 is a graph showing the amount of warpage of the LSI with respect to the number (density) of chip capacitors. The material of the flat plate is alumina (7 ppm / ° C.), and the thickness is unified to 0.5 mm. It can be seen that as the density of the chip capacitor increases, the rigidity of the substrate itself increases and the amount of warpage decreases. Chip capacitors may have different shapes due to differences in capacitance and accuracy. For example, an outer shape of 1.6 mm × “1608”
Even a chip capacitor of 0.8 mm has a thickness of about 0.5 mm or 0.8 mm. When such chip capacitors are mounted in a mixed manner, it is desirable to arrange thick chip capacitors at the four corners and the outer periphery so that a flat plate stuck on the upper surface of the chip capacitor is stabilized. Although an example in which a chip capacitor is arranged is shown here, other passive elements (for example, a chip resistor, a choke coil, and the like) can be similarly arranged. Further, any one or a combination of simple ceramic pieces, resin pieces, and metal pieces may be used, or may be used in combination with the passive element.

FIG. 12 shows examples of some passive element arrangements. In the array D of FIG. 12A, 4 × 6 = 24 chip capacitors of “1608” are mounted at equal intervals, and the chip capacitors at the four corners have a large thickness (0.8 mm), and the other 20 capacitors have a thickness of 0.8 mm. (0.5 mm) is mounted. Array E in FIG. 12B is an arrangement in which the gap at the center of array D is expanded in a cross shape. Array F in FIG.
Shows the case where the four central resistors of the array E are chip resistors. The thickness of the chip resistor is almost the same as that of the chip capacitor 12 having a small thickness.

FIG. 13 is a graph showing the amount of LSI warpage for each array. The material of the flat plate is zirconia (10 ppm / ° C.), and the thickness is unified to 0.5 mm. In the arrangements D to F, since the thickness of the chip capacitor at the four corners is large, the thickness of the sealing resin near the center is large, so that resin shrinkage occurs in the heat curing step after filling,
A phenomenon occurs in which the flat plate and the wiring board are attracted to each other, so that the warping direction of the LSI is shifted to the minus side from the arrangement C in which chip capacitors of the same height are uniformly arranged.

Here, the manufacturing process of the second embodiment will be described with reference to the drawings. 14, 15, and 1
FIG. 6 is a cross-sectional view showing the manufacturing process of the second embodiment, in which conditions such as heat treatment are the same as in the first embodiment. First, as shown in FIG. 14A, a plurality of electrode pads 2b are provided on the wiring board 2 in advance. Next, as shown in FIGS. 14B and 14C, a stainless steel mask 20 having a plurality of through holes 20 a is placed on the wiring board 2. Each through hole 20 a is provided so as to coincide with the electrode pad 2 b on the wiring board 2. Therefore, when the mask 20 is placed, only the electrode pad 2b is exposed at the bottom of the through-hole 20a, and the cream solder 21 is spread using the rubber squeegee 22. 21 can be placed.

Next, as shown in FIGS. 14D and 14E, the LSI 1 on which the solder bumps 4a are provided in advance is placed on the wiring board 2 and is heated and reflowed, so that the LSI 1 The bonding portion 4 is formed, and the wiring board 2 and the LSI 1 are electrically connected. Next, as shown in FIGS. 15F and 15G, the liquid resin 3a is poured between the LSI 1 and the wiring board 2 using the dispenser 23, so that the resin 3a is connected to the LSI 1 and the wiring board by a capillary phenomenon. Spread between two. Then, FIG.
As shown in (h), by curing and curing the resin 3a, the gap between the LSI 1 and the wiring board 2 can be sealed with resin. At this time, the LSI 1 and the wiring board 2 are deformed due to a slight decrease in the volume of the sealing resin 3a, and a convex warpage is generated on the LSI 1 side. Then, FIG.
As shown in FIG. 5 (i), the chip capacitor 12 is mounted on the wiring board 2 on the side where the LSI 1 is not mounted, with the side on which the LSI 1 is mounted down, in the same manner as in the case of the LSI 1.
With.

Next, as shown in FIG. 16 (j), a flat plate 5 of the same size as the LSI 1 is placed on the chip capacitor 12.
Is placed, and the resin 13 is placed between the flat plate 5 and the wiring board 2.
pour a. Next, as shown in FIG. 16 (k), the gap between the flat plate 5 and the wiring board 2 is sealed with a resin by curing the resin 13a by curing. At this time, the resin 13a shrinks in the same manner as described above, but the resin 13a is warped in a direction opposite to the above-described warpage, so that the resin 13a is balanced and flat as a whole. Finally, as shown in FIG. 16 (l), the mounting structure according to the present embodiment is completed by fixing the heat sink 10 to the back surface of the LSI 1 via the heat conducting member 9.

[Third Embodiment] As a type of a wiring board, a ceramic board, a board having a thin film wiring layer on a ceramic board, and the like can be considered in addition to a printed wiring board made of an epoxy-based organic resin. Multiple L on one substrate
In the case of an LSI package structure in which the SI is flip-chip mounted, it is expected that the warpage of the entire package will be very large. However, by arranging the flat plate of the present invention at each LSI mounting position, the warpage of the entire LSI package is expected. Can be suppressed. In the first and second embodiments, the soldering structure is described as the LSI joint, but Au (gold) ball bumps are arranged on the LSI side.
Conductive adhesive, In / Sn solder, Ag on the wiring board side
A structure using a / Sn-based solder is also conceivable. As the shape of the flat plate, in addition to the flat plate shape, a shape having a concave portion capable of accommodating a chip capacitor and a shape having projections at four corners to prevent contact with the chip capacitor are also conceivable.

[0036]

As is apparent from the above description, in a structure in which an LSI is flip-chip mounted on a wiring board and a sealing resin is filled in an LSI bonding portion, a flat plate is formed on the back surface of the wiring board in the LSI mounting portion. By bonding, LS
I can suppress the warpage of the heat sink and the heat sink and L
Since the heat conductive member provided on the bonding surface of the SI can be made thin and uniform, an LSI package structure having a high heat radiation effect can be obtained. Further, in the above structure, by arranging the chip capacitor on the wiring board in the gap between the rear flat plate and the wiring board, it is possible to suppress a sudden voltage fluctuation of the LSI and realize a high-speed operation. The present invention is applied to a so-called COB in which a plurality of integrated circuit chips are mounted on a wiring board,
If at least one integrated circuit chip is flip-chip mounted, it can be applied to that chip. Of course, the present invention may be applied to a plurality of flip-chip mounted chips. Some of the plurality of integrated circuit chips are QFP (Quad Flat Package) or SOP.
(Small Outline Package). These chips are used, for example, as a temperature sensor or a driver IC for controlling the sensor. Further, not only an integrated circuit chip but also passive elements such as a chip capacitor and a chip resistor may be mounted together.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing step of the package structure according to FIG. 1;

FIG. 3 is a sectional view showing a manufacturing step of the package structure according to FIG. 1;

FIG. 4 is a sectional view showing a manufacturing step of the package structure according to FIG. 1;

FIG. 5 is a sectional view showing a manufacturing step of the package structure according to FIG. 1;

FIG. 6 is a sectional view showing a second embodiment of the present invention.

FIG. 7 is a sectional view showing a second embodiment of the present invention.

FIG. 8 is a plan view showing a layout of a chip capacitor.

FIG. 9 is a graph showing a relationship between a thermal expansion coefficient of a flat plate and LSI warpage.

FIG. 10 is a graph showing the relationship between the thickness of a flat plate and the warpage of an LSI.

FIG. 11 is a graph showing the relationship between the number of chip capacitors and LSI warpage.

FIG. 12 is a plan view showing a layout of a chip capacitor.

FIG. 13 is a graph showing the relationship between the layout of a chip capacitor and the warpage of an LSI.

FIG. 14 is a sectional view showing a manufacturing step of the mounting structure according to FIG. 7;

FIG. 15 is a sectional view showing a step continued from FIG. 14;

FIG. 16 is a sectional view showing a step continued from FIG. 15;

FIG. 17 is a perspective view showing a general COB.

FIG. 18 is a sectional view showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LSI, 2 ... wiring board, 2a ... wiring, 2b ... electrode pad, 3 ... sealing resin, 3a ... resin, 4 ... LSI joining part,
4a: solder bump, 5: flat plate, 6: small warpage, 8:
Large warp, 9: heat conductive member, 10: heat sink, 1
1: gap, 12: chip capacitor, 13: sealing resin,
13a: resin, 14: chip capacitor, 15: chip resistor, 20: mask, 20a: through hole, 21: cream solder.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 1/18 H01L 23/12 L 3/32 23/36 M 3/34 507 F term (Reference) 5E319 AA03 AB05 BB05 BB11 CC33 CC61 CD45 5E336 AA04 BB01 CC31 CC53 CC58 EE03 GG03 5F036 AA01 BB01 BB08 BD01 5F044 KK02 KK04 LL01 LL07 RR10 RR18

Claims (26)

[Claims] 1. An integrated circuit chip mounting structure comprising a wiring board and a plurality of integrated circuit chips mounted on the wiring board, wherein at least one of the integrated circuit chips is mounted on the wiring board. While being flip-chip mounted on the main surface,
The flip-chip mounted portion is sealed with a resin, and a plate member is bonded to the back surface of the wiring substrate via a resin in opposition to the flip-chip mounted integrated circuit chip. Circuit chip mounting structure. 2. The integrated circuit chip mounting structure according to claim 1, wherein the plate member has a coefficient of thermal expansion smaller than that of the wiring substrate and larger than that of the integrated circuit chip. 3. The mounting structure of an integrated circuit chip according to claim 1, wherein the size of the plate member is within 80 to 120% of the outer shape of the integrated circuit chip. 4. The plate member according to claim 1, wherein a material of the plate member is alumina, a 42 alloy alloy,
A mounting structure of an integrated circuit chip, which is one of zirconia and forsterite. 5. The integrated circuit chip mounting structure according to claim 1, wherein a heat sink is provided on a back surface of the integrated circuit chip via a heat conductive member. 6. The integrated circuit chip mounting structure according to claim 1, wherein a plurality of chip capacitors are provided on the wiring board between the plate member and the wiring board. 7. The mounting structure of an integrated circuit chip according to claim 1, wherein a plurality of chip resistors are provided on the wiring board between the plate member and the wiring board. 8. The integrated circuit chip according to claim 6, wherein the plurality of chip capacitors are arranged closer to a peripheral portion of the integrated circuit chip than to a central portion thereof. Mounting structure. 9. The integrated circuit chip according to claim 7, wherein the plurality of chip resistors are arranged closer to a peripheral portion than to a central portion of the integrated circuit chip. Mounting structure. 10. The plurality of chip capacitors according to claim 6, wherein a thin one is arranged near a central part of the integrated circuit chip, and a thick one is arranged near a peripheral part of the integrated circuit chip. Characteristic integrated circuit chip mounting structure. 11. The integrated circuit chip according to claim 7, wherein the plurality of chip resistors are thin near the center of the integrated circuit chip and thick near the periphery of the integrated circuit chip. Characteristic integrated circuit chip mounting structure. 12. The wiring board according to claim 1, wherein the wiring board is a board made of an epoxy-based organic resin,
An integrated circuit chip mounting structure, which is a ceramic substrate or a substrate having a thin film wiring layer on a ceramic substrate. 13. The connection between the integrated circuit chip and the wiring board according to claim 1, wherein the connection between the integrated circuit chip and the wiring board is made of an Au ball bump provided on the integrated circuit chip side and a conductive resin provided on the wiring board side. In / S
An integrated circuit chip mounting structure realized by bonding with an n-based solder or an Ag / Sn-based solder. 14. A method of mounting a plurality of integrated circuit chips on a wiring board, wherein at least one of the integrated circuit chips is flip-chip mounted on a main surface of the wiring board, and the flip-chip mounting is performed. A resin member, and bonding a plate member via a resin to the back surface of the wiring board in opposition to the flip-chip mounted integrated circuit chip. 15. The method according to claim 14, wherein the plate member has a coefficient of thermal expansion smaller than that of the wiring board and larger than that of the integrated circuit chip. 16. The method according to claim 14, wherein the size of the plate member is within 80 to 120% of the outer shape of the integrated circuit chip. 17. The plate member according to claim 14, wherein a material of the plate member is alumina, a 42 alloy alloy,
A method for mounting an integrated circuit chip, which is one of zirconia and forsterite. 18. The method for mounting an integrated circuit chip according to claim 14, wherein a heat sink is provided on a back surface of the integrated circuit chip via a heat conductive member. 19. The method according to claim 14, wherein a plurality of chip capacitors are provided on the wiring board between the plate member and the wiring board. 20. The method for mounting an integrated circuit chip according to claim 14, wherein a plurality of chip resistors are provided on the wiring board between the plate member and the wiring board. 21. The integrated circuit chip according to claim 19, wherein the plurality of chip capacitors are arranged closer to a periphery of the integrated circuit chip than to a center of the integrated circuit chip. Implementation method. 22. The integrated circuit chip according to claim 20, wherein the plurality of chip resistors are arranged closer to a periphery of the integrated circuit chip than to a center of the integrated circuit chip. Implementation method. 23. The multi-chip capacitor according to claim 19, wherein the plurality of chip capacitors are thin near the center of the integrated circuit chip and thick near the periphery of the integrated circuit chip. Characteristic integrated circuit chip mounting method. 24. The semiconductor device according to claim 20, wherein the plurality of chip resistors are thin near the center of the integrated circuit chip and thick near the periphery of the integrated circuit chip. Characteristic integrated circuit chip mounting method. 25. The wiring board according to claim 14, wherein the wiring board is made of an epoxy-based organic resin.
A method of mounting an integrated circuit chip, which is either a ceramic substrate or a substrate having a thin film wiring layer on a ceramic substrate. 26. The connection between the integrated circuit chip and the wiring board according to claim 14, wherein the connection between the integrated circuit chip and the wiring board is made of an Au ball bump provided on the integrated circuit chip side and a conductive resin provided on the wiring board side. In / S
A method for mounting an integrated circuit chip, which is realized by bonding with an n-based solder or an Ag / Sn-based solder.