JP2003092382A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the sameInfo
- Publication number
- JP2003092382A JP2003092382A JP2001283790A JP2001283790A JP2003092382A JP 2003092382 A JP2003092382 A JP 2003092382A JP 2001283790 A JP2001283790 A JP 2001283790A JP 2001283790 A JP2001283790 A JP 2001283790A JP 2003092382 A JP2003092382 A JP 2003092382A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- hole
- resin member
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、一主面に多数個の
ランド部が形成された基板に、このランド部と電気的に
接続する多数個の電極端子が設けられた半導体素子を実
装した半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mounts a semiconductor device having a substrate having a large number of lands formed on one main surface and a large number of electrode terminals electrically connected to the lands. The present invention relates to a semiconductor device and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】近年では、携帯電話に代表される情報通
信技術の進展によって、様々な情報通信機器に例えば高
周波通信モジュールや高速シリアルインターフェース等
が実装されている。特に、携帯型の情報通信機器におい
ては、これら高周波通信モジュールや高速シリアルイン
ターフェースの軽薄短小化が要望されている。そして、
この要望を満足させる技術として、図８に示すような半
導体素子を基板に直接実装させた、すなわちフェースダ
ウン実装させた半導体装置１００が注目されている。2. Description of the Related Art In recent years, with the development of information communication technology represented by a mobile phone, various information communication equipments are equipped with, for example, a high frequency communication module, a high speed serial interface and the like. Particularly, in portable information communication devices, there is a demand for making these high-frequency communication modules and high-speed serial interfaces light, thin and short. And
As a technique for satisfying this demand, a semiconductor device 100 in which a semiconductor element as shown in FIG. 8 is directly mounted on a substrate, that is, face-down mounting is attracting attention.
【０００３】半導体装置１００は、半導体素子１０１の
周囲を囲むように設けられた電極部１０２に形成された
接続端子１０３と、基板１０４の表面に予めパターニン
グされた配線部１０５の一部に形成されたランド部１０
６とが電気的に接続され、これら半導体素子１０１と基
板１０４との間に樹脂部材１０７が供給された構造を有
している。この樹脂部材１０７は、半導体素子１０１及
び基板１０４のそれぞれの熱膨張係数の違いによって半
導体素子１０１と基板１０４との接続が外れてしまわな
いように、その接続部を覆うことで補強している。ま
た、樹脂部材１０７は、半導体素子１０１の電極部１０
２や接続端子１０３を覆うことで、電極部１０２及び接
続端子１０３が湿度等によって腐食してしまうこと防い
でいる。The semiconductor device 100 is formed on the connection terminal 103 formed on the electrode portion 102 provided so as to surround the periphery of the semiconductor element 101, and on a part of the wiring portion 105 patterned in advance on the surface of the substrate 104. Land part 10
6 is electrically connected, and a resin member 107 is supplied between the semiconductor element 101 and the substrate 104. The resin member 107 is reinforced by covering its connection portion so that the connection between the semiconductor element 101 and the substrate 104 is not disconnected due to the difference in thermal expansion coefficient between the semiconductor element 101 and the substrate 104. Further, the resin member 107 serves as the electrode portion 10 of the semiconductor element 101.
By covering 2 and the connection terminal 103, the electrode portion 102 and the connection terminal 103 are prevented from being corroded by humidity or the like.
【０００４】[0004]
【発明が解決しようとする課題】ところで、上述したよ
うな半導体装置１００では、半導体素子１０１が電極部
１０２ばかりでなく、例えば素子表面のパターン配線等
も樹脂部材１０７で覆われてしまうことがある。この場
合、半導体素子１０１の容量成分が増加してしまい、イ
ンピーダンスが変化してしまうことがある。In the semiconductor device 100 as described above, the resin element 107 may cover not only the semiconductor element 101 but also the electrode portion 102 and, for example, the pattern wiring on the element surface. . In this case, the capacitance component of the semiconductor element 101 may increase and the impedance may change.
【０００５】例えば半導体素子１０１にＭＭＩＣ（Mono
lithic Microwave Integrated Circuit）や、高速デジ
タルＩＣ等の場合、素子表面のパターン配線がマイクロ
ストリップ線路や、コプレナー線路等で形成されている
ことから、インピーダンスマッチングが損なわれてしま
い、ゲイン特性が劣化することがあった。また、高周波
ＩＣ等の場合、素子表面のパターン配線として形成され
たパッシブ素子の定数変化等が生じてしまい、高周波特
性が劣化してしまうといった問題もあった。For example, in the semiconductor element 101, the MMIC (Mono
In the case of a lithic Microwave Integrated Circuit) or a high-speed digital IC, the pattern wiring on the element surface is formed of a microstrip line, a coplanar line, or the like, which impairs impedance matching and deteriorates the gain characteristic. was there. Further, in the case of a high-frequency IC or the like, there is also a problem that a constant element of the passive element formed as a pattern wiring on the element surface is changed and the high-frequency characteristic is deteriorated.
【０００６】そこで、図９に示すように、これらの問題
を解決する半導体装置１１０は、半導体素子１１１の周
囲を囲むように設けられた電極部１１２に形成された電
極端子１１２と、基板１１４の配線部１１５の一部に形
成されたランド部１１６とが電気的に接続部１１７で接
続され、これら半導体素子１１１と基板１１４との間で
樹脂部材１１８が、半導体素子１１１の周囲だけに隙間
なく、すなわち接続部１１７付近だけを被覆するように
隙間なく供給されたフェースダウン実装構造を有してい
る。このため、半導体装置１１０では、半導体素子１１
１と基板１１４との間に樹脂部材１１８が供給されてい
ない中空部１１９を有しており、半導体素子１１１表面
のパターン配線が樹脂部材１１８に覆われてしまうこと
がないことから、ゲイン特性や高周波特性の劣化を防止
することができる。Therefore, as shown in FIG. 9, in a semiconductor device 110 which solves these problems, an electrode terminal 112 formed on an electrode portion 112 provided so as to surround the periphery of a semiconductor element 111 and a substrate 114. The land portion 116 formed in a part of the wiring portion 115 is electrically connected by the connection portion 117, and the resin member 118 is provided between the semiconductor element 111 and the substrate 114 only around the semiconductor element 111 without a gap. That is, it has a face-down mounting structure that is supplied without gap so as to cover only the vicinity of the connecting portion 117. Therefore, in the semiconductor device 110, the semiconductor element 11
1 and the substrate 114 have a hollow portion 119 to which the resin member 118 is not supplied, and the pattern wiring on the surface of the semiconductor element 111 is not covered with the resin member 118. It is possible to prevent deterioration of high frequency characteristics.
【０００７】しかしながら、このような半導体装置１１
０は、製造工程において、半導体素子１１１を基板１１
４に実装した後に、抵抗体部品、コンデンサ部品等の実
装や、基板１１４の他基板への実装が、例えばはんだリ
フロー法等の熱処理加工によって行われる。このため、
半導体装置１１０では、中空部１１９に密封された水分
や樹脂部材１１８に含まれる水分が、はんだリフロー等
の熱処理加工が施される際の急激な温度上昇によって体
積膨張を伴う水蒸気となり、中空部１１９の内圧が上昇
することがある。この場合、半導体装置１１０では、中
空部１１９の内圧を上昇させた水蒸気が、接続部１１７
を破壊しながら開放されることがあり、半導体素子１１
１と基板１１４との接続の外れや、樹脂部材１１８にひ
び割れが生じてしまうといった問題になった。However, such a semiconductor device 11
0 indicates that the semiconductor element 111 is the substrate 11 in the manufacturing process.
After mounting on No. 4, the mounting of the resistor parts, the capacitor parts, etc., and the mounting of the board 114 on another board are performed by heat treatment such as solder reflow method. For this reason,
In the semiconductor device 110, the moisture sealed in the hollow portion 119 or the moisture contained in the resin member 118 becomes water vapor accompanied by volume expansion due to a rapid temperature rise during heat treatment such as solder reflow, and thus the hollow portion 119. The internal pressure of may increase. In this case, in the semiconductor device 110, the water vapor that has increased the internal pressure of the hollow portion 119 causes the connection portion 117 to flow.
The semiconductor element 11 may be opened while being destroyed.
1 and the substrate 114 are disconnected, and the resin member 118 is cracked.
【０００８】したがって、本発明は、このような従来の
事情に鑑みて考案されたものであり、半導体素子を基板
に実装した際に、基板と半導体素子との接続部が剥離す
ることを防止した半導体装置及びその製造方法を提供す
ることを目的とする。Therefore, the present invention has been devised in view of such conventional circumstances, and prevents the connecting portion between the substrate and the semiconductor element from peeling off when the semiconductor element is mounted on the substrate. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.
【０００９】[0009]
【課題を解決するための手段】上述の目的を達成するた
めに、本発明に係る半導体装置は、貫通孔が設けられて
いると共に、この貫通孔を囲む多数個のランド部が設け
られた基板と、基板に設けられたランド部と電気的に接
続される多数個の電極端子を有し、貫通孔を覆うように
して基板の主面上に実装された半導体素子と、半導体素
子の外周部に供給されることによって、基板と半導体素
子との間の空間部の周囲を閉塞すると共に、ランド部と
電極端子との接続部を被覆する樹脂部材と、基板に、は
んだリフロー処理によって溶接される回路部材とを備
え、空間部が、貫通孔を介して開放空間部として構成さ
れている。In order to achieve the above-mentioned object, a semiconductor device according to the present invention is provided with a through hole and a substrate provided with a large number of lands surrounding the through hole. A semiconductor element having a large number of electrode terminals electrically connected to a land portion provided on the substrate and mounted on the main surface of the substrate so as to cover the through hole, and an outer peripheral portion of the semiconductor element. Is supplied to the resin member that closes the periphery of the space between the substrate and the semiconductor element and covers the connection portion between the land portion and the electrode terminal, and is welded to the substrate by the solder reflow process. A circuit member, and the space portion is configured as an open space portion through the through hole.
【００１０】本発明に係る半導体装置は、樹脂部材によ
って閉塞された基板と半導体素子との間の空間部が、貫
通孔を介して開放空間部として構成されており、半導体
素子を実装した基板に回路部材を溶接するはんだリフロ
ー処理といった熱処理加工が施された際の急激な温度上
昇により、基板と半導体素子との間の空間部で体積膨張
した気体が、貫通孔を通って放出されることから、体積
膨張した気体の圧力で基板と半導体素子との接続部が剥
離してしまうことが防止される。In the semiconductor device according to the present invention, the space between the substrate closed by the resin member and the semiconductor element is configured as an open space through the through hole, and the semiconductor element is mounted on the substrate. Due to the sudden temperature rise when heat treatment such as solder reflow processing for welding circuit members is performed, the gas volume expanded in the space between the substrate and the semiconductor element is released through the through hole. It is possible to prevent the connecting portion between the substrate and the semiconductor element from peeling off due to the pressure of the gas whose volume has expanded.
【００１１】また、上述の目的を達成するために、本発
明に係る半導体装置の製造方法は、多数個のランド部が
設けられた基板に貫通孔を形成する孔形成工程と、基板
に設けられたランド部と電気的に接続する多数個の電極
端子を有する半導体素子を、貫通孔を覆うようにして基
板の主面上に実装させる素子実装工程と、半導体素子の
外周部に、ランド部と電極端子との接続部を被覆させる
ように樹脂部材を供給する樹脂供給工程と、半導体素子
が実装された基板に、回路部材をはんだ合金で溶接させ
るはんだリフロー処理を施すはんだリフロー工程とを有
している。この半導体装置の製造方法は、樹脂供給工程
が、基板と半導体素子との間の空間部が貫通孔を介して
開放空間部となるように、空間部の周囲を閉塞させるよ
うに樹脂部材を供給している。In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention includes a hole forming step of forming a through hole in a substrate provided with a large number of land portions, and a step of forming the through hole in the substrate. An element mounting step of mounting a semiconductor element having a large number of electrode terminals electrically connected to the land portion on the main surface of the substrate so as to cover the through hole, and a land portion on the outer peripheral portion of the semiconductor element. It has a resin supply step of supplying a resin member so as to cover the connection part with the electrode terminal, and a solder reflow step of performing a solder reflow process of welding a circuit member with a solder alloy to the substrate on which the semiconductor element is mounted. ing. In this method of manufacturing a semiconductor device, in the resin supplying step, the resin member is supplied so as to close the space around the space so that the space between the substrate and the semiconductor element becomes an open space through the through hole. is doing.
【００１２】本発明に係る半導体装置の製造方法は、基
板と半導体素子との間の空間部が貫通孔を介して開放空
間部となるように、空間部の周囲を閉塞させるように樹
脂部材を供給した後に、半導体素子を実装した基板には
んだリフロー処理を施すことから、はんだリフロー処理
といった熱処理加工の際の急激な温度上昇によって基板
と半導体素子との間の空間部で体積膨張した気体が、貫
通孔を通って放出することによって、体積膨張した気体
の圧力によって基板と半導体素子との接続部が剥離する
ことが防止された半導体装置を得ることができる。In the method of manufacturing a semiconductor device according to the present invention, a resin member is provided to close the space so that the space between the substrate and the semiconductor element becomes an open space through the through hole. After the supply, since the solder reflow process is performed on the substrate on which the semiconductor element is mounted, the gas whose volume is expanded in the space between the substrate and the semiconductor device due to the rapid temperature rise during the heat treatment process such as the solder reflow process, By releasing the gas through the through hole, it is possible to obtain a semiconductor device in which the connection between the substrate and the semiconductor element is prevented from peeling off due to the pressure of the gas whose volume has expanded.
【００１３】さらに、上述の目的を達成するために、本
発明に係る半導体装置の製造方法は、多数個のランド部
が設けられた基板に貫通孔を形成する孔形成工程と、基
板の主面上に、基板の貫通孔を囲むと共にランド部を覆
うように樹脂部材を供給する樹脂供給工程と、樹脂部材
に貫入させることでランド部と電気的に接続する多数個
の電極端子を有する半導体素子を、貫通孔を覆うように
して基板の主面上に実装させる素子実装工程と、半導体
素子が実装された基板に、回路部材をはんだ合金で溶接
させるはんだリフロー処理を施すはんだリフロー工程と
を有している。この半導体装置の製造方法は、素子実装
工程が、基板と半導体素子との間の空間部が貫通孔を介
して開放空間部となるように、空間部の周囲を樹脂部材
で閉塞させるように半導体素子を実装させている。Further, in order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention comprises a hole forming step of forming a through hole in a substrate having a large number of lands, and a main surface of the substrate. A semiconductor device having a resin supplying step of supplying a resin member so as to surround the through hole of the substrate and covering the land portion, and a plurality of electrode terminals electrically connected to the land portion by being penetrated into the resin member. Is mounted on the main surface of the board so as to cover the through hole, and a solder reflow step of performing a solder reflow process of welding a circuit member with a solder alloy on the board on which the semiconductor element is mounted. is doing. In this method for manufacturing a semiconductor device, in the element mounting step, a semiconductor member is used so that a space between the substrate and the semiconductor element becomes an open space through the through hole, and the space is closed by a resin member. The element is mounted.
【００１４】本発明に係る半導体装置の製造方法は、基
板と半導体素子との間の空間部が貫通孔を介して開放空
間部となるように、空間部の周囲を樹脂部材で閉塞させ
るように半導体素子を実装させた後に、半導体素子を実
装した基板にはんだリフロー処理を施すことから、はん
だリフロー処理といった熱処理加工の際の急激な温度上
昇によって基板と半導体素子との間の空間部で体積膨張
したの気体が、貫通孔を通って放出することによって、
体積膨張した気体の圧力によって基板と半導体素子との
接続部が剥離することが防止された半導体装置を得るこ
とができる。In the method of manufacturing a semiconductor device according to the present invention, the space between the substrate and the semiconductor element is closed with a resin member so that the space becomes an open space through the through hole. After the semiconductor element is mounted, the substrate on which the semiconductor element is mounted is subjected to solder reflow treatment, and the volume expansion in the space between the substrate and semiconductor element due to the rapid temperature rise during heat treatment such as solder reflow treatment. By releasing the gas through the through hole,
It is possible to obtain a semiconductor device in which the connection between the substrate and the semiconductor element is prevented from peeling off due to the pressure of the gas whose volume has expanded.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照にして詳細に説明する。本発明の実施の形
態として図１及び図２に示す半導体装置１は、基板２
と、基板２の一主面上に実装された半導体素子３と、基
板２と半導体素子３との間で半導体素子３の周囲を囲む
ように供給された樹脂部材４とを備えている。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. A semiconductor device 1 shown in FIGS. 1 and 2 as an embodiment of the present invention is a substrate 2
A semiconductor element 3 mounted on one main surface of the substrate 2, and a resin member 4 supplied between the substrate 2 and the semiconductor element 3 so as to surround the periphery of the semiconductor element 3.
【００１６】基板２は、一主面上に予めパターニングさ
れ、且つ一部に半導体素子３と電気的に接続するランド
部５が形成された配線部６を有している。そして、この
基板２には、主面上の半導体素子３が実装される領域の
所定の位置に、一主面側から他主面側に貫通する貫通孔
７が設けられている。The substrate 2 has a wiring portion 6 which is pre-patterned on one main surface and in which a land portion 5 electrically connected to the semiconductor element 3 is formed. The substrate 2 is provided with a through hole 7 penetrating from the one main surface side to the other main surface side at a predetermined position in the region where the semiconductor element 3 is mounted on the main surface.
【００１７】半導体素子３には、一主面上に周囲を囲む
ように複数の電極部８が設けられ、これら電極部８に基
板２のランド部５に接続するための電極端子９がそれぞ
れ形成されている。この半導体素子３は、電極部８側の
面と基板２の配線部６側の面とを対向させるように、基
板２に設けられた貫通孔７上に直接実装、すなわちフェ
ースダウン実装されることとなる。The semiconductor element 3 is provided with a plurality of electrode portions 8 on one main surface so as to surround the periphery thereof, and electrode terminals 9 for connecting to the land portions 5 of the substrate 2 are formed on the electrode portions 8. Has been done. The semiconductor element 3 should be directly mounted on the through hole 7 provided in the substrate 2, that is, face down mounting, so that the surface on the electrode portion 8 side and the surface on the wiring portion 6 side of the substrate 2 face each other. Becomes
【００１８】樹脂部材４は、基板２に設けられた貫通孔
７を埋めてしまうことなく、且つ基板２と半導体素子３
との間を隙間なく囲むように供給されている。また、樹
脂部材４は、基板２と半導体素子３との間で、少なくと
も基板２のランド部５と半導体素子３の電極端子９との
接続部１０、及び半導体素子３の電極部８を被覆するよ
うに供給されている。このため、基板２と半導体素子３
との間には、樹脂部材４が供給されていない領域として
中空部１１が形成されることとなる。そして、この中空
部１１は、貫通孔７を介して外部空間に通じ、開放され
た空間となっている。なお、樹脂部材４には、例えばエ
ポキシ系の樹脂等を用いる。The resin member 4 does not fill the through hole 7 formed in the substrate 2 and the substrate 2 and the semiconductor element 3 are not filled.
It is supplied so as to surround the space with no gap. Further, the resin member 4 covers at least the connecting portion 10 between the land portion 5 of the substrate 2 and the electrode terminal 9 of the semiconductor element 3 and the electrode portion 8 of the semiconductor element 3 between the substrate 2 and the semiconductor element 3. Is being supplied. Therefore, the substrate 2 and the semiconductor element 3
A hollow portion 11 is formed between the and, as a region to which the resin member 4 is not supplied. The hollow portion 11 communicates with the external space through the through hole 7 and is an open space. The resin member 4 is made of epoxy resin, for example.
【００１９】次に、以上のような構成の半導体装置１の
製造方法について説明する。この半導体装置１を製造す
る際は、先ず、図３に示すように、半導体素子３の周囲
を囲むように設けられた電極部８に電極端子９を形成す
る。この電極端子９は、例えばはんだ合金や金等の金属
材料からなり、スパッタ法、めっき法、クリームはんだ
印刷法或いはワイヤーボンド法等によって形成される。
次に、図４が示すように、基板２の主面上において、半
導体素子３が実装される領域内に、一主面側から他主面
側に貫通する貫通孔７を例えばドリル等を用いた穿孔加
工で形成する。Next, a method of manufacturing the semiconductor device 1 having the above structure will be described. When manufacturing the semiconductor device 1, first, as shown in FIG. 3, the electrode terminals 9 are formed in the electrode portions 8 provided so as to surround the periphery of the semiconductor element 3. The electrode terminal 9 is made of, for example, a metal material such as solder alloy or gold, and is formed by a sputtering method, a plating method, a cream solder printing method, a wire bond method, or the like.
Next, as shown in FIG. 4, on the main surface of the substrate 2, a through hole 7 penetrating from one main surface side to the other main surface side is formed in a region where the semiconductor element 3 is mounted, by using, for example, a drill. It is formed by drilling.
【００２０】次に、図５に示すように、半導体素子３の
周囲を囲むように設けられている電極端子９と、電極端
子９に対応する位置のランド部５とを電気的に接続させ
ることで、基板２の主面上に半導体素子３を実装する。Next, as shown in FIG. 5, the electrode terminal 9 provided so as to surround the semiconductor element 3 and the land portion 5 at a position corresponding to the electrode terminal 9 are electrically connected. Then, the semiconductor element 3 is mounted on the main surface of the substrate 2.
【００２１】このとき、電極端子９がはんだ合金で形成
されている場合には、ランド部５の電極端子９が接続さ
れる位置にはんだ合金を供給し、はんだリフロー法等に
よってランド部５側に供給されたはんだ合金を溶融さ
せ、この溶融したはんだ合金に半導体素子３側の電極端
子９を鑞付けすることで、ランド部５と電極端子９とを
接続させる。また、電極端子９が金で形成されている場
合には、ランド部５側にはんだ合金を供給して電極端子
９を鑞付けするか、若しくは、ランド部５の電極端子９
が接続される位置に金めっき加工を施して金めっき部を
形成し、この金めっき部と半導体素子３側の電極端子９
との接触部に熱処理加工又は超音波加工を施すことで金
の拡散接合によって、ランド部５と電極端子９とを接続
させる。At this time, when the electrode terminal 9 is formed of a solder alloy, the solder alloy is supplied to the land portion 5 at a position where the electrode terminal 9 is connected, and the land portion 5 side is subjected to the solder reflow method or the like. The land portion 5 and the electrode terminal 9 are connected by melting the supplied solder alloy and brazing the electrode terminal 9 on the semiconductor element 3 side to the melted solder alloy. When the electrode terminal 9 is formed of gold, solder alloy is supplied to the land portion 5 side to braze the electrode terminal 9, or the electrode terminal 9 of the land portion 5 is brazed.
Gold-plating is applied to the position where the connection is made to form a gold-plated portion, and the gold-plated portion and the electrode terminal 9 on the semiconductor element 3 side are formed.
The land portion 5 and the electrode terminal 9 are connected to each other by a heat treatment process or an ultrasonic wave process on the contact portion with and by diffusion bonding of gold.
【００２２】次に、図６に示すように、半導体素子３の
周囲を囲み、且つ基板２のランド部５と半導体素子３の
電極端子９との接続部１０、及び半導体素子３の電極部
８を被覆するように、基板２と半導体素子３との間に樹
脂部材４を例えばディスペンサー等で供給する。このと
き、樹脂部材４は、粘性及びチクソ性が低すぎると例え
ば毛細管現象等により基板２と半導体素子３との間全体
や貫通孔７内部に充填される虞があることから、適宜な
粘性及びチクソ性のものが用いられている。樹脂部材４
の粘性及びチクソ性は、樹脂に対するシリカ等の無機材
料の充填量や、樹脂の組成比率等を調節することで容易
に制御できる。Next, as shown in FIG. 6, the semiconductor element 3 is surrounded and the connection portion 10 between the land portion 5 of the substrate 2 and the electrode terminal 9 of the semiconductor element 3 and the electrode portion 8 of the semiconductor element 3 are formed. The resin member 4 is supplied between the substrate 2 and the semiconductor element 3 by a dispenser or the like so as to cover the substrate. At this time, if the resin member 4 is too low in viscosity and thixotropy, the resin member 4 may be filled in the entire space between the substrate 2 and the semiconductor element 3 or the inside of the through hole 7 due to, for example, a capillary phenomenon. Thixotropic ones are used. Resin member 4
The viscosity and thixotropy can be easily controlled by adjusting the filling amount of an inorganic material such as silica with respect to the resin and the composition ratio of the resin.
【００２３】次に、基板２と半導体素子３との間に供給
された樹脂部材４を所定の条件下で硬化させる。この樹
脂部材４が熱硬化型の場合には、樹脂部材４の周囲を硬
化が促進される条件の温度雰囲気にすることで、樹脂部
材４を硬化させる。この熱硬化型の樹脂部材４において
は、硬化させる温度で加熱させると粘性が低下するが、
例えばアミン系の硬化剤等を用いたり、硬化が早い樹脂
組成にすることにより毛細管現象を抑制することができ
る。また、樹脂部材４が光硬化型の場合には、樹脂部材
４に硬化が促進される条件の波長を有する光線を照射す
ることで、樹脂部材４を硬化させる。Next, the resin member 4 supplied between the substrate 2 and the semiconductor element 3 is cured under predetermined conditions. When the resin member 4 is a thermosetting type, the resin member 4 is hardened by setting the temperature around the resin member 4 to be a temperature atmosphere that promotes hardening. When the thermosetting resin member 4 is heated at a curing temperature, the viscosity is reduced,
For example, the capillarity can be suppressed by using an amine-based curing agent or the like, or by using a resin composition that cures quickly. Further, when the resin member 4 is a photo-curing type, the resin member 4 is cured by irradiating the resin member 4 with a light beam having a wavelength of a condition for promoting the curing.
【００２４】次に、半導体素子３が実装された基板２
に、例えば抵抗体やコンデンサ等の回路部材（図示せ
ず。）をはんだ合金で溶接させるはんだリフロー処理に
よって取り付ける。Next, the substrate 2 on which the semiconductor element 3 is mounted
Then, a circuit member (not shown) such as a resistor or a capacitor is attached by a solder reflow process of welding with a solder alloy.
【００２５】以上のようにして、基板２の貫通孔７上に
半導体素子３や回路部材等が実装され、半導体素子３の
周囲だけを囲むように基板２と半導体素子３との間に樹
脂部材４が供給された半導体装置１が製造される。そし
て、上述した方法によって製造された半導体装置１は、
貫通孔７が設けられた基板２のランド部５と、貫通孔７
上に配置された半導体素子３の電極端子９との接続部１
０を被覆する樹脂部材４が、基板２と半導体素子３との
間で中空部１１を閉塞するように供給されることによ
り、この中空部１１が貫通孔７を介して外部空間に通じ
て開放された構造となっている。As described above, the semiconductor element 3 and the circuit member are mounted on the through hole 7 of the substrate 2, and the resin member is provided between the substrate 2 and the semiconductor element 3 so as to surround only the periphery of the semiconductor element 3. The semiconductor device 1 to which 4 is supplied is manufactured. Then, the semiconductor device 1 manufactured by the above-mentioned method is
The land portion 5 of the substrate 2 provided with the through hole 7 and the through hole 7
Connection part 1 with electrode terminal 9 of semiconductor element 3 arranged above
The resin member 4 covering 0 is supplied so as to close the hollow portion 11 between the substrate 2 and the semiconductor element 3, so that the hollow portion 11 is opened to the outside space through the through hole 7. It has a structured structure.
【００２６】このような構造の半導体装置１では、例え
ば中空部１１内の水分や樹脂部材４に含まれる水分が、
半導体素子３を実装した基板２にはんだリフローといっ
た熱処理加工が施された際の急激な温度上昇によって、
水蒸気となり中空部１１で急激に体積膨張しても、中空
部１１内に発生した水蒸気を貫通孔７を介して外部空間
に放出することができる。したがって、半導体装置１で
は、中空部１１に発生した水蒸気の圧力によって、基板
２のランド部５と半導体素子３の電極端子９との接続部
１０が剥離してしまうことや、基板２と半導体素子３と
の間で硬化した樹脂部材４にひび割れが生じてしまうこ
とを防止できる。In the semiconductor device 1 having such a structure, for example, the moisture in the hollow portion 11 and the moisture contained in the resin member 4 are
Due to the rapid temperature rise when heat treatment such as solder reflow is applied to the substrate 2 on which the semiconductor element 3 is mounted,
Even if it becomes water vapor and the volume of the air is rapidly expanded in the hollow portion 11, the water vapor generated in the hollow portion 11 can be discharged to the external space through the through hole 7. Therefore, in the semiconductor device 1, the connection portion 10 between the land portion 5 of the substrate 2 and the electrode terminal 9 of the semiconductor element 3 is separated due to the pressure of the water vapor generated in the hollow portion 11, and the substrate 2 and the semiconductor element are separated. It is possible to prevent cracks from occurring in the resin member 4 that has been hardened between the two.
【００２７】また、この半導体装置１では、樹脂部材４
が接続部１０付近を覆うことによって、基板２と半導体
素子３との接続部１０を補強することから、接続部１０
に応力が掛かることで基板２と半導体素子３との接続が
外れてしまうことを防止できる。そして、この半導体装
置１では、樹脂部材４が少なくとも半導体素子３の電極
部８及び電極端子９を覆うことによって、電極部８及び
電極端子９が例えば湿度等で腐食してしまうことを防ぐ
ことができる。Further, in this semiconductor device 1, the resin member 4
Covers the vicinity of the connecting portion 10 to reinforce the connecting portion 10 between the substrate 2 and the semiconductor element 3, so that the connecting portion 10
It is possible to prevent disconnection between the substrate 2 and the semiconductor element 3 due to stress applied to the substrate. In the semiconductor device 1, the resin member 4 covers at least the electrode portion 8 and the electrode terminal 9 of the semiconductor element 3 to prevent the electrode portion 8 and the electrode terminal 9 from being corroded by, for example, humidity. it can.
【００２８】さらに、半導体装置１では、樹脂部材４
が、基板２と半導体素子３との間で、半導体素子２の周
囲を囲むように設けられた電極部８だけを被覆するよう
に供給されていることから、例えば半導体素子３の表面
に形成されたパターン配線等を樹脂部材４が覆うことが
なく、半導体素子３のゲイン特性や高周波特性の劣化を
防止することができる。Further, in the semiconductor device 1, the resin member 4
Is supplied so as to cover only the electrode portion 8 provided so as to surround the semiconductor element 2 between the substrate 2 and the semiconductor element 3, and thus is formed on the surface of the semiconductor element 3, for example. Since the resin member 4 does not cover the patterned wiring and the like, it is possible to prevent the gain characteristics and the high frequency characteristics of the semiconductor element 3 from deteriorating.
【００２９】さらにまた、半導体装置１では、基板２の
貫通孔７上に半導体素子３を実装した後に、基板２と半
導体素子３との間に樹脂部材４を供給することによっ
て、樹脂部材４を供給する際の中空部１１内の圧力が貫
通孔７を通って開放されることから、中空部１１内の圧
力が樹脂部材４に掛かることがなく、樹脂部材４を半導
体素子３の周囲に隙間なく供給することができる。Furthermore, in the semiconductor device 1, after mounting the semiconductor element 3 on the through hole 7 of the substrate 2, the resin member 4 is supplied between the substrate 2 and the semiconductor element 3 to remove the resin member 4. Since the pressure in the hollow portion 11 at the time of supply is released through the through hole 7, the pressure in the hollow portion 11 does not act on the resin member 4, and the resin member 4 is provided around the semiconductor element 3 with a gap. Can be supplied without.
【００３０】以上、基板２に半導体素子３を実装した後
に、基板２と半導体素子３との間に樹脂部材４を供給す
ることで得られた半導体装置１について説明したが、こ
の半導体装置１は、次に説明する第２の製造方法によっ
て製造されても良い。例えば、図７に示す第２の製造方
法によって製造される半導体装置２０は、基板２に樹脂
部材２１を供給した後に、半導体素子３を基板２に実装
することで得られる。以下の説明においては、半導体装
置２０における上述した半導体装置１と同等な構成及び
部位については、説明を省略するとともに、図面におい
て同じ符号を付するものとする。The semiconductor device 1 obtained by mounting the semiconductor element 3 on the substrate 2 and then supplying the resin member 4 between the substrate 2 and the semiconductor element 3 has been described above. It may be manufactured by the second manufacturing method described below. For example, the semiconductor device 20 manufactured by the second manufacturing method shown in FIG. 7 is obtained by supplying the resin member 21 to the substrate 2 and then mounting the semiconductor element 3 on the substrate 2. In the following description, the description of the same components and parts of the semiconductor device 20 as those of the semiconductor device 1 will be omitted, and the same reference numerals will be given in the drawings.
【００３１】第２の製造方法によって半導体装置２０を
製造する際は、先ず、図７（ａ）に示すように、一部に
ランド部５が形成された配線部６が予めパターニングさ
れた基板２を用意する。次に、基板２の主面上におい
て、半導体素子３が実装される領域内に、一主面側から
他主面側に貫通する貫通孔７を例えばドリル等を用いた
穿孔加工で形成する。When the semiconductor device 20 is manufactured by the second manufacturing method, first, as shown in FIG. 7A, the substrate 2 in which the wiring portion 6 in which the land portion 5 is partially formed is patterned in advance. To prepare. Next, on the main surface of the substrate 2, a through hole 7 penetrating from one main surface side to the other main surface side is formed in a region where the semiconductor element 3 is mounted by, for example, a drilling process using a drill or the like.
【００３２】次に、基板２に半導体素子３が実装された
際の半導体素子３の周囲を囲む位置に、ランド部５を覆
うように樹脂部材２１を供給する。この樹脂部材２１に
は、例えばＡＣＦ（Anisotropic Conductive Film）、
ＮＣＦ（Non-Conductive Film）等のフィルム状樹脂
や、ＡＣＰ（Anisotropic Conductive Paste）、ＮＣＰ
（Non-Conductive Paste）等のペースト状樹脂等の熱硬
化性樹脂、又は光硬化性樹脂等を用いる。Next, the resin member 21 is supplied to the position surrounding the periphery of the semiconductor element 3 when the semiconductor element 3 is mounted on the substrate 2 so as to cover the land portion 5. The resin member 21 includes, for example, ACF (Anisotropic Conductive Film),
Film-like resin such as NCF (Non-Conductive Film), ACP (Anisotropic Conductive Paste), NCP
A thermosetting resin such as a paste resin such as (Non-Conductive Paste) or a photocurable resin is used.
【００３３】次に、同図（ｂ）に示すように、半導体素
子３の周囲を囲むように設けられた電極部８に電極端子
９を形成する。次に、同図（ｃ）に示すように、半導体
素子３の電極部８に形成された電極端子９を、ランド部
５の電極端子９に対応する位置に設置し、例えばプレス
装置等を用いて電極端子９が樹脂部材２１に貫入するよ
うに半導体素子３を基板２に押しつけながら、樹脂部材
２１を所定の条件下で硬化させることで、基板２のラン
ド部５と半導体素子３の電極端子９とを接続する。この
とき、樹脂部材２１としてＡＣＦ、ＡＣＰ等を用いた場
合には、導電性粒子によって、ランド部５と電極端子９
とを接続させる。樹脂部材２１としてＮＣＦ、ＮＣＰ等
を用いた場合には、樹脂部材２１を硬化させる際の樹脂
部材２１の収縮力によって電極端子９をランド部５に押
しつけるように接触させることで、ランド部５と電極端
子９とを接続させる。Next, as shown in FIG. 3B, the electrode terminal 9 is formed on the electrode portion 8 provided so as to surround the semiconductor element 3. Next, as shown in FIG. 3C, the electrode terminals 9 formed on the electrode portion 8 of the semiconductor element 3 are installed at positions corresponding to the electrode terminals 9 of the land portion 5, and, for example, a pressing device is used. While the semiconductor element 3 is pressed against the substrate 2 so that the electrode terminal 9 penetrates into the resin member 21, the resin member 21 is cured under predetermined conditions, so that the land portion 5 of the substrate 2 and the electrode terminal of the semiconductor element 3 are pressed. 9 is connected. At this time, when ACF, ACP or the like is used as the resin member 21, the land portion 5 and the electrode terminal 9 are made of conductive particles.
And connect. When NCF, NCP, or the like is used as the resin member 21, the contraction force of the resin member 21 at the time of curing the resin member 21 brings the electrode terminal 9 into contact with the land portion 5 so as to press the land portion 5. The electrode terminal 9 is connected.
【００３４】次に、半導体素子３が実装された基板２
に、例えば抵抗体やコンデンサ等の回路部材（図示せ
ず。）をはんだ合金で溶接させるはんだリフロー処理に
よって取り付ける。Next, the substrate 2 on which the semiconductor element 3 is mounted
Then, a circuit member (not shown) such as a resistor or a capacitor is attached by a solder reflow process of welding with a solder alloy.
【００３５】以上のようにして、同図（ｄ）に示すよう
に、基板２の貫通孔７上に半導体素子３や回路部材等が
直接実装、すなわちフェースダウン実装された半導体装
置２０が製造される。この半導体装置２０は、樹脂部材
２１を基板２上に供給する際の樹脂部材２１の供給量を
制御することによって、例えば貫通孔７内部に充填され
ること等がなく、樹脂部材２１が基板２と半導体素子３
との間の空間、すなわち中空部１１だけを閉塞し、この
中空部１１が貫通孔７を介して外部空間に通じて開放さ
れた構造となっている。As described above, as shown in FIG. 3D, the semiconductor device 20 in which the semiconductor element 3, the circuit member and the like are directly mounted on the through hole 7 of the substrate 2, that is, the face-down mounting is manufactured. It In this semiconductor device 20, by controlling the supply amount of the resin member 21 when the resin member 21 is supplied onto the substrate 2, for example, the inside of the through hole 7 is not filled, and the resin member 21 is not included in the substrate 2. And semiconductor element 3
A space between and, that is, only the hollow portion 11 is closed, and the hollow portion 11 is opened to the outside space through the through hole 7.
【００３６】このような構造の半導体装置２０では、例
えば中空部１１内の水分や樹脂部材２１に含まれる水分
が、半導体素子３を実装した基板２にはんだリフローと
いった熱処理加工が施された際の急激な温度上昇によっ
て、水蒸気となり中空部１１で急激に体積膨張しても、
中空部１１内に発生した水蒸気を貫通孔７を介して外部
空間に放出することができる。したがって、半導体装置
２０では、中空部１１に発生した水蒸気の圧力によっ
て、基板２のランド部５と半導体素子３の電極端子９と
の接続部１０が剥離してしまうことや、基板２と半導体
素子３との間で硬化した樹脂部材２１にひび割れが生じ
てしまうことを防止できる。In the semiconductor device 20 having such a structure, for example, when the moisture in the hollow portion 11 or the moisture contained in the resin member 21 is subjected to heat treatment such as solder reflow on the substrate 2 on which the semiconductor element 3 is mounted. Due to the rapid temperature rise, even if the volume becomes steam and the volume of the hollow portion 11 rapidly expands,
The water vapor generated in the hollow portion 11 can be discharged to the external space through the through hole 7. Therefore, in the semiconductor device 20, the connection portion 10 between the land portion 5 of the substrate 2 and the electrode terminal 9 of the semiconductor element 3 is peeled off due to the pressure of the water vapor generated in the hollow portion 11, and the substrate 2 and the semiconductor element are separated. It is possible to prevent cracks from occurring in the resin member 21 that has been hardened between the two.
【００３７】また、この半導体装置２０では、樹脂部材
２１が基板２と半導体素子３との接続部１０を覆うこと
によってこの接続部１０を補強することから、接続部１
０に応力が掛かることで基板２と半導体素子３との接続
が外れてしまうことを防止できる。そして、この半導体
装置２０では、樹脂部材２１が少なくとも半導体素子３
の電極部８及び電極端子９を覆うことによって、電極部
８及び電極端子９が例えば湿度等で腐食してしまうこと
を防ぐことができる。Further, in this semiconductor device 20, since the resin member 21 covers the connecting portion 10 between the substrate 2 and the semiconductor element 3 to reinforce the connecting portion 10, the connecting portion 1
It is possible to prevent disconnection between the substrate 2 and the semiconductor element 3 due to the stress applied to 0. In the semiconductor device 20, the resin member 21 is at least the semiconductor element 3
By covering the electrode portion 8 and the electrode terminal 9 of the above, it is possible to prevent the electrode portion 8 and the electrode terminal 9 from being corroded by, for example, humidity.
【００３８】さらに、半導体装置２０では、樹脂部材２
１が基板２と半導体素子３との間で、半導体素子２の周
囲を囲むように設けられた電極部８だけを被覆するよう
に供給されていることから、例えば半導体素子３の表面
に形成されたパターン配線等を樹脂部材２１が覆うこと
がなく、半導体素子３のゲイン特性や高周波特性の劣化
を防止することができる。Further, in the semiconductor device 20, the resin member 2
Since 1 is supplied between the substrate 2 and the semiconductor element 3 so as to cover only the electrode portion 8 provided so as to surround the periphery of the semiconductor element 2, it is formed on the surface of the semiconductor element 3, for example. Since the resin member 21 does not cover the patterned wiring and the like, it is possible to prevent the gain characteristics and the high frequency characteristics of the semiconductor element 3 from being deteriorated.
【００３９】さらにまた、半導体装置２０では、貫通孔
７が形成された基板２に樹脂部材２１を供給した後に、
半導体素子３を基板２に接続することによって、半導体
素子３を接続する際の中空部１１内の圧力が貫通孔７を
通って開放されることから、中空部１１内の圧力による
基板２に対する半導体素子３の浮きを防ぎ、適切に半導
体素子３を基板２に接続することができる。Furthermore, in the semiconductor device 20, after the resin member 21 is supplied to the substrate 2 in which the through holes 7 are formed,
By connecting the semiconductor element 3 to the substrate 2, the pressure in the hollow portion 11 at the time of connecting the semiconductor element 3 is released through the through hole 7. Therefore, the semiconductor for the substrate 2 due to the pressure in the hollow portion 11 It is possible to prevent the element 3 from floating and appropriately connect the semiconductor element 3 to the substrate 2.
【００４０】[0040]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、貫通孔が設けられた基板の貫通孔を覆うように
半導体素子が実装され、樹脂部材によって基板と半導体
素子との間で閉塞された空間部が貫通孔を介して開放空
間部として構成された構造となっていることから、後の
工程で半導体素子を実装した基板にはんだリフローとい
った熱処理加工が施された際の急激な温度上昇により基
板と半導体素子との間で体積膨張した気体を、貫通孔を
通して放出することができる。したがって、本発明によ
れば、熱処理加工によって体積膨張した気体の圧力が基
板と半導体素子との間の空間部で上昇することがないこ
とから、基板と半導体素子との接続部が剥離すること
や、基板と半導体素子との間に供給された樹脂部材にひ
び割れが生じることを防止した半導体装置を得ることが
できる。As described above in detail, according to the present invention, the semiconductor element is mounted so as to cover the through hole of the substrate provided with the through hole, and the resin member is provided between the substrate and the semiconductor element. Since the space part that is closed by the structure is configured as an open space part through the through hole, it is possible to sharply change the temperature when heat treatment such as solder reflow is applied to the substrate on which the semiconductor element is mounted in a later process. The gas whose volume has expanded between the substrate and the semiconductor element due to the temperature rise can be discharged through the through hole. Therefore, according to the present invention, the pressure of the gas that has undergone volume expansion due to the heat treatment does not rise in the space between the substrate and the semiconductor element, so that the connection portion between the substrate and the semiconductor element peels off. Thus, it is possible to obtain a semiconductor device in which the resin member supplied between the substrate and the semiconductor element is prevented from cracking.
【図１】本発明に係る半導体装置を示す要部断面図であ
る。FIG. 1 is a cross-sectional view of essential parts showing a semiconductor device according to the present invention.
【図２】同半導体装置を示す要部平面図である。FIG. 2 is a main-portion plan view showing the semiconductor device.
【図３】同半導体装置の製造工程を説明するため図であ
り、半導体素子に接続端子が形成された状態を示す断面
図である。FIG. 3 is a view for explaining the manufacturing process of the semiconductor device, and a cross-sectional view showing a state in which the connection terminals are formed on the semiconductor element.
【図４】同半導体装置の製造工程を説明するため図であ
り、基板に貫通孔が形成された状態を示す断面図であ
る。FIG. 4 is a view for explaining the manufacturing process of the same semiconductor device, and a cross-sectional view showing a state in which a through hole is formed in the substrate.
【図５】同半導体装置の製造工程を説明するため図であ
り、基板に半導体素子を実装した状態を示す断面図であ
る。FIG. 5 is a view for explaining the manufacturing process of the semiconductor device, and a cross-sectional view showing a state in which the semiconductor element is mounted on the substrate.
【図６】同半導体装置の製造工程を説明するため図であ
り、完成した半導体装置の断面図である。FIG. 6 is a view for explaining the manufacturing process for the semiconductor device, and is a cross-sectional view of the completed semiconductor device.
【図７】半導体装置の他の製造方法を説明するための図
であり、同図（ａ）は基板の貫通孔の周囲に樹脂部材が
供給された状態を示す断面図、同図（ｂ）は半導体素子
に接続端子が形成された状態を示す断面図、同図（ｃ）
は基板に半導体素子を接続させた状態を示す断面図、同
図（ｄ）は完成した半導体装置を示す断面図である。7A and 7B are views for explaining another method of manufacturing a semiconductor device, wherein FIG. 7A is a sectional view showing a state in which a resin member is supplied around the through hole of the substrate, and FIG. Is a cross-sectional view showing a state in which a connection terminal is formed on a semiconductor element, FIG.
Is a cross-sectional view showing a state in which a semiconductor element is connected to a substrate, and FIG. 7D is a cross-sectional view showing a completed semiconductor device.
【図８】従来の半導体装置を示す要部断面図である。FIG. 8 is a main-portion cross-sectional view showing a conventional semiconductor device.
【図９】同半導体装置を示す要部断面図である。FIG. 9 is a main-portion cross-sectional view showing the semiconductor device.
１，２０ 半導体装置、２ 基板、３ 半導体素子、
４，２１ 樹脂部材、５ランド部、６ 配線部、７ 貫
通孔、８ 電極部、９ 電極端子、１０ 接続部、１１
中空部1, 20 semiconductor device, 2 substrate, 3 semiconductor element,
4, 21 resin member, 5 land portion, 6 wiring portion, 7 through hole, 8 electrode portion, 9 electrode terminal, 10 connection portion, 11
Hollow part
Claims (3)
通孔を囲む多数個のランド部が設けられた基板と、 上記基板に設けられた上記ランド部と電気的に接続され
る多数個の電極端子を有し、上記貫通孔を覆うようにし
て上記基板の主面上に実装された半導体素子と、 上記半導体素子の外周部に供給されることによって、上
記基板と上記半導体素子との間の空間部の周囲を閉塞す
ると共に、上記ランド部と上記電極端子との接続部を被
覆する樹脂部材と、 上記基板に、はんだリフロー処理によって溶接される回
路部材とを備え、 上記空間部が、上記貫通孔を介して開放空間部として構
成されていることを特徴とする半導体装置。1. A substrate having a through hole and a plurality of lands surrounding the through hole, and a plurality of lands electrically connected to the land provided on the substrate. Between the substrate and the semiconductor element, the semiconductor element having an electrode terminal and mounted on the main surface of the substrate so as to cover the through hole, and by being supplied to the outer peripheral portion of the semiconductor element. While closing the periphery of the space portion of, the resin member that covers the connection portion of the land portion and the electrode terminal, and the substrate, a circuit member welded by a solder reflow process, the space portion, A semiconductor device, which is configured as an open space through the through hole.
通孔を形成する孔形成工程と、 上記基板に設けられた上記ランド部と電気的に接続する
多数個の電極端子を有する半導体素子を、上記貫通孔を
覆うようにして上記基板の主面上に実装させる素子実装
工程と、 上記半導体素子の外周部に、上記ランド部と上記電極端
子との接続部を被覆させるように上記樹脂部材を供給す
る樹脂供給工程と、 上記半導体素子が実装された上記基板に、回路部材をは
んだ合金で溶接させるはんだリフロー処理を施すはんだ
リフロー工程とを有し、 上記樹脂供給工程は、上記基板と上記半導体素子との間
の空間部が上記貫通孔を介して開放空間部となるよう
に、上記空間部の周囲を閉塞させるように上記樹脂部材
を供給することを特徴とする半導体装置の製造方法。2. A semiconductor device having a hole forming step of forming a through hole in a substrate provided with a large number of land parts, and a large number of electrode terminals electrically connected to the land parts provided in the substrate. An element mounting step of mounting on the main surface of the substrate so as to cover the through hole, and the resin so that the outer peripheral portion of the semiconductor element covers the connection portion between the land portion and the electrode terminal. A resin supplying step of supplying a member, and a solder reflow step of performing a solder reflow process of welding a circuit member with a solder alloy to the board on which the semiconductor element is mounted, the resin supplying step is the same as the board. A semiconductor device manufacturing method characterized in that the resin member is supplied so as to close the space around the space so that the space between the semiconductor element and the semiconductor element becomes an open space through the through hole. Method.
通孔を形成する孔形成工程と、 上記基板の主面上に、上記基板の上記貫通孔を囲むと共
に上記ランド部を覆うように樹脂部材を供給する樹脂供
給工程と、 上記樹脂部材に貫入させることで上記ランド部と電気的
に接続する多数個の電極端子を有する半導体素子を、上
記貫通孔を覆うようにして上記基板の主面上に実装させ
る素子実装工程と、 上記半導体素子が実装された上記基板に、回路部材をは
んだ合金で溶接させるはんだリフロー処理を施すはんだ
リフロー工程とを有し、 上記素子実装工程は、上記基板と上記半導体素子との間
の空間部が上記貫通孔を介して開放空間部となるよう
に、上記空間部の周囲を上記樹脂部材で閉塞させるよう
に上記半導体素子を実装させることを特徴とする半導体
装置の製造方法。3. A hole forming step of forming a through hole in a substrate provided with a large number of lands, and surrounding the through hole of the substrate and covering the land on the main surface of the substrate. A resin supply step of supplying a resin member, and a semiconductor element having a large number of electrode terminals that are electrically connected to the lands by penetrating the resin member to cover the through hole, An element mounting step of mounting on a surface, a solder reflow step of performing a solder reflow process of welding a circuit member with a solder alloy to the substrate on which the semiconductor element is mounted, the element mounting step is the substrate The semiconductor element is mounted such that a space between the semiconductor element and the semiconductor element is an open space through the through hole, and the resin member surrounds the space. The method of manufacturing a semiconductor device to be.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001283790A JP2003092382A (en) | 2001-09-18 | 2001-09-18 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001283790A JP2003092382A (en) | 2001-09-18 | 2001-09-18 | Semiconductor device and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003092382A true JP2003092382A (en) | 2003-03-28 |
Family
ID=19107236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001283790A Pending JP2003092382A (en) | 2001-09-18 | 2001-09-18 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003092382A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7348263B2 (en) | 2005-03-01 | 2008-03-25 | Seiko Epson Corporation | Manufacturing method for electronic component, electronic component, and electronic equipment |
| JPWO2006062195A1 (en) * | 2004-12-09 | 2008-06-12 | 松下電器産業株式会社 | Semiconductor mounting board |
| US7863529B2 (en) | 2007-11-05 | 2011-01-04 | Seiko Epson Corporation | Electronic component |
| WO2014207786A1 (en) * | 2013-06-28 | 2014-12-31 | 株式会社 東芝 | Semiconductor package mounting structure, and camera head of endoscope apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000133664A (en) * | 1998-10-22 | 2000-05-12 | Sony Corp | Semiconductor device |
| JP2001156246A (en) * | 1999-11-25 | 2001-06-08 | Nec Corp | Mounting structure and mounting method for integrated circuit chip |
-
2001
- 2001-09-18 JP JP2001283790A patent/JP2003092382A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000133664A (en) * | 1998-10-22 | 2000-05-12 | Sony Corp | Semiconductor device |
| JP2001156246A (en) * | 1999-11-25 | 2001-06-08 | Nec Corp | Mounting structure and mounting method for integrated circuit chip |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2006062195A1 (en) * | 2004-12-09 | 2008-06-12 | 松下電器産業株式会社 | Semiconductor mounting board |
| US7348263B2 (en) | 2005-03-01 | 2008-03-25 | Seiko Epson Corporation | Manufacturing method for electronic component, electronic component, and electronic equipment |
| US7867830B2 (en) | 2005-03-01 | 2011-01-11 | Seiko Epson Corporation | Manufacturing method for electronic component with sealing film |
| US8664730B2 (en) | 2005-03-01 | 2014-03-04 | Seiko Epson Corporation | Manufacturing method for electronic component, electronic component, and electronic equipment |
| US7863529B2 (en) | 2007-11-05 | 2011-01-04 | Seiko Epson Corporation | Electronic component |
| US8097817B2 (en) | 2007-11-05 | 2012-01-17 | Seiko Epson Corporation | Electronic component |
| US8342859B2 (en) | 2007-11-05 | 2013-01-01 | Seiko Epson Corporation | Electronic component |
| WO2014207786A1 (en) * | 2013-06-28 | 2014-12-31 | 株式会社 東芝 | Semiconductor package mounting structure, and camera head of endoscope apparatus |
| JPWO2014207786A1 (en) * | 2013-06-28 | 2017-02-23 | 株式会社東芝 | Mounting structure of semiconductor package, camera head of endoscope device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101237172B1 (en) | Bump-on-lead flip chip interconnection | |
| KR100203030B1 (en) | Semiconductor device and method for manufacturing the same, and flexible film for mounting semiconductor chip | |
| KR100924510B1 (en) | Semiconductor device, its manufacturing method, and electronic apparatus | |
| JP5421863B2 (en) | Manufacturing method of semiconductor package | |
| WO2005076351A1 (en) | Module with built-in part and its manufacturing method | |
| JPH1064955A (en) | Structure for mounting semiconductor chip | |
| JP2000036520A (en) | Method for mounting flip chip and device therefor | |
| JP4864810B2 (en) | Manufacturing method of chip embedded substrate | |
| KR100452252B1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2003218289A (en) | Semiconductor device and method for manufacturing the same and print mask | |
| JP4129837B2 (en) | Manufacturing method of mounting structure | |
| JP2003092382A (en) | Semiconductor device and method for manufacturing the same | |
| JP2001060642A (en) | Semiconductor chip mounting method, semiconductor, and manufacture thereof | |
| JP3485509B2 (en) | Flip chip type semiconductor device and manufacturing method thereof | |
| JP2003152131A (en) | Hollow sealed package and its manufacturing method | |
| US20030201544A1 (en) | Flip chip package | |
| JP3804586B2 (en) | Manufacturing method of semiconductor device | |
| EP1369919A1 (en) | Flip chip package | |
| JP2940491B2 (en) | Flip-chip mounting structure and method in multi-chip module and flip-chip mounting substrate in multi-chip module | |
| JP2002016104A (en) | Mounting method of semiconductor device and manufacturing method of semiconductor device mounted assembly | |
| JP4285140B2 (en) | Manufacturing method of semiconductor device | |
| JP2705658B2 (en) | Electronic device assembly and method of manufacturing the same | |
| JP3234062B2 (en) | Semiconductor package and manufacturing method thereof | |
| JP3382516B2 (en) | Semiconductor package | |
| KR20050045628A (en) | Underfill-less flip chip type semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080814 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100916 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100928 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101118 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20110104 |