JPWO2014207786A1 - Mounting structure of semiconductor package, camera head of endoscope device - Google Patents

Mounting structure of semiconductor package, camera head of endoscope device Download PDF

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JPWO2014207786A1
JPWO2014207786A1 JP2014542617A JP2014542617A JPWO2014207786A1 JP WO2014207786 A1 JPWO2014207786 A1 JP WO2014207786A1 JP 2014542617 A JP2014542617 A JP 2014542617A JP 2014542617 A JP2014542617 A JP 2014542617A JP WO2014207786 A1 JPWO2014207786 A1 JP WO2014207786A1
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semiconductor package
wiring board
mounting structure
fill material
connection terminal
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義広 江頭
義広 江頭
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Toshiba Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10151—Sensor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

本発明の半導体パッケージの実装構造は、半導体装置が収容された半導体パッケージと、半導体パッケージと接続され、厚み方向に貫通する少なくとも１の貫通孔を有する配線基板と、半導体パッケージの全周に塗布され、半導体パッケージの側面及び配線基板の表面に密着して半導体パッケージと配線基板との接続を補強するサイドフィル材と、を具備する。The mounting structure of the semiconductor package of the present invention is applied to the entire circumference of the semiconductor package in which the semiconductor device is accommodated, the wiring substrate connected to the semiconductor package and having at least one through hole penetrating in the thickness direction. And a side fill material that reinforces the connection between the semiconductor package and the wiring board in close contact with the side surface of the semiconductor package and the surface of the wiring board.

Description

本発明の実施形態は、ＣＣＤイメージセンサやＣＭＯＳイメージセンサ等の固体撮像素子が収容された半導体パッケージの実装構造及び該実装構造を備えた内視鏡装置のカメラヘッドに関する。   Embodiments described herein relate generally to a mounting structure of a semiconductor package in which a solid-state imaging device such as a CCD image sensor or a CMOS image sensor is accommodated, and a camera head of an endoscope apparatus including the mounting structure.

内視鏡装置の撮像素子としてＣＣＤ（charge-coupled device）イメージセンサやＣＭＯＳ（相補性金属酸化膜半導体）イメージセンサ等の固体撮像素子が用いられている。これら固体撮像素子は、セラミック等によりパッケージされた状態で配線基板に実装される。ところで、内視鏡装置は、検体内へ挿入されるため使用毎及び定期的な滅菌が必要である。硬性内視鏡装置の場合、高温（例えば、１３４℃）と常温（例えば、室温）とを繰り返す（以下、熱サイクルと記載する）オートクレープ滅菌が行われるのが一般的である。   Solid-state imaging devices such as CCD (charge-coupled device) image sensors and CMOS (complementary metal oxide semiconductor) image sensors are used as imaging devices for endoscope apparatuses. These solid-state imaging devices are mounted on a wiring board in a state packaged with ceramic or the like. By the way, since an endoscope apparatus is inserted into a specimen, it needs to be sterilized every time it is used. In the case of a rigid endoscope apparatus, it is common to perform autoclave sterilization that repeats high temperature (for example, 134 ° C.) and room temperature (for example, room temperature) (hereinafter referred to as a heat cycle).

しかしながら、熱サイクルを繰り返すと、半導体パッケージと配線基板との熱膨張率の違いから、半導体パッケージと配線基板とを接続する半田にクラックが生じ、半導体装置との導通がとれなくなる問題が発生する。そこで、半導体パッケージの周囲の配線基板との隙間をサイドフィル材で封止し、熱サイクルによる不具合を抑制するようにしている。   However, when the thermal cycle is repeated, a problem arises in that the solder that connects the semiconductor package and the wiring board is cracked due to the difference in thermal expansion coefficient between the semiconductor package and the wiring board, and the semiconductor device cannot be electrically connected. Therefore, a gap with the wiring substrate around the semiconductor package is sealed with a side fill material so as to suppress problems due to thermal cycling.

特開２００８−２５８４９５号公報JP 2008-258495 A 特表２００３−５０１８４１号公報Japanese translation of PCT publication No. 2003-501841 特開２００２−２３２１３０号公報Japanese Patent Laid-Open No. 2002-232130

しかしながら、半導体パッケージの周囲の配線基板との隙間をサイドフィル材により封止した場合、半導体パッケージ下面と配線基板との間が密閉される。このためサイドフィル材を熱硬化させる際に、半導体パッケージと配線基板との間に存在する気体が膨張し、サイドフィル材に孔が発生するという問題がある。孔が発生する際には、サイドフィル材にボイド（気泡）（貫通孔を含む）による突起物等が発生する。そして、このボイドにより、検体内へ挿入される内視鏡装置のカメラヘッドの小型化が妨げられるという問題が発生する。   However, when the gap with the wiring substrate around the semiconductor package is sealed with the side fill material, the space between the lower surface of the semiconductor package and the wiring substrate is sealed. For this reason, when thermosetting the side fill material, there is a problem that the gas existing between the semiconductor package and the wiring board expands, and a hole is generated in the side fill material. When the holes are generated, protrusions or the like due to voids (bubbles) (including through holes) are generated in the side fill material. This void causes a problem that miniaturization of the camera head of the endoscope apparatus inserted into the specimen is hindered.

本発明の実施形態は、かかる従来の課題を解決するためになされたものであり、サイドフィル材に孔が発生しない半導体パッケージの実装構造及び該実装構造を備えた内視鏡装置のカメラヘッドを提供することを目的とする。   An embodiment of the present invention is made to solve such a conventional problem, and includes a mounting structure of a semiconductor package in which no hole is generated in a side fill material, and a camera head of an endoscope apparatus including the mounting structure. The purpose is to provide.

本発明の半導体パッケージの実装構造は、半導体装置が収容された半導体パッケージと、半導体パッケージと接続され、厚み方向に貫通する少なくとも１の貫通孔を有する配線基板と、半導体パッケージの側面及び配線基板の表面に密着して半導体パッケージの全周囲を封止するサイドフィル材と、を具備する。   The semiconductor package mounting structure of the present invention includes a semiconductor package in which a semiconductor device is accommodated, a wiring board connected to the semiconductor package and having at least one through-hole penetrating in the thickness direction, side surfaces of the semiconductor package, and the wiring board And a side fill material that is in close contact with the surface and seals the entire periphery of the semiconductor package.

本発明の実施形態は、サイドフィル材に孔が発生しない半導体パッケージの実装構造及び該実装構造を備えた内視鏡装置のカメラヘッドを提供することができる。   The embodiment of the present invention can provide a mounting structure of a semiconductor package in which no hole is generated in the side fill material, and a camera head of an endoscope apparatus including the mounting structure.

実施形態に係る撮像装置の構成図である。It is a block diagram of the imaging device which concerns on embodiment. 実施形態に係るカメラヘッドの構成図である。It is a block diagram of the camera head which concerns on embodiment. 配線基板の一部拡大断面図である。It is a partial expanded sectional view of a wiring board. サイドフィル材に孔が空いた例を示す断面図である。It is sectional drawing which shows the example in which the hole was opened in the sidefill material.

以下、図面を参照して、実施形態を詳細に説明する。
（実施形態）
図１は、実施形態に係る撮像装置１００（以下、撮像装置１００と記載する）の構成図である。撮像装置１００は、例えば、内視鏡装置であり、ヘッド部２００と、ＣＣＵ（Camera Control Unit）３００（以下、本体部３００と記載する）と、ヘッド部２００と本体部３００とを接続するカメラケーブル４００（配線ケーブル）とを備える。Hereinafter, embodiments will be described in detail with reference to the drawings.
(Embodiment)
FIG. 1 is a configuration diagram of an imaging apparatus 100 (hereinafter referred to as an imaging apparatus 100) according to an embodiment. The imaging apparatus 100 is, for example, an endoscope apparatus, and includes a head unit 200, a CCU (Camera Control Unit) 300 (hereinafter referred to as a main body unit 300), and a camera that connects the head unit 200 and the main body unit 300. A cable 400 (wiring cable).

ヘッド部２００は、イメージセンサ２１０が収容された半導体パッケージ２２０と、半導体パッケージ２２０を実装した配線基板２３０と、半導体パッケージ２２０及び配線基板２３０を収容する筐体２４０とを備える。なお、ヘッド部２００の詳細な構成については、図２を参照して後述する。   The head unit 200 includes a semiconductor package 220 in which the image sensor 210 is accommodated, a wiring board 230 on which the semiconductor package 220 is mounted, and a housing 240 that accommodates the semiconductor package 220 and the wiring board 230. The detailed configuration of the head unit 200 will be described later with reference to FIG.

本体部３００は、ＩＦ回路３０１と、メモリ３０２と、プロセッサ３０３と、ドライバ３０４と、コントローラ３０５と、電源回路３０６とを備える。   The main body unit 300 includes an IF circuit 301, a memory 302, a processor 303, a driver 304, a controller 305, and a power supply circuit 306.

ＩＦ回路３０１は、ヘッド部２００との間で制御信号やデータの送受信を行うためのインタフェースである。   The IF circuit 301 is an interface for transmitting and receiving control signals and data to and from the head unit 200.

メモリ３０２は、不揮発性メモリであり、例えば、シリアルＥＥＰＲＯＭ（Electrically Erasable Programmable Read-Only Memory）である。メモリ３０２には、ヘッド部２００の設定データ（動作モード）や補正データが記憶されている。   The memory 302 is a nonvolatile memory, and is, for example, a serial EEPROM (Electrically Erasable Programmable Read-Only Memory). The memory 302 stores setting data (operation mode) and correction data for the head unit 200.

プロセッサ３０３は、画像処理用のプロセッサである。プロセッサ３０３は、ヘッド部２００から送信される画像信号に種々の補正（例えば、ノイズ補正、ホワイトバランス、γ補正等）を行う。プロセッサ３０３は、補正後の画像信号を外部の表示装置５００（例えば、ＣＲＴ（Cathode Ray Tube）や液晶モニタ）へ出力する。   The processor 303 is a processor for image processing. The processor 303 performs various corrections (for example, noise correction, white balance, γ correction, etc.) on the image signal transmitted from the head unit 200. The processor 303 outputs the corrected image signal to an external display device 500 (for example, a CRT (Cathode Ray Tube) or a liquid crystal monitor).

ドライバ３０４は、イメージセンサ２１０の駆動回路である。ドライバ３０４は、コントローラ３０５からの制御に基づいてイメージセンサ２１０の駆動方式やフレームレートを変更する。また、ドライバ３０４は、イメージセンサ２１０へパルス信号（例えば、垂直同期や水平同期（転送パルス信号、リセットゲートパルス信号）のためのパルス信号）を出力する。   The driver 304 is a drive circuit for the image sensor 210. The driver 304 changes the driving method and the frame rate of the image sensor 210 based on the control from the controller 305. The driver 304 outputs a pulse signal (for example, a pulse signal for vertical synchronization or horizontal synchronization (transfer pulse signal, reset gate pulse signal)) to the image sensor 210.

コントローラ３０５は、メモリ３０２から補正データや設定データを読み出す。コントローラ３０５は、読み出した補正データや設定データに基づいて、プロセッサ３０３及びドライバ３０４を制御する。   The controller 305 reads correction data and setting data from the memory 302. The controller 305 controls the processor 303 and the driver 304 based on the read correction data and setting data.

電源回路３０６は、外部電源に接続される。電源回路３０６は、外部電源からの電力を所定の電圧に変換して本体部３００の構成回路（ＩＦ回路３０１、メモリ３０２、プロセッサ３０３、ドライバ３０４、コントローラ３０５）へ供給する。また、電源回路３０６からの電力は、カメラケーブル４００を介してヘッド部２００にも供給される。   The power supply circuit 306 is connected to an external power supply. The power supply circuit 306 converts electric power from the external power supply into a predetermined voltage and supplies it to the constituent circuits (IF circuit 301, memory 302, processor 303, driver 304, controller 305) of the main body 300. Further, power from the power supply circuit 306 is also supplied to the head unit 200 via the camera cable 400.

（半導体パッケージの実装構造）
図２は、カメラヘッド２００の構成図である。図２（ａ）は、カメラヘッド２００の平面図、図２（ｂ）は、図２（ａ）の線分Ｉ−Ｉでの断面図である。なお、図２では、筐体２４０の図示を省略している。以下、図２を参照して、半導体パッケージ２２０の配線基板２３０への実装構造について説明する。(Semiconductor package mounting structure)
FIG. 2 is a configuration diagram of the camera head 200. 2A is a plan view of the camera head 200, and FIG. 2B is a cross-sectional view taken along line I-I in FIG. 2A. In addition, illustration of the housing | casing 240 is abbreviate | omitted in FIG. Hereinafter, the mounting structure of the semiconductor package 220 on the wiring board 230 will be described with reference to FIG.

図２に示すように、半導体パッケージ２２０は、イメージセンサ２１０を収容する筐体２２０Ａと、無色透明な基板であるリッド２２０Ｂとを備える。イメージセンサ２１０は、例えば、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサやＣＣＤ（Charge Coupled Device）イメージセンサなどの固体撮像素子である。   As shown in FIG. 2, the semiconductor package 220 includes a housing 220 </ b> A that houses the image sensor 210 and a lid 220 </ b> B that is a colorless and transparent substrate. The image sensor 210 is a solid-state image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor.

筐体２２０Ａは、イメージセンサ２１０との接続端子Ｔ１と、配線基板２３０との接続端子Ｔ２とを有する。接続端子Ｔ１と接続端子Ｔ２とは、筐体２２０Ａ内において電気的に接続されている（不図示）。また、半導体パッケージ２２０の実装面積を小さくするために、接続端子Ｔ２は、平面電極パッドを格子状に並べたＬＧＡ（Land Grid Array）となっている。   The housing 220 </ b> A includes a connection terminal T <b> 1 for the image sensor 210 and a connection terminal T <b> 2 for the wiring board 230. The connection terminal T1 and the connection terminal T2 are electrically connected in the housing 220A (not shown). In order to reduce the mounting area of the semiconductor package 220, the connection terminal T2 is an LGA (Land Grid Array) in which planar electrode pads are arranged in a grid pattern.

なお、上述のように、この実施形態では、平面電極パッドを格子状に並べたＬＧＡにより半導体パッケージ２２０と配線基板２３０とを接続している。このため、半導体パッケージ２２０と配線基板２３０との接続の補強には、アンダーフィルではなく、サイドフィルを用いている（サイドフィルについては後述する）。   As described above, in this embodiment, the semiconductor package 220 and the wiring substrate 230 are connected by the LGA in which the planar electrode pads are arranged in a lattice pattern. Therefore, a side fill is used instead of an underfill for reinforcing the connection between the semiconductor package 220 and the wiring board 230 (the side fill will be described later).

筐体２２０Ａ内に収容されたイメージセンサ２１０は、ボンディングワイヤＷにより筐体２２０Ａの接続端子Ｔ１と電気的に接続されている。リッド２２０Ｂは、筐体２２０Ａの開口Ｋ１を塞いで半導体パッケージ２２０を密閉する。   The image sensor 210 accommodated in the housing 220A is electrically connected to the connection terminal T1 of the housing 220A by a bonding wire W. The lid 220B seals the semiconductor package 220 by closing the opening K1 of the housing 220A.

図３は、配線基板２３０の一部拡大断面図である。図３に示すように、配線基板２３０は、絶縁層２３０Ｂ及び配線パターンである導体層２３０Ｃが複数積層された積層体の表面Ｈ及び裏面Ｒに、各々接続端子Ｔ３及び接続端子Ｔ４とを有する。上記積層体の表面Ｈ及び裏面Ｒは、各々接続端子Ｔ３及び接続端子Ｔ４を露出する開口Ｋ２を有するソルダーレジスト層２３０Ｄにより被覆されている。   FIG. 3 is a partially enlarged cross-sectional view of the wiring board 230. As shown in FIG. 3, the wiring board 230 includes a connection terminal T3 and a connection terminal T4 on the front surface H and the back surface R of the multilayer body in which a plurality of insulating layers 230B and conductor layers 230C as wiring patterns are stacked. The front surface H and the back surface R of the laminate are covered with a solder resist layer 230D having an opening K2 exposing the connection terminal T3 and the connection terminal T4, respectively.

接続端子Ｔ３は、半導体パッケージ２２０との接続端子である。また、接続端子Ｔ４は、外部接続端子である。接続端子Ｔ３及び接続端子Ｔ４は、配線パターンである導体層２３０Ｃ及びビア２３０Ｅにより電気的に接続されている。なお、この実施形態では、ビア２３０Ｅは、フィルドビアであるが、コンフォーマルビアとしてもよい。また、フィルドビアとコンフォーマルビアを組み合わせてもよい。   The connection terminal T3 is a connection terminal with the semiconductor package 220. The connection terminal T4 is an external connection terminal. The connection terminal T3 and the connection terminal T4 are electrically connected by a conductor layer 230C and a via 230E that are wiring patterns. In this embodiment, the via 230E is a filled via, but may be a conformal via. Also, filled vias and conformal vias may be combined.

なお、この実施形態では、配線基板２３０の内部を貫通するいわゆる貫通ビアにより接続端子Ｔ３と接続端子Ｔ４とを電気的に接続していない。これは、貫通ビアの直上もしくは直下に接続端子Ｔ３，Ｔ４を形成することができないためである。つまり、上面視にて、貫通ビアと異なる位置に接続端子Ｔ３，Ｔ４を形成する必要があり、接続端子Ｔ３，Ｔ４の配置間隔（ピッチ）を狭くすることができないためである。   In this embodiment, the connection terminal T3 and the connection terminal T4 are not electrically connected by a so-called through via penetrating the inside of the wiring board 230. This is because the connection terminals T3 and T4 cannot be formed immediately above or directly below the through via. That is, it is necessary to form the connection terminals T3 and T4 at positions different from the through vias when viewed from above, and the arrangement interval (pitch) of the connection terminals T3 and T4 cannot be reduced.

また、配線基板２３０は、略中央に厚み方向に貫通する貫通孔２３０Ａを有する。この貫通孔２３０Ａは、ドリル加工により容易に形成することができる。貫通孔２３０Ａを形成する際は、導体層２３０Ｃやビア２３０Ｅを傷つけないように留意が必要である。なお、貫通孔２３０Ａの位置は、上面視にて半導体パッケージ２２０下であれば他の位置でもよい。   In addition, the wiring board 230 has a through hole 230A that penetrates in the thickness direction substantially at the center. This through hole 230A can be easily formed by drilling. When forming the through hole 230A, care must be taken not to damage the conductor layer 230C or the via 230E. The position of the through hole 230A may be another position as long as it is below the semiconductor package 220 in a top view.

配線基板２３０には、半導体パッケージ２２０が実装されている。具体的には、配線基板２３０の接続端子Ｔ３と半導体パッケージ２２０の接続端子Ｔ２とを半田等により接続することで、配線基板２３０に半導体パッケージが実装される。   A semiconductor package 220 is mounted on the wiring board 230. Specifically, the semiconductor package is mounted on the wiring board 230 by connecting the connection terminal T3 of the wiring board 230 and the connection terminal T2 of the semiconductor package 220 with solder or the like.

サイドフィル材２５０は、熱硬化性の樹脂であり、半導体パッケージ２２０の全周囲に塗布される。サイドフィル材２５０は、熱硬化により半導体パッケージ２２０の側面Ｓ及び配線基板２３０の表面Ｆに密着して、半導体パッケージ２２０の全周囲を封止する。サイドフィル材２５０は、熱硬化により半導体パッケージ２２０と配線基板２３０との接続を補強する。   The side fill material 250 is a thermosetting resin and is applied to the entire periphery of the semiconductor package 220. The side fill material 250 is in close contact with the side surface S of the semiconductor package 220 and the surface F of the wiring substrate 230 by thermosetting to seal the entire periphery of the semiconductor package 220. The side fill material 250 reinforces the connection between the semiconductor package 220 and the wiring board 230 by thermosetting.

サイドフィル材２５０により半導体パッケージ２２０と配線基板２３０との接続を補強することで、半導体パッケージ２２０と配線基板２３０との接続部分への応力の集中が緩和され、半導体パッケージ２２０と配線基板２３０との接続信頼性が向上する。   By reinforcing the connection between the semiconductor package 220 and the wiring substrate 230 with the side fill material 250, the concentration of stress on the connection portion between the semiconductor package 220 and the wiring substrate 230 is alleviated. Connection reliability is improved.

なお、半導体パッケージ２２０及び配線基板２３０との間にサイドフィル材２５０で囲まれた空間２６０が形成される。そして、この空間２６０は、配線基板２３０の貫通孔２３０Ａを介して外部空間と連通している。このため、サイドフィル材２５０を熱硬化させる際に、加熱により膨張した空間２６０内の気体は、この貫通孔２３０Ａを介して外部空間に排出される。   A space 260 surrounded by the side fill material 250 is formed between the semiconductor package 220 and the wiring board 230. The space 260 communicates with the external space through the through hole 230 </ b> A of the wiring board 230. For this reason, when the side fill material 250 is heat-cured, the gas in the space 260 expanded by heating is discharged to the external space through the through hole 230A.

一方、図４に示すように、配線基板２３０に貫通孔２３０Ａがない場合、空間２６０は、密閉空間となる。このため、サイドフィル材２５０を熱硬化させる際に、加熱により膨張した空間２６０内の気体の逃げ場がない。その結果、空間２６０の圧力が高くなり、最終的にサイドフィル材２５０を突き破ってサイドフィル材２５０に孔２５０ａが発生する。   On the other hand, as shown in FIG. 4, when the wiring board 230 does not have the through hole 230 </ b> A, the space 260 becomes a sealed space. For this reason, when the side fill material 250 is thermally cured, there is no escape space for the gas in the space 260 expanded by heating. As a result, the pressure in the space 260 is increased, and finally the side fill material 250 is broken through to generate holes 250a in the side fill material 250.

そして、孔２５０ａが発生する際に、サイドフィル材２５０にボイド２５０ｂ（貫通孔を含む）が発生する。近年では、カメラヘッド２００を挿入するために検体に与える傷（開口）を最小限とするため、カメラヘッド２００の小型化がすすめられている。このため、カメラヘッド２００の筐体２４０も半導体パッケージ２２０及び配線基板２３０をぎりぎり収容できる程度の大きさとなっている。このためサイドフィル材２５０にボイド２５０ｂが発生すると、配線基板２３０を筐体２４０内に収容できない虞がある。また、このボイド２５０ｂの発生した配線基板２２０を収容できるよう筐体２４０を大きくしてしまうと、カメラヘッド２００の小型化が妨げられるという問題が発生する。   When the holes 250a are generated, voids 250b (including through holes) are generated in the side fill material 250. In recent years, the miniaturization of the camera head 200 has been promoted in order to minimize scratches (openings) on the specimen in order to insert the camera head 200. For this reason, the housing 240 of the camera head 200 is also large enough to accommodate the semiconductor package 220 and the wiring board 230. For this reason, when the void 250 b is generated in the side fill material 250, the wiring substrate 230 may not be accommodated in the housing 240. Further, if the housing 240 is enlarged to accommodate the wiring board 220 in which the voids 250b are generated, there arises a problem that miniaturization of the camera head 200 is hindered.

なお、発生したボイド２５０ｂを削り取ることも考えられるが、ボイド２５０ｂを削る際に発生するパーティクルが半導体パッケージ２２０に付着する虞がある。特に、パーティクルが半導体パッケージ２２０のリッド２２０Ｂに付着するとイメージセンサ２１０による撮像に悪影響を与えてしまう。また、リッド２２０Ｂに傷をつける虞があるため、パーティクルの除去は困難である。さらに、サイドフィル材２５０に孔が発生すると、半導体パッケージ２２０と配線基板２３０との接続を補強する力が弱くなるため、半導体パッケージ２２０と配線基板２３０との接続信頼性が低下してしまう。   Although it is conceivable to scrape off the generated void 250b, there is a possibility that particles generated when scraping the void 250b adhere to the semiconductor package 220. In particular, if particles adhere to the lid 220 </ b> B of the semiconductor package 220, the imaging by the image sensor 210 is adversely affected. Further, it is difficult to remove the particles because the lid 220B may be damaged. Furthermore, if a hole is generated in the side fill material 250, the force that reinforces the connection between the semiconductor package 220 and the wiring board 230 is weakened, so that the connection reliability between the semiconductor package 220 and the wiring board 230 is reduced.

以上のように、実施形態に係る半導体パッケージの実装構造では、イメージセンサ２１０が収容された半導体パッケージ２２０と、半導体パッケージ２２０と接続され、厚み方向に貫通する少なくとも１の貫通孔２３０Ａを有する配線基板２３０と、半導体パッケージ２２０の側面Ｓ及び配線基板２３０の表面Ｆに密着して半導体パッケージ２２０の全周囲を封止するサイドフィル材２５０とを具備している。   As described above, in the semiconductor package mounting structure according to the embodiment, the semiconductor package 220 in which the image sensor 210 is accommodated, and the wiring board that is connected to the semiconductor package 220 and has at least one through hole 230A that penetrates in the thickness direction. 230, and a side fill material 250 that seals the entire periphery of the semiconductor package 220 in close contact with the side surface S of the semiconductor package 220 and the surface F of the wiring substrate 230.

このため、半導体パッケージ２２０、配線基板２３０及びサイドフィル材２５０により形成される空間２６０が配線基板２３０の貫通孔２３０Ａを介して外部空間と連通する。この結果、サイドフィル材２５０を熱硬化させる際に、加熱により膨張した空間２６０内の気体が貫通孔２３０Ａを介して外部空間に排出され、サイドフィル材２５０にボイドが発生することを防止することができる。   For this reason, the space 260 formed by the semiconductor package 220, the wiring board 230, and the side fill material 250 communicates with the external space through the through hole 230 </ b> A of the wiring board 230. As a result, when the side fill material 250 is thermoset, the gas in the space 260 expanded by heating is discharged to the external space through the through-hole 230A, thereby preventing the side fill material 250 from generating voids. Can do.

なお、通常、貫通孔２３０Ａは一つあれば十分であるが、貫通孔２３０Ａの数は任意である。このため、貫通孔２３０Ａは２以上であってもよい。また、貫通孔２３０Ａの直径φは、好ましくは、０．８ｍｍ程度であるが、空間Ｓ内の気体が貫通孔２３０Ａを介して外部空間に十分に排出される範囲であれば、貫通孔２３０Ａの直径φを小さくすることも可能である。発明者による実験では、貫通孔２３０Ａの直径φが０．１７ｍｍの場合でも、空間Ｓ内の気体が貫通孔２３０Ａを介して外部空間に十分に排出された。なお、この実験は、貫通孔２３０Ａの直径φの下限を０．１７ｍｍに限定するものではない。   Normally, one through hole 230A is sufficient, but the number of through holes 230A is arbitrary. For this reason, the number of through holes 230A may be two or more. Further, the diameter φ of the through hole 230A is preferably about 0.8 mm, but if the gas in the space S is sufficiently discharged to the external space through the through hole 230A, the diameter of the through hole 230A is It is also possible to reduce the diameter φ. In the experiment by the inventor, even when the diameter φ of the through hole 230A is 0.17 mm, the gas in the space S is sufficiently discharged to the external space through the through hole 230A. In this experiment, the lower limit of the diameter φ of the through hole 230A is not limited to 0.17 mm.

（その他の実施形態）
以上のように、本発明のいくつかの実施形態について説明したが、上記実施形態は、例として提示したものであり、発明の範囲を限定することを意図するものではない。上記実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を変更しない範囲で、種々の省略、置き換え、変更を行うことができる。(Other embodiments)
As mentioned above, although several embodiment of this invention was described, the said embodiment is shown as an example and is not intending limiting the range of invention. The above embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention.

１００…撮像装置、２００…ヘッド部、２００…カメラヘッド、２１０…イメージセンサ、２２０…半導体パッケージ、２２０Ａ…筐体、２２０Ｂ…リッド、２３０…配線基板、２３０Ａ…貫通孔、２３０Ｂ…絶縁層、２３０Ｃ…導体層、２３０Ｄ…ソルダーレジスト層、２３０Ｅ…ビア、２４０…筐体、２５０…サイドフィル材、２５０ａ…孔、２５０ｂ…ボイド、２６０…空間、３００…本体部、３０１…ＩＦ回路、３０２…メモリ、３０３…プロセッサ、３０４…ドライバ、３０５…コントローラ、３０６…電源回路、４００…カメラケーブル、５００…表示装置。   DESCRIPTION OF SYMBOLS 100 ... Imaging device, 200 ... Head part, 200 ... Camera head, 210 ... Image sensor, 220 ... Semiconductor package, 220A ... Housing, 220B ... Lid, 230 ... Wiring board, 230A ... Through-hole, 230B ... Insulating layer, 230C ... Conductor layer, 230D ... Solder resist layer, 230E ... Via, 240 ... Housing, 250 ... Side fill material, 250a ... Hole, 250b ... Void, 260 ... Space, 300 ... Main part, 301 ... IF circuit, 302 ... Memory , 303: processor, 304 ... driver, 305 ... controller, 306 ... power supply circuit, 400 ... camera cable, 500 ... display device.

Claims (5)

半導体装置が収容された半導体パッケージと、
前記半導体パッケージと接続され、厚み方向に貫通する少なくとも１の貫通孔を有する配線基板と、
前記半導体パッケージの側面及び前記配線基板の表面に密着して前記半導体パッケージの全周囲を封止するサイドフィル材と、
を具備する半導体パッケージの実装構造。A semiconductor package containing a semiconductor device; and
A wiring board connected to the semiconductor package and having at least one through hole penetrating in the thickness direction;
A side fill material that seals the entire periphery of the semiconductor package in close contact with the side surface of the semiconductor package and the surface of the wiring board;
A semiconductor package mounting structure comprising: 前記半導体装置は、固体撮像素子である請求項１に記載の半導体パッケージの実装構造。   The semiconductor package mounting structure according to claim 1, wherein the semiconductor device is a solid-state imaging device. 前記配線基板は、
表面に形成された前記半導体パッケージとの第１の接続端子と、
裏面に形成された外部接続用の第２の接続端子と、
を有し、
前記第１，第２の接続端子が貫通ビア以外のビアで接続されている請求項１に記載の半導体パッケージの実装構造。The wiring board is
A first connection terminal with the semiconductor package formed on the surface;
A second connection terminal for external connection formed on the back surface;
Have
The semiconductor package mounting structure according to claim 1, wherein the first and second connection terminals are connected by vias other than through vias. 前記ビアは、フィルドビア及び／又はコンフォーマルビアである請求項３に記載の半導体パッケージの実装構造。   The semiconductor package mounting structure according to claim 3, wherein the via is a filled via and / or a conformal via. 半導体装置が収容された半導体パッケージと、前記半導体パッケージと接続され、厚み方向に貫通する少なくとも１の貫通孔を有する配線基板と、前記半導体パッケージの側面及び前記配線基板の表面に密着して前記半導体パッケージの全周囲を封止するサイドフィル材と、を具備する半導体パッケージの実装構造を備えた内視鏡装置のカメラヘッド。   A semiconductor package containing a semiconductor device, a wiring board connected to the semiconductor package and having at least one through-hole penetrating in a thickness direction, the semiconductor package being in close contact with a side surface of the semiconductor package and the surface of the wiring board A camera head of an endoscope apparatus comprising a semiconductor package mounting structure including a side fill material that seals the entire periphery of the package.
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