JP3374812B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3374812B2 JP3374812B2 JP31942799A JP31942799A JP3374812B2 JP 3374812 B2 JP3374812 B2 JP 3374812B2 JP 31942799 A JP31942799 A JP 31942799A JP 31942799 A JP31942799 A JP 31942799A JP 3374812 B2 JP3374812 B2 JP 3374812B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- semiconductor chip
- reinforcing
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、面実装型の半導体
装置に関し、特に、本発明は、中間基板に有機基板を用
いたフリップチップ実装を有する面実装型の半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mounting type semiconductor device, and more particularly, the present invention relates to a surface mounting type semiconductor device having flip chip mounting using an organic substrate as an intermediate substrate.
【０００２】[0002]
【従来の技術】従来、半導体装置は一般に、放熱板、補
強板等を設けて構成される。例えば、従来例１としての
特開平１１−４０６８７号公報の「半導体装置」を、図
４および図５に示す。図４は縦断面図、図５は横断面図
である。この従来の半導体装置は、半導体チップ２１、
バンプ２２、樹脂基板２３、樹脂基板上面２４、パッド
２５、はんだボール２７、封止樹脂２８、補強板２９、
接着剤３０、３３、補強部材３１、およびカバー板３２
を有して構成される。本構成の半導体装置は、反り防止
のためにフリップチップ型のＢＧＡ（Ball Grid Array)
パッケージの半導体チップ２１を避けた四隅の部分に補
強板２９を接着し、さらにその上にカバー板３２を接着
した構造となっている。必要に応じて、カバー板３２の
上面に不図示の放熱フィンを取り付けることができる。2. Description of the Related Art Conventionally, a semiconductor device is generally constructed by providing a heat radiating plate, a reinforcing plate and the like. For example, FIG. 4 and FIG. 5 show a “semiconductor device” of Japanese Patent Laid-Open No. 11-40687 as Conventional Example 1. 4 is a vertical sectional view, and FIG. 5 is a horizontal sectional view. This conventional semiconductor device includes a semiconductor chip 21,
Bump 22, resin substrate 23, resin substrate upper surface 24, pad 25, solder ball 27, sealing resin 28, reinforcing plate 29,
Adhesives 30, 33, reinforcing member 31, and cover plate 32
Is configured. The semiconductor device of this configuration is a flip chip type BGA (Ball Grid Array) for preventing warpage.
A reinforcing plate 29 is adhered to the four corners of the package that are away from the semiconductor chip 21, and a cover plate 32 is further adhered on the reinforcing plate 29. If necessary, a radiating fin (not shown) can be attached to the upper surface of the cover plate 32.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来例の構造の半導体装置は、樹脂基板２３の半導体チッ
プ２１を避けた部分を使用して補強板２９を取り付ける
ため、取り付けのためのエリアが必要であり、半導体装
置の外形サイズを極力小さくしようとするには適してい
ない。However, in the semiconductor device having the structure of the conventional example described above, since the reinforcing plate 29 is attached using the portion of the resin substrate 23 that avoids the semiconductor chip 21, an area for attachment is required. Therefore, it is not suitable for minimizing the outer size of the semiconductor device.
【０００４】また、補強板２９、カバー板３２はＳＵＳ
３０４や銅を使用しており、重量も大きく、小型軽量化
を狙う製品への適用には適していない。その熱膨張係数
は、ＳＵＳ３０４：１８．９ｐｐｍ、銅：１６．５ｐｐ
ｍといずれも通常のガラスエポキシ基板の１２〜１４ｐ
ｐｍよりも大きく、リフロー時やその後に温度変化にさ
らされた場合、熱膨張係数の大きさが違うことによるス
トレスが半導体装置に加わり、ＰＫＧ（パッケージ）自
身の信頼性を低下させる可能性がある。The reinforcing plate 29 and the cover plate 32 are made of SUS.
Since 304 and copper are used, they are heavy and not suitable for application to products that aim to be small and lightweight. The coefficient of thermal expansion is SUS304: 18.9 ppm, copper: 16.5 pp
m and all are 12-14p of a normal glass epoxy substrate
If it is larger than pm and is exposed to temperature change during or after reflow, stress due to different magnitude of thermal expansion coefficient may be applied to the semiconductor device and the reliability of the PKG (package) itself may be reduced. .
【０００５】さらに熱膨張係数が異なることにより、温
度変化により半導体装置に反りが生じ、その反りの生じ
る部分にはんだボール接続部が有る場合は、応力が加わ
り、はんだでの破断を引き起こし易く、接続信頼性を低
下させる場合があるという問題を伴う。Further, due to the difference in the thermal expansion coefficient, the semiconductor device is warped due to the temperature change, and when there is a solder ball connecting portion at the portion where the warping occurs, stress is applied to the semiconductor device, which easily causes breakage in the solder. There is a problem that reliability may be reduced.
【０００６】本発明は、基板スペース利用効率を高め、
接続信頼性を高めた半導体装置を提供することを目的と
する。The present invention enhances the board space utilization efficiency,
An object is to provide a semiconductor device with improved connection reliability.
【０００７】[0007]
【課題を解決するための手段】かかる目的を達成するた
め、請求項１記載の発明によれば、半導体装置は、中間
基板に有機基板を用いたフリップチップ実装を有する面
実装型の半導体装置において、回路面を中間基板側に向
けて実装されている半導体チップと、半導体チップの裏
面側すなわち中間基板の反対側に設けられた補強基板
と、中間基板の半導体チップを実装している面の反対面
に形成されたＢＧＡ接続用のはんだボールとを有して構
成され、補強基板の厚みおよび材質を中間基板と同じと
したことを特徴とするものである。 In order to achieve the above object , according to the invention of claim 1, the semiconductor device is a surface mount type semiconductor device having flip chip mounting using an organic substrate as an intermediate substrate . , The semiconductor chip mounted with the circuit surface facing the intermediate substrate side, the reinforcing substrate provided on the back surface side of the semiconductor chip, that is, on the opposite side of the intermediate substrate, and the opposite side of the surface of the intermediate substrate mounting the semiconductor chip. And a solder ball for BGA connection formed on the surface, and the thickness and material of the reinforcing substrate are the same as those of the intermediate substrate.
It is characterized by having done .
【０００８】請求項２記載の発明によれば、半導体装置
は、補強基板には、半導体チップを収容するように半導
体チップを覆い包む凹部（キャビティ）が設けられ、こ
の凹部は、半導体チップと同じ厚みでかつ同じ大きさで
あり、補強基板の厚みを、当該補強基板における凹部底
面の肉薄部の肉厚とし、補強基板の凹部周辺の最も厚い
部分が、半導体チップの厚みと中間基板の厚みとを合わ
せた厚みとなっている請求項１に記載の半導体装置であ
ることを特徴とするものである。According to the second aspect of the invention, the semiconductor device is such that the semiconductor substrate is mounted on the reinforcing substrate so as to accommodate the semiconductor chip.
There is a recess (cavity) that covers the body chip.
The concave part of the same thickness and size as the semiconductor chip
Yes, the thickness of the reinforcing substrate is defined as the bottom of the recess in the reinforcing substrate.
The thinnest part of the surface is the thickest, and the thickest part around the concave part of the reinforcing substrate
The part matches the thickness of the semiconductor chip and the thickness of the intermediate substrate.
The semiconductor device according to claim 1, which has a reduced thickness .
【０００９】請求項３記載の発明よれば、半導体装置
は、補強基板の両表層にはベタ銅パターンを設け、この
補強基板の半導体チップの上部に当たる部分にさらに所
定の大きさの放熱用スルーホールを設け、放熱性を高め
た請求項１または２に記載の半導体装置であることを特
徴とするものである。 According to the invention described in claim 3, a semiconductor device
Is provided with a solid copper pattern in both surface layers of the reinforcing substrate, further providing a predetermined size for heat dissipation through-hole of the portion corresponding to the upper portion of the semiconductor chip of the reinforcing substrate, improved heat dissipation property
It is the semiconductor device according to claim 1 or 2 characterized by
It is a characteristic.
【００１０】請求項４記載の発明よれば、半導体装置
は、補強基板は、半導体チップおよび中間基板へ所定の
接着剤により強固に接着されている請求項１から３の何
れか１項に記載の半導体装置であることを特徴とするも
のである。 According to the invention described in claim 4, a semiconductor device
, The reinforcing substrate, what of claims 1 to 3 which are firmly bonded by predetermined adhesive to the semiconductor chip and the intermediate substrate
The semiconductor device according to item 1 is also characterized in that
Of.
【００１１】請求項５記載の発明よれば、半導体装置
は、中間基板の熱膨張係数（α１）と補強基板の熱膨張
係数（α２）を、α１＞α２、の関係とした請求項１か
ら４の何れか１項に記載の半導体装置であることを特徴
とするものである。 According to the invention of claim 5, a semiconductor device
Is the thermal expansion coefficient between the reinforcing substrate thermal expansion coefficient of the intermediate substrate (α1) (α2), α1 > α2, related to the claims 1 to
The semiconductor device according to any one of 4 to 4 is characterized in that
It is what
【００１２】[0012]
【発明の実施の形態】次に、添付図面を参照して本発明
による半導体装置の実施の形態を詳細に説明する。図１
から図３を参照すると、本発明の半導体装置の一実施形
態が示されている。BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Figure 1
3 to FIG. 3, there is shown one embodiment of the semiconductor device of the present invention.
【００１３】（第１の実施例）
図１に本発明の半導体装置の第１の実施例の断面図を示
す。本実施例の半導体装置１は、半導体チップ２、中間
基板３、補強基板４、接着材５、はんだボール６、マザ
ーボード７、放熱用スルーホール８、を有して構成され
る。(First Embodiment) FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention. The semiconductor device 1 of this embodiment is configured to include a semiconductor chip 2, an intermediate substrate 3, a reinforcing substrate 4, an adhesive material 5, a solder ball 6, a mother board 7, and a heat dissipation through hole 8.
【００１４】半導体装置１はフリップチップ実装構造を
とっており、半導体チップ２は回路面を中間基板３側に
向けて実装されている。半導体チップ２の裏面側すなわ
ち中間基板３の反対側に補強基板４が設けられている。
補強基板４の厚み、材質は中間基板と同じであり、半導
体チップ２および中間基板３へ接着剤５により強固に接
着されている。中間基板３の半導体チップ２を実装して
いる面の反対面にはＢＧＡ（Ball Grid Array)接続用の
はんだボール６が形成され、このはんだボール６により
マザーボード７に実装されている。The semiconductor device 1 has a flip-chip mounting structure, and the semiconductor chip 2 is mounted with the circuit surface facing the intermediate substrate 3 side. A reinforcing substrate 4 is provided on the back surface side of the semiconductor chip 2, that is, on the opposite side of the intermediate substrate 3.
The thickness and material of the reinforcing substrate 4 are the same as those of the intermediate substrate, and they are firmly adhered to the semiconductor chip 2 and the intermediate substrate 3 with the adhesive 5. Solder balls 6 for BGA (Ball Grid Array) connection are formed on the surface of the intermediate substrate 3 opposite to the surface on which the semiconductor chip 2 is mounted, and the solder balls 6 are mounted on the mother board 7.
【００１５】（動作の説明）
図１に示す本発明の半導体装置の第１の実施例につい
て、図面を基に詳細に説明する。上記に構成される半導
体装置１は、フリップチップ実装構造をとっており、半
導体チップ２の回路面を中間基板３側に向けて実装され
ている。中間基板３はガラスエポキシ基板であり、半導
体チップ２のピン数とピンピッチによっては微細配線の
可能なビルドアップ構造の基板を使用することができ
る。(Description of Operation) A first embodiment of the semiconductor device of the present invention shown in FIG. 1 will be described in detail with reference to the drawings. The semiconductor device 1 configured as described above has a flip chip mounting structure, and is mounted with the circuit surface of the semiconductor chip 2 facing the intermediate substrate 3 side. The intermediate substrate 3 is a glass epoxy substrate, and depending on the number of pins and the pin pitch of the semiconductor chip 2, a substrate having a buildup structure capable of fine wiring can be used.
【００１６】半導体チップ２の裏面側、すなわち中間基
板３の反対側に補強基板４が設けられている。補強基板
４の材質は、中間基板３と同じガラスエポキシ基板を用
いており、図１の場合は、板厚、外形サイズも中間基板
３と同じである。この補強基板４は、半導体チップ２お
よび中間基板３に接着剤５により強固に接着されてい
る。半導体チップ１の厚み分、補強基板４と中間基板３
に間隙が生ずるが、その間隙へも接着剤５を充填する。
本実施例での接着剤５は、熱硬化型のエポキシ樹脂を用
いている。A reinforcing substrate 4 is provided on the back surface side of the semiconductor chip 2, that is, on the opposite side of the intermediate substrate 3. As the material of the reinforcing substrate 4, the same glass epoxy substrate as that of the intermediate substrate 3 is used, and in the case of FIG. 1, the plate thickness and the outer size are also the same as those of the intermediate substrate 3. The reinforcing substrate 4 is firmly adhered to the semiconductor chip 2 and the intermediate substrate 3 with the adhesive 5. The thickness of the semiconductor chip 1, the reinforcing substrate 4 and the intermediate substrate 3
Although there is a gap in the gap, the adhesive 5 is also filled in the gap.
The adhesive 5 in this embodiment is a thermosetting epoxy resin.
【００１７】中間基板３の半導体チップ２を実装してい
る面の反対面にＢＧＡ接続用のはんだボール６が形成さ
れ、このはんだボール６により、電気的、機械的にマザ
ーボード７に実装されている。本実施例でのはんだボー
ル６は、Ｓｎ６３／Ｐｂ３７の共晶はんだを用いてい
る。Solder balls 6 for BGA connection are formed on the surface of the intermediate substrate 3 opposite to the surface on which the semiconductor chip 2 is mounted, and are electrically and mechanically mounted on the mother board 7 by the solder balls 6. . The solder balls 6 in this embodiment are made of Sn63 / Pb37 eutectic solder.
【００１８】本実施例の第１の効果として、半導体装置
をマザーボードに実装した際のＢＧＡはんだボールの接
続信頼性が良いことがあげられる。これは、半導体チッ
プに対して、同材質の中間基板と補強基板が対称的に配
置されている構造であるため、熱ストレスが加わった時
に半導体装置自身の反りの発生を抑えることができるか
らである。その結果、マザーボードに実装した時に、は
んだボールの接続部に加わるストレスを抑えることがで
きる。The first effect of this embodiment is that the connection reliability of the BGA solder balls when the semiconductor device is mounted on the motherboard is good. This is because the intermediate substrate and the reinforcing substrate of the same material are symmetrically arranged with respect to the semiconductor chip, so that it is possible to suppress warpage of the semiconductor device itself when thermal stress is applied. is there. As a result, it is possible to suppress the stress applied to the connection portion of the solder ball when it is mounted on the motherboard.
【００１９】本実施例の第２の効果として、軽量、小型
な半導体装置を得ることができる。これは、比重の大き
い金属製の補強基板を使用せず、比重の小さい樹脂性の
基板を使用しているためである。また、補強基板を半導
体チップも含めた部分に接着することができ、半導体装
置としての外形サイズを極力小さくすることができる。As a second effect of this embodiment, a lightweight and compact semiconductor device can be obtained. This is because a metal-made reinforcing substrate having a large specific gravity is not used, but a resin substrate having a small specific gravity is used. Further, the reinforcing substrate can be bonded to the portion including the semiconductor chip, and the outer size of the semiconductor device can be minimized.
【００２０】（第２の実施例）
本発明の第２の実施例を図２に示す。本図２においては
補強基板４には、半導体チップ２と同じ厚み、同じ大き
さの凹部（キャビティ）が設けてあり、接着する際に半
導体チップ２を覆い包む構造となっている。補強基板４
の最も厚い部分の厚みは、半導体チップ２と中間基板３
の厚みを合わせた厚みとなっている。(Second Embodiment) FIG. 2 shows a second embodiment of the present invention. In FIG. 2, the reinforcing substrate 4 is provided with a recess (cavity) having the same thickness and the same size as the semiconductor chip 2, and has a structure that covers the semiconductor chip 2 when bonding. Reinforcing board 4
The thickness of the thickest part of the semiconductor chip 2 and the intermediate substrate 3 is
It is the combined thickness of.
【００２１】本構造とすることにより、第１の実施例の
場合よりも接着材の部分が小さくなり、より温度ストレ
スが加わった場合のＰＫＧ自身の信頼性を向上させるこ
とができる。With this structure, the portion of the adhesive material becomes smaller than in the case of the first embodiment, and the reliability of the PKG itself when temperature stress is applied can be improved.
【００２２】（第３の実施例）
本発明の第３の実施例を図３に示す。本図３において
は、補強基板４の半導体チップ２の上部に当たる部分に
放熱用スルーホール８が設けられている。放熱用スルー
ホール８を補強基板４の両表層に設けたベタ銅パターン
に接続することにより、さらに放熱性を高めることがで
きる。本構造においては、半導体チップ２の周囲を密封
する構造でありながら熱設計も考慮しているため、消費
電力の大きい半導体チップにも適用可能である。(Third Embodiment) FIG. 3 shows a third embodiment of the present invention. In FIG. 3, a heat dissipation through-hole 8 is provided in a portion of the reinforcing substrate 4 which corresponds to the upper portion of the semiconductor chip 2. By connecting the through holes 8 for heat dissipation to the solid copper patterns provided on both surface layers of the reinforcing substrate 4, the heat dissipation can be further improved. In this structure, although the structure around the semiconductor chip 2 is hermetically sealed, thermal design is also taken into consideration, so that the present invention can be applied to a semiconductor chip with high power consumption.
【００２３】これは図２の構造においても、放熱用スル
ーホール８を設けることにより、本第３の実施例と同様
の効果を得ることができる。Even in the structure of FIG. 2, the same effect as that of the third embodiment can be obtained by providing the heat dissipation through hole 8.
【００２４】（第４の実施例）
第１から第３の実施例では、中間基板３と補強基板４は
同じ材質の同じサイズのものを使用しているが、第４の
実施例として半導体チップ２、中間基板３、補強基板４
さらにはマザーボード７のそれぞれの熱膨張係数を考慮
してＢＧＡの接続信頼性を向上させることもできる。(Fourth Embodiment) In the first to third embodiments, the intermediate substrate 3 and the reinforcing substrate 4 are made of the same material and have the same size, but as a fourth embodiment, a semiconductor chip is used. 2, intermediate substrate 3, reinforcing substrate 4
Furthermore, the connection reliability of the BGA can be improved in consideration of the respective thermal expansion coefficients of the motherboard 7.
【００２５】中間基板３と補強基板４はいずれも半導体
装置の外形サイズと同サイズであり、使用する基板面積
はそれほど大きくない。しかしマザーボード７は、通常
使用する基板面積は大きいため、安価な基板を使用する
ことが望ましい。安価な基板としては、熱膨張係数の大
きいガラスエポキシ基板が代表的であるが、その熱膨張
係数は大きい場合で１４ｐｐｍまで大きくなる。Both the intermediate substrate 3 and the reinforcing substrate 4 have the same external size as the semiconductor device, and the substrate area used is not so large. However, since the mother board 7 usually has a large board area, it is desirable to use an inexpensive board. A glass epoxy substrate having a large coefficient of thermal expansion is typical as an inexpensive substrate, but when the coefficient of thermal expansion is large, it increases to 14 ppm.
【００２６】一方、フリップチップ実装する相手の中間
基板３には、半導体チップ２の熱膨張係数（３ｐｐｍ）
に近づけるために、低膨張の有機基板を使用する場合が
ある（１０〜７ｐｐｍ程度）。その場合は、中間基板３
の熱膨張係数（α１）と補強基板４の熱膨張係数（α
２）を、α１＞α２、とすることにより、ＢＧＡの接続
信頼性を向上させることができる。On the other hand, the thermal expansion coefficient (3 ppm) of the semiconductor chip 2 is provided on the intermediate substrate 3 of the other party for flip-chip mounting.
There is a case where an organic substrate having a low expansion is used (about 10 to 7 ppm) in order to approach the above condition. In that case, the intermediate substrate 3
Coefficient of thermal expansion (α1) of the reinforcing substrate 4 (α1)
By setting 2) to α1> α2, the connection reliability of the BGA can be improved.
【００２７】これは、このような熱膨張係数にすること
により、半導体装置１単体では、加熱時には中央部が下
に凸に、冷却時には上に凸に変形する。よって、半導体
装置１を熱膨張係数の大きいマザーボード７に実装した
場合の、加熱冷却時の変形に追従する。ただし、半導体
装置１単体の加熱時の変形量は、補強基板４を取り付け
ていない構造の時よりも変形量を小さくコントロールす
る必要がある。With such a coefficient of thermal expansion, the central portion of the semiconductor device 1 is deformed to be convex downward when heated and convex upward when cooled. Therefore, when the semiconductor device 1 is mounted on the motherboard 7 having a large coefficient of thermal expansion, the deformation during heating and cooling is followed. However, it is necessary to control the deformation amount of the semiconductor device 1 when it is heated to be smaller than that of the structure in which the reinforcing substrate 4 is not attached.
【００２８】また、同様な効果として、中間基板３と補
強基板４の材質を同じとした場合は、中間基板３の板厚
（ｔ１）と補強基板４の板厚を、ｔ１＞ｔ２、として中
間基板２の熱変形をやや優位とさせてもよい。Further, as a similar effect, when the intermediate substrate 3 and the reinforcing substrate 4 are made of the same material, the plate thickness (t1) of the intermediate substrate 3 and the plate thickness of the reinforcing substrate 4 are set to t1> t2, and the intermediate value is obtained. The thermal deformation of the substrate 2 may be slightly superior.
【００２９】さらに、板厚を同じとした場合で、中間基
板３の剛性（Ｅ１）を補強基板４の剛性（Ｅ２）を、Ｅ
１＞Ｅ２、としてもよい。このことは、これらを組み合
わせた場合や、基板の表層、内層の銅配線層のパターン
の設計によっても同様な効果を得ることができるのは明
らかである。Further, when the plate thickness is the same, the rigidity (E1) of the intermediate substrate 3 is equal to the rigidity (E2) of the reinforcing substrate 4 is equal to E
1> E2. It is clear that the same effect can be obtained by combining these or by designing the patterns of the surface copper layer and the inner copper wiring layer of the substrate.
【００３０】尚、上述の実施形態は本発明の好適な実施
の一例である。但し、これに限定されるものではなく、
本発明の要旨を逸脱しない範囲内において種々変形実施
が可能である。The above-mentioned embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this,
Various modifications can be made without departing from the scope of the present invention.
【００３１】[0031]
【発明の効果】以上の説明より明らかなように、本発明
の半導体装置は、半導体チップが回路面を中間基板側に
向けて実装され、補強基板が半導体チップの裏面側すな
わち中間基板の反対側に設けられ、ＢＧＡ接続用のはん
だボールが中間基板の半導体チップを実装している面の
反対面に形成されている。この構成により、マザーボー
ドへ実装時の熱ストレスが加わった時に半導体装置自身
の反りの発生を抑えることができ、また、はんだボール
の接続部に加わるストレスも抑えることができ、ＢＧＡ
はんだボールの接続信頼性が向上する。As is apparent from the above description, in the semiconductor device of the present invention, the semiconductor chip is mounted with the circuit surface facing the intermediate substrate side, and the reinforcing substrate is the back surface side of the semiconductor chip, that is, the opposite side of the intermediate substrate. And solder balls for BGA connection are formed on the surface of the intermediate substrate opposite to the surface on which the semiconductor chip is mounted. With this configuration, it is possible to suppress the occurrence of warpage of the semiconductor device itself when heat stress is applied to the motherboard during mounting, and it is also possible to suppress the stress applied to the solder ball connection portion.
The solder ball connection reliability is improved.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の半導体装置の実施形態を示す第１の実
施例の断面図である。FIG. 1 is a sectional view of a first example showing an embodiment of a semiconductor device of the present invention.
【図２】第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment.
【図３】第３の実施例の断面図である。FIG. 3 is a sectional view of a third embodiment.
【図４】従来例の縦断面図である。FIG. 4 is a vertical sectional view of a conventional example.
【図５】従来例の横断面図である。FIG. 5 is a cross-sectional view of a conventional example.
１ 半導体装置 ２ 半導体チップ ３ 中間基板 ４ 補強基板 ５ 接着材 ６ はんだボール ７ マザーボード ８ 放熱用スルーホール ２１ 半導体チップ ２２ バンプ ２３ 樹脂基板 ２４ 樹脂基板上面 ２５ パッド ２７ はんだボール ２８ 封止樹脂 ２９ 補強板 ３０、３３ 接着剤 ３１ 補強部材 ３２ カバー板 1 Semiconductor device 2 semiconductor chips 3 Intermediate board 4 Reinforcing board 5 adhesive 6 solder balls 7 Motherboard 8 Through holes for heat dissipation 21 semiconductor chips 22 bump 23 Resin substrate 24 Resin substrate top surface 25 pads 27 Solder balls 28 Sealing resin 29 Reinforcement plate 30, 33 adhesive 31 Reinforcement member 32 cover plate
Claims (5)
ップ実装を有する面実装型の半導体装置において、 回路面を前記中間基板側に向けて実装されている半導体
チップと、 前記半導体チップの裏面側すなわち中間基板の反対側に
設けられた補強基板と、 前記中間基板の半導体チップを実装している面の反対面
に形成されたＢＧＡ接続用のはんだボールと、 を有して構成され、 前記補強基板の厚みおよび材質を前記中間基板と同じと
したことを特徴とする半導体装置。1. A surface-mount type semiconductor device having flip-chip mounting using an organic substrate as an intermediate substrate, comprising: a semiconductor chip mounted with a circuit surface facing the intermediate substrate; and a back surface side of the semiconductor chip. That is, the reinforcing board is provided on the opposite side of the intermediate board, and the solder ball for BGA connection is formed on the surface of the intermediate board opposite to the surface on which the semiconductor chip is mounted. A semiconductor device in which the thickness and material of the substrate are the same as those of the intermediate substrate.
容するように前記半導体チップを覆い包む凹部（キャビ
ティ）が設けられ、 前記凹部は、前記半導体チップと同じ厚みでかつ同じ大
きさであり、 前記補強基板の厚みを、当該補強基板における前記凹部
底面の肉薄部の肉厚とし、 前記補強基板の凹部周辺の最も厚い部分が、前記半導体
チップの厚みと前記中間基板の厚みとを合わせた厚みと
なっている ことを特徴とする請求項１に記載の半導体装
置。2. The reinforcing substrate accommodates the semiconductor chip.
To cover the semiconductor chip so that
Is provided, and the recess has the same thickness and the same size as the semiconductor chip.
Is of can, the thickness of the reinforcing substrate, the recess in the reinforcing substrate
The thickness of the thin portion on the bottom is the thickness, and the thickest portion around the recess of the reinforcing substrate is the semiconductor.
The total thickness of the thickness of the chip and the thickness of the intermediate substrate, and
The semiconductor device according to claim 1, characterized in that it it.
ンを設け、 該補強基板の前記半導体チップの上部に当たる部分にさ
らに所定の大きさの放熱用スルーホールを設け、 放熱性を高めたことを特徴とする請求項１または２に記
載の半導体装置。3. A solid copper pattern is provided on both surface layers of the reinforcing substrate, and a through hole for heat radiation of a predetermined size is further provided at a portion of the reinforcing substrate corresponding to an upper portion of the semiconductor chip to enhance heat radiation. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
び中間基板へ所定の接着剤により強固に接着されている
ことを特徴とする請求項１から３の何れかに記載の半導
体装置。4. The semiconductor device according to claim 1, wherein the reinforcing substrate is firmly attached to the semiconductor chip and the intermediate substrate with a predetermined adhesive.
記補強基板の熱膨張係数（α２）を、α１＞α２、の関
係としたことを特徴とする請求項１から４の何れかに記
載の半導体装置。5. The thermal expansion coefficient (α1) of the intermediate substrate and the thermal expansion coefficient (α2) of the reinforcing substrate have a relationship of α1> α2. The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31942799A JP3374812B2 (en) | 1999-11-10 | 1999-11-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31942799A JP3374812B2 (en) | 1999-11-10 | 1999-11-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001135749A JP2001135749A (en) | 2001-05-18 |
| JP3374812B2 true JP3374812B2 (en) | 2003-02-10 |
Family
ID=18110083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31942799A Expired - Fee Related JP3374812B2 (en) | 1999-11-10 | 1999-11-10 | Semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3374812B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101919248B1 (en) | 2014-01-09 | 2018-11-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device package with warpage control structure |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4930204B2 (en) * | 2007-06-07 | 2012-05-16 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| JP5150518B2 (en) | 2008-03-25 | 2013-02-20 | パナソニック株式会社 | Semiconductor device, multilayer wiring board, and manufacturing method thereof |
| JP5980566B2 (en) * | 2012-05-17 | 2016-08-31 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| DE102014114973B4 (en) * | 2014-10-15 | 2020-10-01 | Infineon Technologies Ag | Press-fit package with chip contact on active surface with stress protection and process for manufacturing the same |
-
1999
- 1999-11-10 JP JP31942799A patent/JP3374812B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101919248B1 (en) | 2014-01-09 | 2018-11-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device package with warpage control structure |
| US10685920B2 (en) | 2014-01-09 | 2020-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package with warpage control structure |
| US11329006B2 (en) | 2014-01-09 | 2022-05-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package with warpage control structure |
| US11764169B2 (en) | 2014-01-09 | 2023-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package with warpage control structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001135749A (en) | 2001-05-18 |
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