JPH10229102A - Electronic product - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize deformation of a warpage of a laminated material subsequent to the connection of LSI chips with an organic wiring board in the case where the LSI chips are respectively mounted on the surface and backside of the board in an asymmetrical state to the minimum, by a method wherein the thicknesses and elastic coefficients of the LSI chips, the board and a resin which constitute the laminated material, are controlled. SOLUTION: As a method of preventing deformation of a warpage of a laminated material, which is caused by a difference between the linear expansion coefficients of LSI chips subsequent to the connection of the chips 1 with an organic wiring board 3 and a difference between the linear expansion coefficients of resins 2 and the organic wiring board 3, the chips 1 of the same thickness are aligned with chip side bump electrodes 5 and board side electrodes 4 using the resins 2, such that the chips 1 are mounted on the surface and backside of the board 3 in a symmetrical state with the center of the middle of the board 3 as an axis in the section of the laminated material and thereafter, are respectively mounted on the surface and backside of the board 3. At this point, laminated members of a structure, wherein the sum total of the bending rigidities of each laminated material, which is constituted of a member in the range of the bending rigidity of roughly 10 to 90W(kg mm<2> ) (W: the width (mm) of a composite member) of the chips 1 and a member in the range of the bending rigidity of roughly 0.0004 to 4W(kg mm<2> ) of the board 3 which is connected with these chips 1, is roughly 30W(kg mm<2> ) or higher, are respectively mounted on the surface and backside of the board 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic circuit
The present invention relates to a mounting structure in which chips are connected by a flip chip method.

[0002]

BACKGROUND ART LSI chip implementation in an electronic component such as a far primarily but there was a face-up method according Waiyabonde _Lee ring, as the packing density increases, becoming increasingly so face-down type of a resin is employed It is expected that this face-down mounting will be the main focus in the future.

[0003] The mounting by the face-down method using the resin is a method in which the electrodes of the LSI chip and the wiring electrodes of the organic wiring board are electrically connected and simultaneously fixed with the resin. There is a concern that the reliability of the connection may be degraded due to the warpage of the laminate due to the difference in linear expansion coefficient between the chip, the resin, and the organic wiring substrate. As a method for preventing warpage deformation, as shown in FIG. 1, an LSI chip 1 of the same thickness is symmetrical on the front and back sides of the substrate with respect to the center of the wiring substrate 3 in the cross section of the laminate as shown in FIG. There is a method of mounting the side electrode 4 after positioning using the resin 2.

[0004]

However, in such a method, it is necessary to always mount the board symmetrically on the front and back sides of the board.

The present invention relates to a case in which an LSI chip and an organic wiring board are mounted by a face-down method using a resin, and the LSI chip, the organic wiring board, and the resin constituting the laminate without applying any external force to the laminate. By controlling the thickness and the elastic modulus, the warpage of the laminated body after connection when mounted asymmetrically on the front and back of the substrate is to be minimized.

[0006]

In general, it is known that the bending rigidity EI indicates the magnitude of the deformation resistance of a beam and the amount of deformation is inversely proportional to the deformation of the beam due to mechanical bending of the beam. References: Ichiro Nakahara, Mechanics of Materials). Here, E is a modulus of elasticity of the material, and I is a second moment of area determined by the shape and size of the cross section regardless of the material.

FIG. 2 is a perspective view of a laminate comprising n layers. An n-layer LSI chip 11 is mounted on a wiring board 10 with a resin 12
FIG. Length L (mm), width w (mm) (L
FIG. 3 is a cross-sectional view when the laminate of ≧ w) is taken in the AA ′ direction. As described above, the second moment of area is determined by the shape and size of the cross section. The cross section of the laminate has a rectangular form, moment of inertia of area I in this case is wh ^3/12
(H; thickness). Therefore, the sum? En _n I _n the flexural rigidity of the stacked body illustrated in FIG. 3,

[0008]

[Number 1] is represented as _{ΣE n I n = E 1 w} 1 h 1 3/12 + E 2 w 2 h 2 3/12 + ····· + E n w n h n 3/12 ... ( Equation 1).

Sum of bending stiffness of laminates having different layer structures 異 な る
E _n I _n the deformation amount of the seek relationship as shown in FIG. 4, the deformation amount is inversely proportional to the sum? En _n I _n the bending stiffness, is ΣE _n I _n 30
Above w (kgmm ² ), the deformation becomes small and stable. The present invention proposes an appropriate layer configuration of the laminate based on this fact.

[0010]

FIG. 5 shows a first embodiment of the present invention.
Linear expansion coefficient ^{α = 3.0 × 10 ~ 6 /} ℃, the LSI chip 20 having physical properties of elastic modulus E = 169.8GPa, linear expansion coefficient at a temperature lower than the glass transition temperature ^{_{α 1 = 11.6 × 10 ~ 6}} / ℃, the glass transition temperature The coefficient of linear expansion α ₂ = 1.4 × 10 ⁶ / ° C. above, the elastic modulus E _G of the glassy region = 17.5 GPa, and the elastic modulus E _R of the rubbery region E _R = 5.2 GP
a, a glass epoxy substrate 21 having a physical property of Tg = 158 ° C. is subjected to a linear expansion coefficient α ₁ = 65.6 × 10 to ⁶ / ° C. and a linear expansion coefficient α ₂ = 184.9 × 10
~ ⁶ / ° C., the elastic coefficient of the glass-like region E _G = 2.5 GPa, rubbery region coefficient of elasticity _{E R = 0.01GPa, Tg = 115} ℃ constituent materials using small amount of filler-containing resin 22 having the properties of Were connected at 180 ° C. while changing the thickness of the laminate, and the amount of deformation of the laminate when the laminate was cooled to 20 ° C. was measured. The size of the laminate is 13 mm in length
X The amount of deformation in the length direction was measured at a width of 3 mm. In this case, the thickness of the resin is approximately 0.01 mm. FIG. 6 shows the relationship between the thickness of the LSI chip 20 and the amount of deformation when the thickness of the glass epoxy substrate 21 is constant at 0.4 mm. As the thickness of the LSI chip 20 increases, the amount of deformation decreases. Sum of bending stiffness at this time Σ
The amount of deformation of the relationship between E _n I _n shown in FIG. ? En _n I rigidity of the entire laminate as the value increases the _n is increased, the amount of deformation is small. 8 by plotting the deformation amount of the relationship? En _n I _n when varying the thickness of the LSI chip 20 and the glass epoxy substrate 21. ΣE from Figure ^{_{8 n I n = 90kgmm 2 (}} w = 3m
It can be seen that the deformation amount is small and stable above m). In a stable region where the deformation amount is small, no problem occurred in terms of reliability. FIG. 9 shows the relationship between the chip thickness / substrate thickness and the amount of thermal deformation at this time. From this figure, it can be seen that the ratio of the LSI chip to the thickness of the glass epoxy substrate is 1.4 or more in the region where the amount of thermal deformation is small and stable.

FIG. 10 shows a second embodiment. In this example, an LSI chip 31 is mounted on a printed wiring board 32 using an anisotropic conductive adhesive 33. FIG. 1 is a sectional view of a contact portion of the electrode 34.
It is shown in FIG. The protruding electrode 35 on the chip side and the electrode 36 on the substrate side are electrically connected by conductive particles 37 in the anisotropic conductive adhesive, and are bonded and fixed by the resin 38 in the anisotropic conductive adhesive. . Particle diameter of the conductive particles for calculation of? En _n I _n in this case, the height of the electrodes is very small compared to the thickness of other constituent materials, electrodes and conductive particles occupying the connection area of the LSI chip Since the ratio is very small, conductive particles, protruding electrodes on the chip side, and electrodes on the substrate side are ignored. Here, the elastic modulus (20 ° C.) of the resin of the anisotropic conductive adhesive used is approximately 2.5 GPa.

[0012]

[Number 2] ΣE _n I _n = EI (LSI chip) + EI (resin) + EI (substrate) = (16980 × w × 0.55 3 /12)+(250×w×0.059 3/12) + (1750 × w × ^{0.8 3/12) = 310.1w kgmm} 2 ... ( it becomes Equation 2) above, deformation amount and ΣE in the material structure
relationship _n I _n is according to Figure 4.

FIG. 12 shows a third embodiment. 0.4mm thick
A 0.4 mm thick LSI chip 42 is bonded to a glass epoxy substrate 41 with a silver paste 43, and 0.17
FIG. 4 is a diagram in which an LSI chip 44 having a thickness of mm is electrically connected by an anisotropic conductive adhesive 45. This for the calculation of? En _n I _n when ignoring electrode and conductive particles, silver for the same reason as in the second embodiment. The elastic modulus of the adhesive of the silver paste 43 is approximately 1 GPa.

[0014]

Equation 3] ΣE _n I _n = EI (substrate) + EI (silver paste) + EI (0.4 mm thick LSI chip) + EI (anisotropic conductive adhesives) + EI (0.17 mm thick LSI chip) = 106.8w kgmm ² ... (Number 3) becomes above, this case is the relationship of the deformation amount and the? En _n I _n but according to FIG. 4, a material is symmetrically identical construction material mounted on both sides of the substrate 41, even thickness identical Is an exception.

[0015]

According to the present invention, a simple preliminary experiment or simulation is performed to control the sum of the bending stiffness of the laminate. That is, by appropriately controlling the layer configuration, an electronic device having an optimal semiconductor element mounting structure that minimizes deformation due to heat and mechanical external force when mounted asymmetrically on the front and back of the substrate. We can provide products.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a double-sided mounting example.

FIG. 2 is a perspective view of a laminate including n layers.

FIG. 3 is a cross-sectional view of a laminate having a length L (mm) and a width w (mm) (L ≧ w).

[4] Bending characteristic diagram of the amount of deformation of the relationship between the sum? En _n I _n rigidity.

FIG. 5 is an explanatory diagram of a laminate of an LSI chip / resin / glass epoxy substrate.

FIG. 6 is a characteristic diagram showing a relationship between a thickness of an LSI chip and a deformation amount in an LSI chip / resin (0.01 mmt) / glass epoxy substrate (0.4 mmt) laminate.

[7] LSI chip / resin (0.01mmt) / glass epoxy substrate (0.4mmt) characteristic diagram of the amount of deformation of the relationship between the sum? En _n I _n the flexural rigidity in the laminate.

[8] LSI chip / resin / characteristic diagram of the amount of deformation of the relationship between the sum? En _n I _n the flexural rigidity in a glass epoxy substrate laminate.

FIG. 9 is a characteristic diagram showing a relationship between a chip thickness / substrate thickness and an amount of thermal deformation.

FIG. 10 is a perspective view of a mounting example of a COB (chip-on-board).

FIG. 11 is a sectional view of a connection portion of a COB electrode.

FIG. 12 is a cross-sectional view of a COB double-sided mounting example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LSI chip, 2 ... resin, 3 ... wiring board, 4 ... board side electrode, 5 ... chip side protrusion electrode.

Claims (2)

[Claims] (1) In addition to an LSI chip and a substrate, a resin, a metal,
In a composite member comprising an n-layer of ceramics, the LS
The flexural rigidity EI of the I chip is approximately 10 w to 90 w (kgmm ² ) (w; width of the composite member (mm)), and the flexural rigidity EI of the substrate connected thereto is approximately 0.0004 w to ⁴ w (kgmm ² ). total? En _n I _n the bending range of the member composed laminated rigid member mounting the laminated member having (; modulus of elasticity, I E geometrical moment of inertia) approximately 30w (kgmm ²⁾ or more and consisting structure An electronic product characterized by that: 2. In addition to the LSI chip and the substrate, resin, metal,
In a composite member comprising an n-layer of ceramics, the LS
An electronic product wherein a laminated member having an I-chip thickness of at least 1.4 times the thickness of the substrate is mounted.