JP2000138453A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board with improved reliability in temperature change and excellent strength. SOLUTION: A core substrate 32 is provided where a first-stage wiring pattern 38 is formed on an organic insulating layer 35 on both surfaces of the core 33 while electrically connected through a conductive medium 37 formed inside a through hole 34, with the metal core 33 where the through hole 34 is formed provided while the organic insulating layer 35 formed on both surfaces of the core 33 and on the inside wall of the through hole 34. Further, wiring patterns 43 and 45 at second and later stages are formed on the first-stage wiring pattern 38 of a core substrate 32, by required stages sequentially through insulating layers 40 and 44, wherein required wiring patterns comprising the first-stage wiring pattern 38 are electrically connected with a conductive medium 42 formed by penetrating the insulating layers 40 and 44.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring board suitable for use as a package for mounting a semiconductor chip.

[0002]

2. Description of the Related Art In recent years, resin wiring boards which are easy and inexpensive to manufacture are becoming mainstream. FIG. 5 shows a build-up board 10 which is a resin wiring board on which a semiconductor chip is mounted. 12 is the core substrate. The core substrate 12 is formed by performing electroless copper plating and then electrolytic copper plating on both surfaces of a core 16 made of a resin (glass-reinforced resin such as bismaletriazine-BT resin) on which a through hole 14 is formed. The plating film is etched to form first-stage wiring patterns 20, 20 electrically connected by a through-hole plating film (conductive medium) 18.

The second-stage wiring patterns 24, 24 and the third-stage wiring patterns 26, 26 are formed on the first-stage wiring patterns 20, 20 via insulating layers 22, 22 by a known build-up method. Is formed. 28 and 28 are solder resist layers. The semiconductor chip mounting portion is formed on one side, and the third-stage wiring pattern 26 is formed on the other side.
A bump (not shown) for external connection is formed to complete the wiring substrate 10.

[0004]

The semiconductor chip made of silicon has a coefficient of thermal expansion of 3 to 4 × 10 ⁻⁶ / ° C.
The mounting board (printed wiring board) on the side where the wiring board 10 is mounted has a thermal expansion coefficient of about 17 × 10 ⁻⁶ / ° C. The thermal expansion coefficient of the wiring substrate 10 is approximately 16 to 17 × 10 ⁻⁶ / ° C., depending on the thermal expansion coefficient of the core 16 made of a glass-reinforced resin, which is a main material.

According to the conventional wiring board, the coefficient of thermal expansion between the wiring board and the mounting board is substantially matched, and the stress concentration between them is eliminated, but the coefficient of thermal expansion between the wiring board 10 and the semiconductor chip is reduced. There is a problem that reliability is low with respect to a temperature change, for example, a difference is large, stress is concentrated on a semiconductor chip after a temperature cycle, and distortion occurs. Further, recently, the thickness of the wiring board 10 tends to be relatively thin, and the strength is reduced. Therefore, it is necessary to add a separate stiffener, and there is a problem that the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a wiring board having improved reliability against temperature change and excellent strength.

[0007]

The present invention has the following arrangement to achieve the above object. That is, a metal core having a through hole is formed, an organic insulating layer is formed on both surfaces of the core and the inner wall of the through hole, and the organic insulating layer is formed in the through hole on the organic insulating layer on both surfaces of the core. A core substrate on which a first-stage wiring pattern electrically connected through the conductive medium is formed, and a required number of stages are sequentially formed via an insulating layer on the first wiring pattern of the core substrate,
Required wiring patterns including the first-stage wiring pattern are provided with a second-stage or lower wiring pattern electrically connected by a conductive medium penetrating the insulating layer.

Since a metal is used for the core, by selecting a metal material for the core, the thermal expansion coefficient of the wiring board can be reduced to the thermal expansion coefficient of the silicon semiconductor chip by 3 to 4 × 1.
0 ^-6 / ° C and thermal expansion coefficient of the mounting board side of 16 to 17 × 10
^It can be adjusted to an intermediate size of ^-6 / ° C, balances the coefficient of thermal expansion between silicon chips, wiring boards, and mounting boards, reduces stress concentration and distortion, and changes in temperature. Reliability can be improved. In addition, metal has higher strength than resin, so the overall strength can be increased without adding a separate stiffener,
Cost can be reduced.

A bump for external connection can be formed by connecting to the outermost wiring pattern. Further, a semiconductor chip mounting portion can be provided and used as a package for mounting a semiconductor chip. In this case, a terminal for flip chip bonding of the semiconductor chip can be formed in the semiconductor chip mounting portion, so that the semiconductor chip can be flip chip connected. Further, by providing two or more semiconductor chip mounting portions, a package compatible with MCM can be provided.

[0010] A clad material comprising two or more metal layers can be used for the metal core. The use of such a clad material is preferable because the coefficient of thermal expansion of the core can be adjusted. When the metal core has a thermal expansion coefficient between 3 × 10 ⁻⁶ / ° C. and 12 × 10 ⁻⁶ / ° C. or less, which is an intermediate thermal expansion coefficient between the silicon chip and the mounting substrate, a semiconductor is used. This is preferable because the thermal expansion coefficient when the chip is mounted and mounted on the mounting board is balanced.

It is preferable to use a plurality of independent metal plates in the same plane for the metal core. In particular, the metal plate includes an independent metal plate corresponding to a portion corresponding to the semiconductor chip mounting portion and an independent metal plate corresponding to a portion other than the semiconductor chip mounting portion. It is preferable to use one having In this case, on the metal plate corresponding to the semiconductor chip mounting portion,
A semiconductor chip having an area of 1 to 1.5 times the area of the semiconductor chip is preferably used.

Further, two or more metal plates independent of a thickness direction of the core substrate are used for the metal core.
It is preferable to use a metal plate having at least two layers by bonding them via an organic adhesive. In this case, two or more metal plates having different thermal expansion coefficients are used, and these metal plates are located on the other side from the metal plate located on the semiconductor chip mounting portion side. It is preferable to arrange so as to increase toward the metal plate. By doing so, the occurrence of distortion in the semiconductor chip can be suppressed, and the thermal stress with the mounting substrate can be reduced.

It is more preferable that the metal core is electrically connected to a required portion so that the core also serves as a power supply layer or a ground layer. Instead of the above-mentioned metal cores, a carbon composite plate may be used.

[0014]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an explanatory cross-sectional view illustrating an example of the wiring board 30. Reference numeral 32 denotes the core substrate. The core substrate 30 has a metal core 33. The core 33 has a thickness of about 0.2 to 0.6 mm, but is not limited thereto. A through hole 34 is formed in the core 33. Organic insulating layers 35 are formed on both surfaces of the core 33 and on the inner walls of the through holes 34.

A through hole 34 is formed in a metal plate by a first drilling process. The metal plate having the through hole 34 is disposed between B-stage resin sheets, and is heated and press-laminated to form a surface of the metal plate. With resin,
The resin is filled in the through hole 34. Next, a second drilling process is performed on the through hole 34 so that the core 3
Organic insulating layers 3 on both sides of the substrate 3 and on the inner wall of the through hole 34.
5 can be formed. When copper is used for the core substrate, adhesion to the resin can be improved by performing blackening after performing the first drilling.

The organic insulating layer 35 can be made of an epoxy-based, maleimide-based, phenylene ether-based, tetrafluoroethylene-based, cyanoester-based, or imide-based resin. In these resins, glass or organic (such as aramid) woven or nonwoven fabric, or inorganic (Si
Or Al ₂ O ₃ ) particles. Organic insulating layer 3
5 may have a structure of two or more layers of different materials in order to improve the insulating property.

On the organic insulating layer 35 (including the inside of the through hole 34), electroless copper plating and then electrolytic copper plating are performed to form a copper plating film. By etching this copper plating film, first-stage wiring patterns 38, 38 electrically connected by the through-hole plating film 37 are formed on both surfaces of the core 33, and are formed on the core substrate 32. The resin 39 is filled in the through hole 34.

On both surfaces of the core substrate 32, insulating layers 40, 40 are formed by a modified epoxy resin sheet or the like. The thickness of the insulating layers 40, 40 is preferably approximately 40 to 50 μm. Fine via holes 41 are formed in the insulating layers 40 by a CO ₂ laser or the like. In the insulating layers 40, 40 and the via holes 41, 41, electroless copper plating and then electrolytic copper plating are performed to form a copper plating film, and the copper plating film on the surface is etched,
Second-stage wiring patterns 43, 43 that are electrically connected to the first-stage wiring patterns 38, 38 are formed by plating films (conductive media) 42 on the inner walls of the via holes. Insulating layer 40
For example, a polyphenylene ether-based, polyimide-based, or cyanoester-based resin can be used. In addition, the resin that becomes the insulating layer 40 may contain inorganic particles, glass, an organic woven fabric, or a nonwoven fabric.

In the same manner as described above, the third-stage wiring is electrically connected to the second-stage wiring patterns 43 by the plating film (conductive medium) 42 on the inner wall of the via hole 41 on the insulating layers 44, 44. Patterns 45, 45 are formed. Except for the semiconductor chip mounting portion (not shown) formed on one surface side of the wiring board 30 and the pad portion (not shown) formed on the other surface side, on the third-stage wiring pattern 45. , And are covered with the solder resist layers 46 and 46.

A terminal (not shown) for flip-chip connection of the semiconductor chip, which is connected to the third-stage wiring pattern 45, is formed in the semiconductor chip mounting portion. The semiconductor chip may be electrically connected to the third-stage wiring pattern 45 by a wire. Alternatively, a plurality of semiconductor chip mounting portions may be provided and formed on an MCM wiring substrate compatible with a multichip. A solder ball or the like is attached to the pad portion to form a bump (not shown) for external connection. It is formed on the wiring board 30 as described above.

The insulating layers 40 and 44 may be formed by applying a photosensitive resist, and the via holes 41 may be formed by known photolithography. The number of wiring patterns in the second and lower stages (the second and lower stages include the case of only the second stage) is not particularly limited. Also,
The core 33 of the core substrate 32 may be used as a power supply layer or a ground layer. In this case, a fine hole (not shown) is provided in the organic insulating layer 35, and a plating film is formed in the hole in a plating step of forming the first-stage wiring pattern 38. The core 33 is connected to the power supply line or the ground line of the first wiring pattern 38 by the film.

The coefficient of thermal expansion of the wiring board 30 depends largely on the thickness of the core 33 made of the main material. However, according to the wiring board 30, since the core 33 is made of metal, the core 33 has a large thermal expansion coefficient. Is selected, the thermal expansion coefficient of the wiring board 30 is set to 3 to 4 × 10 ⁻⁶ / ° C. for the silicon semiconductor chip, and the thermal expansion coefficient of the mounting board side to 16 to 17 × 10 ^−6. / ° C., which can be adjusted to an intermediate size, and the thermal expansion coefficient between the silicon chip, the wiring board 30 and the mounting board can be balanced, stress concentration and distortion can be reduced, Reliability can be improved. Further, since the strength of metal is higher than that of resin, the overall strength can be increased without adding a separate stiffener, and the cost can be reduced.

The core 33 of the core substrate 32 is preferably made of a metal having a coefficient of thermal expansion of 3 × 10 ⁻⁶ / ° C. or more and 12 × 10 ⁻⁶ / ° C. or less. For example, for the core 33, an alloy such as a Kovar (iron-nickel-cobalt) alloy, a 42 alloy (iron-nickel), molybdenum, or a pure metal can be used. The thermal expansion coefficient of Kovar alloy is about 6 × 10 ^-6 /
C., the coefficient of thermal expansion of the 42 alloy is about 4.times.10.sup.- ⁶ / .degree. C., and that of molybdenum is about 5.times.10.sup.- ⁶ / .degree.

Further, the core 33 is not limited to a single-layer metal, but may be a clad material in which dissimilar metal layers are joined. For example, as a clad material, copper, invar, copper (copper volume ratio is 40 to 60%, and the thermal expansion coefficient of the clad material is 6 to 9 ×
10 ^-6 / ° C), copper / 42 alloy / copper (copper volume ratio 40 ~
At 80%, the coefficient of thermal expansion of the clad material is 6 to 10 × 10 ^-6 /
℃), copper, Kovar alloy, copper (40-70 volume ratio of copper)
% And the coefficient of thermal expansion of the clad material is 8-11 × 10 ^-6 / ° C)
The thermal expansion coefficient of the entire wiring board 30 can be adjusted. Copper-molybdenum,
A copper impregnated material such as copper-tungsten can also be used. When these copper composite materials are used, the copper ratio is determined by the thermal conductivity (at least 100 W / mk in the plane direction in the above range) and the electric resistance (all 6 × in the above range) in addition to the above thermal expansion coefficient. 10 ⁻⁶ Ωcm). Further, instead of the metal core 33, a carbon composite material can be used. The carbon composite material has a coefficient of thermal expansion of 1 to 10 × 10 ⁻⁶ / ° C.
It is.

FIG. 2 shows another embodiment. In the present embodiment, instead of using one metal plate for the core 33,
A plurality of planarly independent metal plates are used. For example, one metal plate 33a is provided at the center, and a frame-shaped metal plate 33b is provided around the metal plate 33a. The other configuration is the same as that shown in FIG. 1, and therefore the description is omitted and the drawing is shown in a simplified manner. The metal plate 33a and the metal plate 33b may be arranged with a gap, or may be fitted into the frame-shaped metal plate 33b by contacting the metal plate 33a. The number of metal plates to be made independent is not limited to two, and may be three or more. When a plurality of metal plates are independently formed, each metal plate can be used as a power supply layer, a ground layer, or the like.

FIG. 3 shows an example in which the metal plate 33a disposed at the center and the metal plate 33b disposed at the periphery of the device shown in FIG. 2 have different thermal expansion coefficients. In this case, the metal plate 33a disposed at the center is set so as to correspond to the semiconductor chip mounting portion, and its thermal expansion coefficient is smaller than that of the metal plate 33b disposed at the periphery.
It is preferable to use one close to a silicon semiconductor chip. For example, a 42 alloy or molybdenum can be used as the metal plate 33a. By doing so, the thermal expansion coefficient can be matched with the semiconductor chip 50 mounted on the semiconductor chip mounting portion, and the occurrence of distortion of the semiconductor chip 50 can be suppressed as much as possible. In this case, the area of the metal plate 33a is preferably not less than 1 and not more than 1.5 times the area of the semiconductor chip 50. Using a metal plate 33a slightly larger than the semiconductor chip 50 is effective for preventing distortion.

On the other hand, the peripheral metal plate 33b has a thermal expansion coefficient of 16 to 17 × 10 ^-6 /
It is preferable to use one close to ° C. For example, copper can be used as the metal plate 33b. Many bumps such as solder balls are arranged at this portion and are bonded to the mounting substrate via the bumps. Therefore, the thermal expansion coefficient is more suitable as the position is closer to the mounting substrate.

FIG. 4 shows still another embodiment. In the present embodiment, a structure in which a plurality of metal plates are joined to the core 33 of the core substrate 32 using an organic adhesive is used.
The other configuration is the same as that shown in FIG. 1, and therefore the description is omitted and the drawing is shown in a simplified manner. In the illustrated example, three metal plates 33c, 33d, 33e are provided on the core 33.
And the respective metal plates are joined by an adhesive 48.

Preferably, these metal plates are arranged so that the coefficient of thermal expansion increases in order from the metal plate 33c located on the semiconductor chip mounting portion side to the metal plate 33e located on the other side (bump forming side). It is. For example, a metal plate 33
For c, a copper / invar / copper clad plate or a 42 alloy material (thermal expansion coefficient: 3 to 4 × 10 ⁻⁶ / ° C.)
Is made of a Kovar alloy (about 6 × 10 ⁻⁶ / ° C.) and a metal plate 33.
Nickel (about 13 × 10 ⁻⁶ / ° C.) or copper (about 17 × 10 ⁻⁶ / ° C.) can be used for e. In this case, the core 33 is not limited to three layers, but may be any two or more layers.

By providing a gradient in the coefficient of thermal expansion as described above, it is possible to suppress the occurrence of distortion of the semiconductor chip 50 mounted on the semiconductor chip mounting portion, as shown in FIG.
Also, thermal stress is not generated on the mounting substrate side, which is preferable. When the metal plate is composed of a plurality of metal plates as shown in FIGS. 2 to 4, each metal plate may be used with different functions such as a power supply layer and a ground layer. it can.

[0031]

According to the wiring board of the present invention, as described above, the metal is used for the core. Therefore, by selecting the metal material of the core, the thermal expansion coefficient of the wiring board can be reduced by that of silicon. It can be adjusted to an intermediate value between the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion on the mounting board side, balance the coefficient of thermal expansion between the silicon chip, the wiring board and the mounting board, and concentrate the stress. In addition, distortion can be reduced, and reliability against temperature change can be improved. Further, since the strength of metal is higher than that of resin, the overall strength can be increased without adding a separate stiffener, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional explanatory view of a wiring board,

FIG. 2 is an explanatory view of an example in which a plurality of independent metal plates are used for a core;

FIG. 3 is an explanatory diagram of an example in which a plurality of independent metal plates having different coefficients of thermal expansion are used for a core;

FIG. 4 is an explanatory diagram of an example in which a core is formed by bonding a plurality of metal plates with an adhesive,

FIG. 5 is an explanatory sectional view of a conventional wiring board.

[Explanation of symbols]

 REFERENCE SIGNS LIST 30 wiring board 32 core board 33 core 34 through hole 35 organic insulating layer 37 through hole plating film 38 first stage wiring pattern 40 insulating layer 41 via hole 42 plating film (conductive medium) 43 second stage wiring pattern 44 insulating layer 45 Third-stage wiring pattern 48 Adhesive 50 Semiconductor chip

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Mitsuharu Shimizu 711 Toshida, Kurita-sha, Nagano City, Nagano Prefecture F-term (reference) 5E315 AA05 AA10 BB01 BB02 BB05 BB15 BB16 CC01 CC14 DD15 DD16 DD17 DD25 DD27 GG16 5E346 AA03 AA12 AA15 AA25 AA43 BB03 BB04 BB07 BB16 CC09 CC10 CC32 DD02 DD25 DD32 DD48 EE31 EE33 FF15 FF45 GG15 GG17 GG27 GG28 HH11

Claims (14)

[Claims] A metal core having a through-hole formed therein, an organic insulating layer formed on both surfaces of the core and inner walls of the through-hole, and an organic insulating layer formed on the organic insulating layer on both surfaces of the core; A core substrate on which a first-stage wiring pattern electrically connected via the formed conductive medium is formed, and a required number of stages formed sequentially on the first-stage wiring pattern of the core substrate via an insulating layer And a second and subsequent wiring patterns electrically connected between required wiring patterns including the first wiring pattern by a conductive medium formed through the insulating layer. Wiring board. 2. The method according to claim 1, wherein a bump for external connection is formed on an outermost wiring pattern.
The wiring board as described. 3. The wiring board according to claim 1, wherein a semiconductor chip mounting portion is formed. 4. The wiring board according to claim 3, wherein a terminal for flip-chip connecting the semiconductor chip is formed in the semiconductor chip mounting portion. 5. The wiring substrate according to claim 3, wherein two or more semiconductor chip mounting portions are formed. 6. The wiring board according to claim 1, wherein the metal core is formed using a clad material composed of two or more metal layers. 7. The metal core has a coefficient of thermal expansion of 3 ×.
Wiring board according to claim 2, 3, 4, 5 or 6 wherein it is a ^{10 -6 / ℃ ~12 × 10 -6} / ℃. 8. The wiring board according to claim 1, wherein the metal core is composed of a plurality of metal plates independent in a plane direction. 9. The metal plate includes a metal plate at a portion corresponding to the semiconductor chip mounting portion and a metal plate corresponding to a portion other than the semiconductor chip mounting portion, and the two metal plates have different coefficients of thermal expansion. 9. The wiring board according to claim 8, wherein: 10. The wiring board according to claim 9, wherein the metal plate at a portion corresponding to the semiconductor chip mounting portion has an area of 1 to 1.5 times the area of the semiconductor chip. 11. The metal core is composed of two or more metal plates independent in a thickness direction, and each of the metal plates is joined via an organic adhesive layer. The wiring board according to claim 1, 2, 3, 4, or 5. 12. Each of the two or more metal plates has a different coefficient of thermal expansion, and the coefficient of thermal expansion increases from the metal plate located on the semiconductor chip mounting portion side to the metal plate located on the other side. The wiring board according to claim 11, wherein the wiring board is arranged so as to be arranged as follows. 13. A power supply layer or a ground layer, wherein said metal core is electrically connected at a predetermined position, and is used as a power supply layer or a ground layer. ,
The wiring board according to 8, 9, 10, 11 or 12. 14. The wiring board according to claim 1, wherein the core is formed by using a carbon composite plate instead of the metal core.