JP3626631B2 - LSI chip mounting structure - Google Patents

LSI chip mounting structure Download PDF

Info

Publication number
JP3626631B2
JP3626631B2 JP16808799A JP16808799A JP3626631B2 JP 3626631 B2 JP3626631 B2 JP 3626631B2 JP 16808799 A JP16808799 A JP 16808799A JP 16808799 A JP16808799 A JP 16808799A JP 3626631 B2 JP3626631 B2 JP 3626631B2
Authority
JP
Japan
Prior art keywords
lsi chip
substrate
lsi
mounting structure
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16808799A
Other languages
Japanese (ja)
Other versions
JP2000357709A (en
Inventor
正義 三好
浩史 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16808799A priority Critical patent/JP3626631B2/en
Publication of JP2000357709A publication Critical patent/JP2000357709A/en
Application granted granted Critical
Publication of JP3626631B2 publication Critical patent/JP3626631B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はＬＳＩチップの実装構造に関するものであり、特にシリコン基板ボールグリッドアレイに関するものである。
【０００２】
【従来の技術】
近年、ＬＳＩパッドの微細化は急速に進んでいる。これは、ＣＳＰ（チップ・サイズ・パッケージ）実装、フリップチップ実装が普及してきたことを示している。回路実装学会誌（ＶＯＬ．１１ Ｎｏ．７ ＮＯＶ．１９９６）Ｐ．４６９の図に示すように、現在ではボールグリッドアレイに搭載するＬＳＩについてもフリップチップ実装することが一般的になってきている。簡単な断面図を図４に示す。プリント基板にフリップチップ実装をする場合、図４にも示すような通常の貫通スルーホールのプリント基板６ではフリップチップを受けるパッドを製造することができないため、表面にビルドアップ層を１〜２層形成し、微細なパッドを製造している。図４では、ビルドアップ層１１がコア基板１２の両表面に形成されている。また、ＣＯＢ（チップ・オン・ボード）をフリップチップ実装で行う場合を図５に示す。ＣＯＢは、フリップチップＬＳＩを基板に直接搭載する実装方式である。図５において、ＬＳＩ１を実装するために、ビルドアップ配線基板２１はビルドアップ層２０を形成している。
【０００３】
【発明が解決しようとする課題】
しかし、その微細化されたフリップチップを実装する実装基板、ケース基板についてその進歩はＬＳＩの進歩に対して決して早いとは言えない。現在、２０００ピンクラスのＬＳＩを実装するためにはビルドアップ層は４層必要となる。多層化することは非常に困難なことであり、価格の上昇の要因となってしまう。ＬＳＩのパッドにおいて更なる微細化が進んだ場合、ビルドアップ層は多層化、微細化を進める必要がある。
【０００４】
また、ＣＯＢに用いるビルドアップ基板のビルドアップ層は、フリップチップを搭載するエリアだけに形成することはできないため、フリップチップ用多ピンＬＳＩが１個でも搭載する場合には、基板全面をビルドアップ層を形成する。そのためビルドアップ基板は面積が大きくなると歩留まりの低下、コストの上昇を招くことになる。
【０００５】
ビルドアップ基板の他に、従来技術による微細化配線が可能な基板としては、ガラスセラミックのベース基板の上に銅のパターンとポリイミドとを積層した基板もあるが、これはビルドアップ基板以上に高価でありコストアップの原因になる。
【０００６】
本発明の目的は、ＬＳＩのプロセスを使用することによりＬＳＩの微細化に対応したＬＳＩチップの実装構造を提供することである。
【０００７】
【課題を解決するための手段】
本発明によれば、第１の基板と、前記第１の基板上に実装される第２の基板と、前記第２の基板上に実装されるＬＳＩチップと、前記第２の基板に積層され、前記ＬＳＩチップと同等の熱膨張係数を有する補強板とを含み、前記ＬＳＩチップ及び前記第２の基板は、シリコンで形成され、前記第２の基板は、前記ＬＳＩチップの入出力パッドを介して前記ＬＳＩチップと接続され、接続用パッド、及び、前記ＬＳＩチップの入出力パッドと前記接続用パッドとを接続する配線を有し、前記接続用パッドを介して前記第１の基板に接続され、前記配線により前記ＬＳＩチップの入出力パッドのピンのピッチが前記接続用パッドのピンのピッチまで展開されていることを特徴とするＬＳＩチップの実装構造が得られる。
【０００８】
【０００９】
【００１０】
【００１１】
【００１２】
【００１３】
【００１４】
【発明の実施の形態】
以下、本発明の一実施の形態について図１〜図３を参照して詳細に説明する。１はＬＳＩチップである。ＬＳＩチップ（ベアチップ）１は回路面に入出力パッド８（図２参照）を有するベアチップである。入出力パッド８は０．１ｍｍピッチで２０００ピンを配列している。図２に示すようにＬＳＩチップ１の外形は１０ｍｍでほぼフルグリッドに入出力パッド８を配列している。３はシリコン基板であり、信号層１層、ＧＮＤ、及び電源層からなる。
【００１５】
シリコン基板３には、シリコン基板３とプリント基板６を接続するＰＷＢ（プリンテッド ワイヤリング ボード）接続パッド９が形成されている。シリコン基板３の内部の配線は入出力パッド８とＰＷＢ接続パッド９を接続するものである。配線ルールはＬＳＩチップ１内部よりも粗いが、０．１ｍｍピッチのパッドに対しては配線層１層で十分に引くことができる。配線ルールは最も微細なところで線幅及び間隙をそれぞれ０．０１ｍｍ及び０．０１ｍｍとした。φ０．６ｍｍのＰＷＢ接続用パッド９は１．０mmピッチで２０００個二次元に配列している。
【００１６】
ＬＳＩチップ１の入出力パッド８のピンのピッチはＰＷＢ接続パッド９のピンのピッチまで展開することができることに本発明の特徴がある。シリコン基板１の外形は図３に示すように、５０mm程度であり、その板厚は１ｍｍ程度である。
【００１７】
４は窒化アルミの板であり、その板厚は１ｍｍである。窒化アルミ板４は、シリコン基板３の補強のために使用している。窒化アルミは熱膨張係数がシリコンに近くシリコンと接着する場合に反りが小さいという優れた効果を有する。また、熱伝導率も高いためＬＳＩの発熱を放出する役目を果たすことができる。尚、本実施の形態では上記補強板として窒化アルミ板を用いたが、熱膨張係数がシリコンに近く、熱伝導率が高い材料で形成されていれば他の材料でもよい。
【００１８】
２はシリコン基板３と窒化アルミ板４を機械的に接合するための接着剤である。接着剤には接合の信頼性が必要であることはもちろん、熱の伝達経路にもなるため熱伝導率の良いものを選択する必要がある。本実施の形態では、熱伝導率の良いＡｇ（銀）を含んだエポキシ接着剤を使用している。接着剤の厚さは１００μm以下となるようにコントロールすることが望ましい。
【００１９】
５は、シリコン基板３とプリント基板６を電気的に接続するはんだバンプである。ＬＳＩの高さが０．５〜０．６ｍｍあるため、はんだバンプ５は０．８ｍｍ程度を確保する必要がある。はんだバンプ５は高温はんだ等のコアを入れることにより高さをコントロールすることができるが、共晶はんだのはんだボールだけでも良い。
【００２０】
６はプリント基板である。本発明のシリコン基板ＢＧＡ（ボールグリッドアレイ）を使用することによりプリント基板は微細化を行うこと無しに多ピンＢＧＡを実装することができるため、本実施の形態では、通常のプリント基板を使用することができる。
【００２１】
以下、本発明の実装構造を有するシリコン基板ボールグリッドアレイの組立方法について述べる。まず、窒化アルミ板４とシリコン基板３を接着する。接着剤はＡｇエポを使用した。次に、ＬＳＩチップ１をシリコン基板３上にフリップチップ実装した後、アンダーフィル７で樹脂封止する。基板、ＬＳＩ共にシリコンで同じ材料であるため、アンダーフィルは本来の目的では必要としないが、取り扱いを容易にするため本実施例ではアンダーフィルを充填している。しかしながらアンダーフィルを充填しなくても以下に述べる本発明の効果は得られる。最後に、半田ボールをシリコン基板３上に取り付けることにより、シリコン基板ボールグリッドアレイが完成する。これを、プリント基板６上に搭載した図が図１である。
【００２２】
【発明の効果】
本発明は、シリコン基板を採用して、補強板を貼り付けることにより、シリコン基板上でＬＳＩのパッドピッチをＰＷＢのパッドピッチまで展開して半田ボールに接続させて、シリコン基板ＢＧＡとしているので、ＬＳＩと同じ材料、プロセスを使用することができる。したがって、ＬＳＩパッドピッチの微細化に対して、基板の微細化を同等に進歩させることができる。
【００２３】
また、多層化を行う必要が無く、ビルドアップ基板、ポリイミド基板の様な多層化による歩留まりの低下、コストのアップを抑えることができる。
【００２４】
また、シリコン基板ＢＧＡはＬＳＩと同じ材料を使用しているため、反りが少ない。
【図面の簡単な説明】
【図１】本発明のＬＳＩチップの実装構造を説明するための図である。
【図２】ＬＳＩチップの構造を示した図である。
【図３】本発明のＬＳＩチップの実装構造を有するシリコン基板の構造を示した図である。
【図４】従来のＬＳＩチップの実装構造の一例を説明するための図である。
【図５】従来のＬＳＩチップの実装構造の他の例を説明するための図である。
【符号の説明】
１ ＬＳＩチップ
２ 接着剤
３ シリコン基板
４ 窒化アルミ板
５ はんだバンプ
６ プリント基板
７ アンダーフィル
８ 入出力パッド
９ ＰＷＢ接続パッド
１０，２１ ビルドアップ配線基板
１１，２０ ビルドアップ層
１２ コア基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LSI chip mounting structure, and more particularly to a silicon substrate ball grid array.
[0002]
[Prior art]
In recent years, miniaturization of LSI pads is progressing rapidly. This indicates that CSP (chip size package) mounting and flip chip mounting have become widespread. Journal of Circuit Packaging Society (VOL.11 No.7 NOV.1996) As shown in FIG. 469, at present, flip-chip mounting has also become common for LSIs mounted on ball grid arrays. A simple cross-sectional view is shown in FIG. When flip-chip mounting is performed on a printed circuit board, a pad for receiving a flip chip cannot be manufactured with a normal through-hole printed circuit board 6 as shown in FIG. Forming and manufacturing fine pads. In FIG. 4, the buildup layer 11 is formed on both surfaces of the core substrate 12. FIG. 5 shows a case where COB (chip on board) is performed by flip chip mounting. COB is a mounting method in which a flip chip LSI is directly mounted on a substrate. In FIG. 5, the buildup wiring board 21 forms a buildup layer 20 in order to mount the LSI 1.
[0003]
[Problems to be solved by the invention]
However, it cannot be said that the progress of the mounting substrate and the case substrate on which the miniaturized flip chip is mounted is fast compared to the progress of LSI. Currently, four build-up layers are required to mount a 2000 pin class LSI. Multi-layering is very difficult and causes an increase in price. When further miniaturization of LSI pads progresses, the build-up layer needs to be multilayered and miniaturized.
[0004]
In addition, the build-up layer of the build-up substrate used for COB cannot be formed only in the area where the flip chip is mounted. Therefore, when even one flip-chip multi-pin LSI is mounted, the entire surface of the substrate is built up. Form a layer. Therefore, when the area of the build-up substrate is increased, the yield is reduced and the cost is increased.
[0005]
In addition to the build-up board, there is a board in which copper patterns and polyimide are laminated on a glass ceramic base board as a board that can be miniaturized by the conventional technology, but this is more expensive than the build-up board. This causes an increase in cost.
[0006]
An object of the present invention is to provide a mounting structure of an LSI chip corresponding to miniaturization of an LSI by using an LSI process.
[0007]
[Means for Solving the Problems]
According to the present invention, the first substrate, the second substrate mounted on the first substrate, the LSI chip mounted on the second substrate, and the second substrate are stacked. A reinforcing plate having a thermal expansion coefficient equivalent to that of the LSI chip, wherein the LSI chip and the second substrate are made of silicon, and the second substrate is connected via an input / output pad of the LSI chip. Connected to the LSI chip, and connected to the first substrate via the connection pad, and a connection pad and a wiring for connecting the input / output pad of the LSI chip and the connection pad. The LSI chip mounting structure is obtained in which the pitch of the pins of the input / output pads of the LSI chip is expanded to the pitch of the pins of the connection pads by the wiring.
[0008]
[0009]
[0010]
[0011]
[0012]
[0013]
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. Reference numeral 1 denotes an LSI chip. An LSI chip (bare chip) 1 is a bare chip having input / output pads 8 (see FIG. 2) on a circuit surface. The input / output pad 8 has 2000 pins arranged at a pitch of 0.1 mm. As shown in FIG. 2, the LSI chip 1 has an external shape of 10 mm, and input / output pads 8 are arranged in a substantially full grid. Reference numeral 3 denotes a silicon substrate, which includes a signal layer 1, a GND, and a power supply layer.
[0015]
A PWB (printed wiring board) connection pad 9 for connecting the silicon substrate 3 and the printed board 6 is formed on the silicon substrate 3. The wiring inside the silicon substrate 3 connects the input / output pad 8 and the PWB connection pad 9. Although the wiring rule is coarser than that inside the LSI chip 1, it can be sufficiently drawn with a single wiring layer for a pad with a pitch of 0.1 mm. The wiring rule has the smallest line width and gap of 0.01 mm and 0.01 mm, respectively. The PWB connection pads 9 having a diameter of 0.6 mm are two-dimensionally arranged at a pitch of 1.0 mm.
[0016]
The present invention is characterized in that the pin pitch of the input / output pad 8 of the LSI chip 1 can be expanded to the pitch of the pin of the PWB connection pad 9. As shown in FIG. 3, the outer shape of the silicon substrate 1 is about 50 mm, and the plate thickness is about 1 mm.
[0017]
Reference numeral 4 denotes an aluminum nitride plate having a thickness of 1 mm. The aluminum nitride plate 4 is used for reinforcing the silicon substrate 3. Aluminum nitride has an excellent effect that the thermal expansion coefficient is close to that of silicon and the warpage is small when bonded to silicon. In addition, since the thermal conductivity is high, it can serve to release the heat generated by the LSI. In this embodiment, an aluminum nitride plate is used as the reinforcing plate. However, other materials may be used as long as they have a thermal expansion coefficient close to that of silicon and high thermal conductivity.
[0018]
Reference numeral 2 denotes an adhesive for mechanically bonding the silicon substrate 3 and the aluminum nitride plate 4. Adhesives need to have high thermal conductivity because they need not only have reliable bonding, but also serve as heat transfer paths. In this embodiment, an epoxy adhesive containing Ag (silver) having a good thermal conductivity is used. It is desirable to control the thickness of the adhesive to be 100 μm or less.
[0019]
Reference numeral 5 denotes solder bumps for electrically connecting the silicon substrate 3 and the printed circuit board 6. Since the height of the LSI is 0.5 to 0.6 mm, it is necessary to secure the solder bump 5 of about 0.8 mm. The height of the solder bump 5 can be controlled by inserting a core such as high-temperature solder, but only a solder ball of eutectic solder may be used.
[0020]
Reference numeral 6 denotes a printed circuit board. By using the silicon substrate BGA (ball grid array) of the present invention, a printed circuit board can be mounted with a multi-pin BGA without miniaturization. Therefore, in this embodiment, a normal printed circuit board is used. be able to.
[0021]
A method for assembling a silicon substrate ball grid array having the mounting structure of the present invention will be described below. First, the aluminum nitride plate 4 and the silicon substrate 3 are bonded. The adhesive used was an Ag epoxy. Next, after LSI chip 1 is flip-chip mounted on silicon substrate 3, resin sealing is performed with underfill 7. Since both the substrate and the LSI are made of silicon and the same material, the underfill is not necessary for the original purpose, but in this embodiment, the underfill is filled for easy handling. However, the effects of the present invention described below can be obtained without filling the underfill. Finally, the solder balls are mounted on the silicon substrate 3 to complete the silicon substrate ball grid array. FIG. 1 is a diagram in which this is mounted on the printed circuit board 6.
[0022]
【The invention's effect】
Since the present invention adopts a silicon substrate and affixes a reinforcing plate, the pad pitch of the LSI is expanded to the pad pitch of the PWB on the silicon substrate and connected to the solder ball, thereby forming the silicon substrate BGA. The same materials and processes as LSI can be used. Therefore, the miniaturization of the substrate can be advanced equally to the miniaturization of the LSI pad pitch.
[0023]
In addition, there is no need to increase the number of layers, and a decrease in yield and an increase in cost due to the increase in the number of layers such as a build-up substrate and a polyimide substrate can be suppressed.
[0024]
Further, since the silicon substrate BGA uses the same material as the LSI, there is little warpage.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a mounting structure of an LSI chip according to the present invention;
FIG. 2 is a diagram showing a structure of an LSI chip.
FIG. 3 is a diagram showing a structure of a silicon substrate having an LSI chip mounting structure according to the present invention.
FIG. 4 is a diagram for explaining an example of a conventional LSI chip mounting structure;
FIG. 5 is a diagram for explaining another example of a conventional LSI chip mounting structure;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 LSI chip 2 Adhesive 3 Silicon substrate 4 Aluminum nitride board 5 Solder bump 6 Printed board 7 Underfill 8 Input / output pad 9 PWB connection pad 10, 21 Build-up wiring board 11, 20 Build-up layer 12 Core board

Claims (3)

第１の基板と、
前記第１の基板上に実装される第２の基板と、
前記第２の基板上に実装されるＬＳＩチップと、
前記第２の基板に積層され、前記ＬＳＩチップと同等の熱膨張係数を有する補強板とを含み、
前記ＬＳＩチップ及び前記第２の基板は、シリコンで形成され、
前記第２の基板は、
前記ＬＳＩチップの入出力パッドを介して前記ＬＳＩチップと接続され、
接続用パッド、及び、前記ＬＳＩチップの入出力パッドと前記接続用パッドとを接続する配線を有し、
前記接続用パッドを介して前記第１の基板に接続され、
前記配線により前記ＬＳＩチップの入出力パッドのピンのピッチが前記接続用パッドのピンのピッチまで展開されていることを特徴とするＬＳＩチップの実装構造。A first substrate;
A second substrate mounted on the first substrate;
An LSI chip mounted on the second substrate;
A reinforcing plate laminated on the second substrate and having a thermal expansion coefficient equivalent to that of the LSI chip;
The LSI chip and the second substrate are formed of silicon,
The second substrate is
Connected to the LSI chip via the input / output pads of the LSI chip;
A wiring for connecting the connection pad and the input / output pad of the LSI chip and the connection pad;
Connected to the first substrate via the connection pads;
A mounting structure of an LSI chip, wherein a pitch of an input / output pad pin of the LSI chip is expanded to a pitch of a pin of the connection pad by the wiring. 前記第２の基板は、第１の面と第２の面とを有し、
前記第１の面において、前記ＬＳＩチップの入出力パッドを介して前記ＬＳＩチップと接続されるとともに、前記第１の面に前記接続用パッドが設けられ、
前記第２の面に前記補強板が積層されていることを特徴とする請求項１に記載のＬＳＩチップの実装構造。The second substrate has a first surface and a second surface;
The first surface is connected to the LSI chip via an input / output pad of the LSI chip, and the connection pad is provided on the first surface,
2. The LSI chip mounting structure according to claim 1, wherein the reinforcing plate is laminated on the second surface. 前記補強板は窒化アルミの板であることを特徴とする請求項１又は２のいずれか一項に記載のＬＳＩチップの実装構造。The LSI chip mounting structure according to claim 1, wherein the reinforcing plate is an aluminum nitride plate.
JP16808799A 1999-06-15 1999-06-15 LSI chip mounting structure Expired - Fee Related JP3626631B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16808799A JP3626631B2 (en) 1999-06-15 1999-06-15 LSI chip mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16808799A JP3626631B2 (en) 1999-06-15 1999-06-15 LSI chip mounting structure

Publications (2)

Publication Number Publication Date
JP2000357709A JP2000357709A (en) 2000-12-26
JP3626631B2 true JP3626631B2 (en) 2005-03-09

Family

ID=15861612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16808799A Expired - Fee Related JP3626631B2 (en) 1999-06-15 1999-06-15 LSI chip mounting structure

Country Status (1)

Country Link
JP (1) JP3626631B2 (en)

Also Published As

Publication number Publication date
JP2000357709A (en) 2000-12-26

Similar Documents

Publication Publication Date Title
TWI476888B (en) Package substrate having embedded via hole medium layer and fabrication method thereof
KR100856609B1 (en) A semiconductor device and a method of manufacturing the same
US6555917B1 (en) Semiconductor package having stacked semiconductor chips and method of making the same
KR101767108B1 (en) Semiconductor packages having hybrid substrates and methods for fabricating the same
JP5330184B2 (en) Electronic component equipment
EP1134804B1 (en) Thermally enhanced semiconductor carrier
US20090166873A1 (en) Inter-connecting structure for semiconductor device package and method of the same
US20080157327A1 (en) Package on package structure for semiconductor devices and method of the same
TW200931628A (en) Stacking die package structure for semiconductor devices and method of the same
JP2009239256A (en) Semiconductor device and method of fabricating same
KR20010062512A (en) Multi-flip-chip semiconductor assembly
JP2008016519A (en) Semiconductor device and its manufacturing method
CN101252125A (en) Multi-chips package with reduced structure and method for forming the same
US20030030968A1 (en) Microelectronic assembly with stiffening member
TWI694566B (en) Semiconductor package carrier board and manufacturing method thereof and electronic package
CN113035786A (en) Semiconductor structure and manufacturing method thereof
TWI391084B (en) Pcb structure having heat-dissipating member
JPWO2003012863A1 (en) Semiconductor device and manufacturing method thereof
CN116895636B (en) Package substrate and method for fabricating the same
TWI826339B (en) 2.5d packaging structure and preparation method
TW200536074A (en) Chip package structure and process for fabricating the same
CN116053251A (en) Packaging structure, chip, electronic equipment and chip packaging method
KR20180036947A (en) Interconnect structure for semiconductor package and method of fabricating the interconnect structure
JP3626631B2 (en) LSI chip mounting structure
TW200531235A (en) Multi-chip package structure

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20030611

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040921

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041203

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees