JP3603725B2 - Semiconductor device, method of manufacturing the same, and circuit board - Google Patents

Semiconductor device, method of manufacturing the same, and circuit board Download PDF

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JP3603725B2
JP3603725B2 JP2000057624A JP2000057624A JP3603725B2 JP 3603725 B2 JP3603725 B2 JP 3603725B2 JP 2000057624 A JP2000057624 A JP 2000057624A JP 2000057624 A JP2000057624 A JP 2000057624A JP 3603725 B2 JP3603725 B2 JP 3603725B2
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circuit board
thermal expansion
thin layer
semiconductor device
layer
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JP2001244379A (en
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俊史 佐野
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、ボール・グリッド・アレイ（ＢＧＡ）等に使用して好適な半導体装置及びその製造方法並びに回路基板に関する。
【０００２】
【従来の技術】
近年、電子機器の高速・高集積化によって配線経路長を可能な限り短縮することが要求されており、これに伴いベアチップからなる半導体素子をそのまま回路基板上に半田ボールによって直接実装（ベアチップ実装）してなる半導体装置が増加してきている。
一般に、この種の半導体装置は、回路の高集積化に伴い、チップサイズが大型化（□１０ｍｍ以上）する傾向がある。
【０００３】
また、この種の半導体装置は、回路の高速化に伴い、その発熱量が数十Ｗから百Ｗを超えるところまで増加しており、このためベアチップ上にヒートシンク等の放熱用部品が取り付けられている。
【０００４】
このような半導体装置においては、チップサイズが大型化すると、ベース部材が有機系材料からなる回路基板（熱膨張率１５×１０−６／℃）とシリコンチップ（熱膨張率４．２×１０−６／℃）あるいはガリウム−砒素（熱膨張率６．５×１０−６／℃）からなる半導体素子との間の熱膨張率差（１５×１０−６／℃程度）によって、半田接合時に２００℃程度まで加熱された半導体素子に実際の使用温度領域（常温〜８０℃程度）で反りが発生してしまい、このため半導体素子に応力が加わったままの使用となるばかりか、半導体素子に対する放熱用部品の接触面積が小さくなり、信頼性および放熱性が低下する。
【０００５】
この場合、品質上の信頼面で問題が生じない程度にベアチップの変形と応力を低減することは、ベアチップが小型（□１０ｍｍ程度）であれば、ベアチップと回路基板との間に介在する半田ボールが変形吸収して可能であるが、ベアチップが大型化すると、接続ピンの増加による半田ボールの小径化によって困難なものとなる。
【０００６】
このため、大型のベアチップ実装には、図４に示すようにベース部材の材料として熱膨張率がシリコン（Ｓｉ）の熱膨張率に近いセラミック等の無機材料を使用したもの（特開平１０−１６３３８６号公報）、あるいは図５に示すように半田ボールによる変形吸収層を二段にしたインターポーザ構造をもつもの（特開平１０−２４７６６６号公報）が採用されていた。
【０００７】
図４は従来における半導体装置（１）の回路基板に反りが発生している状態を示す図であり、同図において、符号４１で示す半導体装置は、プリント配線基板４２，ベアチップ４３およびヒートシンク４４を備えている。
なお、プリント配線基板４２とベアチップ４３との間には半田ボール４５が介在し、ベアチップ４３とヒートシンク４４との間にはコンパウンドやラバーシート等の伝熱部材４６が介在している。また、同図中、符号４３ａはベアチップ４３の放熱面を示す。
【０００８】
図５は同じく従来における半導体装置（２）の回路基板に反りが発生している状態を示す図であり、同図において、符号５１で示す半導体装置は、プリント配線基板５２，インターポーザ５３，ベアチップ５４およびヒートシンク５５を備えている。
なお、プリント配線基板５２とインターポーザ５３との間およびインターポーザ５３とベアチップ５４との間には半導体装置（１）と同様に半田ボール５６が介在し、ベアチップ５４とヒートシンク５５との間にはコンパウンドやラバーシート等の伝熱部材５７が介在している。また、同図中、符号５４ａはベアチップ５４の放熱面を示す。
【０００９】
【発明が解決しようとする課題】
しかるに、前者（特開平１０−１６３３８６号公報）にあっては、回路基板のベース部材が無機系材料によって形成されているため、有機系材料からなるベース部材と比べて材料選択上の自由度が低くなり、製造コストが嵩むという問題があった。
一方、後者（特開平１０−２４７６６６号公報）にあっては、回路基板上にインターポーザを介して半導体素子が実装されているため、部品点数が嵩み、前者と同様にコスト高になるという問題があった。
【００１０】
また、両者にあっては、コンパウンドやラバーシート等の伝熱部材を用いることにより、回路基板（ベアチップ）の反り変形を吸収するとともに、伝熱面積を拡大することが行われているが、これら各機能を発揮するに十分な寸法に伝熱部材の厚さを設定することを困難なものにしていた。すなわち、伝熱部材の厚さを小さくし過ぎると、ベアチップの反り変形を吸収することができず、また大きくし過ぎると、伝熱部材の熱伝導率がヒートシンク（アルミニウム製）の熱伝導率と比較して小さい（ヒートシンクの１／１００程度）ため、ヒートシンクとベアチップ間の熱伝達が悪くなるからである。この結果、装置設計時に伝熱部材の厚さを設定する作業に細心の注意を払う必要が生じ、装置設計を煩雑にするという問題もあった。
【００１１】
なお、特開平７−２９７５６０号公報にも、「多層プリント配線基板およびその実装構造体」として先行技術が開示されている。
しかし、同公報記載の技術は、「多層プリント配線基板の層間に、層間の剪断ひずみを吸収する吸収層を設け、かつ、各層の面内方向の熱膨張係数を積層方向に対し段階的に変化させた」ものであり、「剪断歪による反りや層間剥離を吸収する」点についての開示はあるものの、「コスト高になる、装置設計を煩雑にする」という従来の問題点を解決するための手段についての開示はない。
【００１２】
本発明はこのような事情に鑑みてなされたもので、ベース部材を有機系材料とする多層基板の層間に低熱膨張率材料からなる薄層を設け、回路基板における素子実装面に平行な方向の複合熱膨張率を所定の範囲に設定することにより、コストの低廉化を図ることができるとともに、装置設計を簡単に行うことができる半導体装置及びその製造方法並びに回路基板の提供を目的とする。
【００１３】
【課題を解決するための手段】
前記目的を達成するために、本発明の請求項１記載の半導体装置は、回路基板上に半田を介して実装され、ベアチップからなる半導体素子を備えた半導体装置において、前記回路基板を、ベース部材を有機系材料とする多層基板によって形成し、この多層基板の層間に低熱膨張率の単一の金属材料からなる薄層を設け、この薄層を、層厚方向中央部に関して対称な位置に位置する複数の金属層で形成するとともに、この薄層を含む回路基板における素子実装面に平行な方向の複合熱膨張率を、４×１０-6／℃〜７×１０-6／℃の範囲とした構成としてある。
したがって、回路基板内に薄層を含み、回路基板における素子実装面に平行な方向の複合熱膨張率がベアチップからなる半導体素子の熱膨張率に近似する。
【００１４】
また、薄層を単一の金属材料層としてあるので、回路基板内の熱膨張率差による基板反り変形が防止される。
【００１５】
請求項２記載の発明は、請求項１記載の半導体装置において、前記薄層が、金属箔層からなる構成としてある。したがって、回路基板内に金属箔層を含み、回路基板における素子実装面に平行な方向の複合熱膨張率がベアチップからなる半導体素子の熱膨張率に近似する。
【００１６】
請求項３記載の発明は、請求項１記載の半導体装置において、薄層が金属メッシュ層からなる構成としてある。したがって、回路基板内に金属メッシュ層を含み、回路基板における素子実装面に平行な方向の複合熱膨張率がベアチップからなる半導体素子の熱膨張率に近似する。
【００１７】
請求項４記載の発明は、ベース部材が有機系材料からなる回路基板を多層基板によって形成し、次に、この多層基板上にベアチップからなる半導体素子を実装することにより、半導体装置を製造する方法であって、前記回路基板を形成するにあたり、層間に低熱膨張率の単一の金属材料からなる薄層を設け、この薄層を、層厚方向中央部に関して対称な位置に位置する複数の金属層で形成するとともに、この薄層を含む回路基板における素子実装面に平行な方向の複合熱膨張率を、４×１０ -6 ／℃〜７×１０ -6 ／℃の範囲に設定する方法としてある。したがって、薄層を含み、回路基板における素子実装面に平行な方向の複合熱膨張率がベアチップからなる半導体素子の熱膨張率に近似する回路基板を得る。
【００１８】
請求項５記載の発明は、ベアチップからなる半導体素子を、半田を介して実装する回路基板において、ベース部材を有機系材料とする多層基板によって形成し、この多層基板の層間に低熱膨張率の単一の金属材料からなる薄層を設け、この薄層を、層厚方向中央部に関して対称な位置に位置する複数の金属層で形成するとともに、この薄層を含む前記回路基板における素子実装面に平行な方向の複合熱膨張率を、４×１０ -6 ／℃〜７×１０ -6 ／℃の範囲とした構成としてある。
【００１９】
【発明の実施の形態】
以下、本発明の実施形態につき、図面を参照して説明する。
図１は本発明の第一実施形態に係る半導体装置を示す断面図である。
同図において、符号１で示す半導体装置は、回路基板２および半導体素子３を備え、電子機器筐体（図示せず）内に収納される。
【００２０】
回路基板２は、二つのプリント配線板２ａ，２ｂを積層してなる多層基板によって形成されている。回路基板２の層間すなわち両プリント配線板２ａ，２ｂ間には、低熱膨張率材料からなる薄層４が配設されている。回路基板２の複合熱膨張率（プリント配線板２ａ，２ｂおよび薄層４による素子実装面ａに平行な方向の複合熱膨張率）は、半導体素子３の素材および薄層４の層厚に合わせて、４×１０−６／℃〜７×１０−６／℃の範囲に設定されている。
【００２１】
例えば、薄層４の層厚を回路基板２の板厚の２２％に相当する寸法に設定した場合には、回路基板２の複合熱膨張率が４×１０−６／℃となる。また、薄層４の層厚を回路基板２の板厚の１１％に相当する寸法に設定した場合には、回路基板２の複合熱膨張率が７×１０−６／℃となる。
この場合、半導体素子３にはＳｉチップ（熱膨張率４．２×１０−６／℃）あるいはＧａ−Ａｓチップ（熱膨張率６．５×１０−６／℃）が用いられ、薄層４にはインバール（熱膨張率０．１３×１０−６／℃，弾性弾性係数１４４０００ＭＰａ）が用いられる。また、回路基板２におけるプリント配線板２ａ，２ｂの熱膨張率および弾性係数をそれぞれ１５×１０−６／℃および１４４００とする。
【００２２】
これにより、回路基板２における実装面ａに平行な方向の複合熱膨張率が半導体素子３の熱膨張率に近似し、半導体素子３における素子実装面ａと平行な方向の反り変形が防止される。
【００２３】
なお、回路基板２の複合熱膨張率を４×１０−６／℃〜７×１０−６／℃の範囲外に設定すると、この熱膨張率と半導体素子３の熱膨張率との差が大きくなり、半導体素子３の実装後に回路基板２に反り変形が生じる。すなわち、半導体素子３の実装後における回路基板２には、複合熱膨張率が４×１０−６／℃より小さくなると、半導体素子３の表面を凹部とするような反り変形が、また複合熱膨張率が７×１０−６／℃より大きくなると、半導体素子３の表面を凸部とするような反り変形が生じる。
【００２４】
各プリント配線板２ａ，２ｂは、スルーホール（貫通ビアホール）を有し、例えばガラス織布にエポキシ樹脂を含浸させてなるベース部材（有機系材料からなるコア部材）およびこのベース部材の表裏両面に形成してなる配線パターン（銅箔，銅めっき層）によって形成されている。そして、各プリント配線板２ａ，２ｂの熱膨張率および弾性係数は、それぞれ１５×１０−６／℃と１４４００ＭＰａに設定されている。
なお、各プリント配線板２ａ，２ｂの熱膨張率は、ガラス織布，エポキシ樹脂および銅による複合熱膨張率となる。
【００２５】
薄層４は、回路基板２の層厚方向中央部に配置されている。これにより、回路基板２内（層厚方向）の熱膨張率差による反り変形が防止される。薄層４は、全体が例えばインバール等からなる単一の金属層あるいはメッシュ層によって形成されており、熱膨張率および弾性係数がそれぞれ０．１３×１０−６／℃と１４４０００ＭＰａに設定されている。
なお、回路基板２の層構成を工夫すれば、層厚方向中央部に関して対称な位置に金属層を配置することなく、回路基板２内の熱膨張率による反り変形が防止される。
【００２６】
半導体素子３は、シリコン（熱膨張率４．２×１０−６／℃）あるいはガリウム−砒素（熱膨張率６．５×１０−６／℃）を素材とするベアチップからなり、回路基板２の表面（素子実装面）上に半田ボール５および樹脂６によって実装されている。これにより、半導体素子３が、回路基板２に対して電気的かつ機械的に接続される。半導体素子３の反実装側面には、放熱用部品としてのヒートシンク７が伝熱部材としてのコンパウンド８を介して取り付けられている。これにより、回路基板２からの発生熱が半田ボール５，樹脂６，半導体素子２およびコンパウンド８を経て、また半導体素子２からの発生熱がコンパウンド８を経てヒートシンク７に到達すると、このヒートシンク７から放散される。
【００２７】
なお、半田ボール５は、半導体素子３の裏面においてチップ実装領域を除きマトリックス状に配列される多数の半田ボールからなり、回路基板２の表面上にリフローソルダリング技術を用いて溶着されている。
【００２８】
次に、本実施形態における半導体装置の製造方法につき、図１および図２（ａ），（ｂ）を用いて説明する。
図２（ａ）および（ｂ）は本発明の第一実施形態に係る本導体装置の製造方法を説明するために示す断面図である。
すなわち、本実施形態における半導体装置の製造は、「回路基板の形成」および「半導体素子の実装」の工程を順次経て行われる。
【００２９】
「回路基板の形成」
先ず、図１に示すプリント配線板２ａ，２ｂのベース部材となるガラスエポキシ材の表裏両面に銅箔を接着したり、あるいは銅めっき処理を施すことにより配線導体層（図示せず）を形成する。なお、ガラスエポキシ材の形成は、ガラス織布にエポキシ樹脂に含浸させることにより行われる。
【００３０】
次に、配線導体層に露光，現像およびエッチングの各処理を順次施すことにより、回路パターン（図示せず）を有するプリント配線板（ガラスエポキシ銅張積層板）２ａ，２ｂを形成する。なお、各プリント配線板２ａ，２ｂは、板厚が同一の寸法に設定される。
【００３１】
そして、図２（ａ）に示すように、両プリント配線板２ａ，２ｂ間に接着剤を介在させて加圧することにより積層体Ａを形成する。この積層体Ａを形成するにあたり、両プリント配線板２ａ，２ｂ間に薄層４を形成する。
この後、積層体Ａにドリル加工を施して複数の貫通孔（図示せず）を設け、これら貫通孔内に金属めっき処理を施すことによりスルーホール（図示せず）を有する回路基板２を形成する。
【００３２】
「半導体素子の実装」
先ず、回路基板２上に半田ボール５が基板表面に当接した状態で半導体素子３を搭載する。
次に、図２（ｂ）に示すように、半導体素子搭載の回路基板２をリフロー内に収容して回路基板２の表面上に半導体素子３を装着した後、この半導体素子３と回路基板２との間に樹脂６を注入して固化させる。
そして、半導体素子３の表面にコンパウンド８を介してヒートシンク７を接合する。
【００３３】
したがって、本実施形態においては、回路基板２における素子実装面ａに平行な方向の複合熱膨張率が半導体素子３の熱膨張率に近似し、回路基板２における素子実装面ａと平行な方向の反り変形が防止されるから、半導体素子３とヒートシンク７との間にコンパウンド８等の伝熱部材を介在させる場合に半導体素子３からヒートシンク７への熱伝導性のみを考慮すればよく（コンパウンド８の厚さを十分に小さくする）、装置設計時に従来のように伝熱部材の厚さを設定する作業に細心の注意を払う必要がない。
【００３４】
また、本実施形態においては、回路基板２のベース部材が有機系材料によって形成されているため、無機系材料からなるベース部材と比べて材料選択上の自由度を高めることができる。
さらに、本実施形態においては、回路基板２上にインターポーザを介して半導体素子３を実装するものではないから、部品点数を削減することができる。
【００３５】
なお、本実施形態においては、貫通ビアホール付きのプリント配線板を備えた半導体装置である場合について説明したが、本発明はこれに限定されず、ブラインドビアホール付きのビルドアップ基板を備えた半導体装置であっても実施形態と同様の効果を奏する。
【００３６】
また、本実施形態においては、回路基板内に単一の薄層を設ける場合について説明したが、本発明はこれに限定されず、第二実施形態として図３に示すように回路基板２内（プリント配線板２ａ〜２ｃ）に複数の薄層３１，３２を設けても差し支えない。この場合、回路基板２内の熱膨張率差による反り変形を防止するためには、回路基板２の層厚方向中央部に関して対称な位置に薄層３１，３２を配置することが望ましい。
【００３７】
【発明の効果】
以上説明したように本発明によれば、回路基板における素子実装面に平行な方向の複合熱膨張率が半導体素子の熱膨張率に近似し、回路基板における素子実装面と平行な方向の反り変形が防止されるから、半導体素子とヒートシンクとの間にコンパウンド等の伝熱部材を介在させる場合に、装置設計時に従来のように伝熱部材の厚さを設定する作業に細心の注意を払うことを必要とせず、装置設計を簡単に行うことができる。
【００３８】
また、回路基板のベース部材が有機系材料によって形成されていることおよびインターポーザが不要であることは、それぞれ材料選択上の自由度を高めることおよび部品点数を削減することが可能となるから、コストの低廉化を図ることができる。
【図面の簡単な説明】
【図１】本発明の第一実施形態に係る半導体装置を示す断面図である。
【図２】（ａ）および（ｂ）は本発明の第一実施形態に係る半導体装置の製造方法を説明するために示す断面図である。
【図３】本発明の第二実施形態に係る半導体装置を示す断面図である。
【図４】従来の半導体装置（１）を示す断面図である。
【図５】従来の半導体装置（２）を示す断面図である。
【符号の説明】
１ 半導体装置
２ 回路基板
２ａ，２ｂ プリント配線板
３ 半導体素子
４ 薄層
５ 半田ボール
６ 樹脂
７ ヒートシンク
８ コンパウンド
ａ 素子実装面[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device suitable for use in a ball grid array (BGA) and the like, a method for manufacturing the same, and a circuit board .
[0002]
[Prior art]
In recent years, it has been required to shorten the wiring path length as much as possible due to the high speed and high integration of electronic devices. With this, semiconductor elements composed of bare chips are directly mounted on circuit boards as they are by solder balls (bare chip mounting). Semiconductor devices are increasing.
In general, this type of semiconductor device tends to have a larger chip size (10 mm or more) as the degree of integration of circuits increases.
[0003]
In addition, with this type of semiconductor device, the heat generation has increased from several tens of watts to more than one hundred watts with the increase in the speed of the circuit. For this reason, heat-dissipating components such as heat sinks have been mounted on bare chips. I have.
[0004]
In such a semiconductor device, the chip size is enlarged, the base member is a circuit board (thermal expansion coefficient 15 × 10 -6 / ℃) made of an organic material and silicon chips (thermal expansion coefficient 4.2 × 10 - 6 / ° C.) or a semiconductor element made of gallium-arsenic (coefficient of thermal expansion 6.5 × 10 −6 / ° C.) (about 15 × 10 −6 / ° C.). The semiconductor element heated to about ° C. is warped in an actual operating temperature range (about room temperature to about 80 ° C.), so that the semiconductor element is not only used while the stress is applied to the semiconductor element but also radiated to the semiconductor element. The contact area of the parts for use is reduced, and the reliability and heat dissipation are reduced.
[0005]
In this case, reducing the deformation and stress of the bare chip to such an extent that there is no problem in terms of quality reliability can be achieved by using a solder ball interposed between the bare chip and the circuit board if the bare chip is small (about 10 mm). However, when the size of the bare chip is increased, it becomes difficult to reduce the diameter of the solder ball by increasing the number of connection pins.
[0006]
For this reason, for mounting a large bare chip, as shown in FIG. 4, an inorganic material such as ceramic having a coefficient of thermal expansion close to that of silicon (Si) is used as a material of the base member (Japanese Patent Laid-Open No. 10-163386). Japanese Patent Application Laid-Open No. Hei 10-247666), or a device having an interposer structure in which a deformation absorbing layer made of solder balls is provided in two stages as shown in FIG.
[0007]
FIG. 4 is a view showing a state in which a circuit board of a conventional semiconductor device (1) is warped. In the same figure, a semiconductor device indicated by reference numeral 41 includes a printed wiring board 42, a bare chip 43, and a heat sink 44. Have.
A solder ball 45 is interposed between the printed wiring board 42 and the bare chip 43, and a heat transfer member 46 such as a compound or a rubber sheet is interposed between the bare chip 43 and the heat sink 44. In the same figure, reference numeral 43a indicates a heat dissipation surface of the bare chip 43.
[0008]
FIG. 5 is a view showing a state in which the circuit board of the conventional semiconductor device (2) is warped. In FIG. 5, the semiconductor device indicated by reference numeral 51 is a printed wiring board 52, an interposer 53, and a bare chip 54. And a heat sink 55.
Note that solder balls 56 are interposed between the printed wiring board 52 and the interposer 53 and between the interposer 53 and the bare chip 54, similarly to the semiconductor device (1). A heat transfer member 57 such as a rubber sheet is interposed. Further, in the figure, reference numeral 54a indicates a heat dissipation surface of the bare chip 54.
[0009]
[Problems to be solved by the invention]
However, in the former (Japanese Patent Application Laid-Open No. 10-163386), since the base member of the circuit board is formed of an inorganic material, the degree of freedom in material selection is lower than that of a base member made of an organic material. However, there has been a problem that the manufacturing cost increases.
On the other hand, the latter (Japanese Patent Laid-Open No. Hei 10-247666) has a problem that the number of components is increased because the semiconductor element is mounted on the circuit board via the interposer, and the cost is increased similarly to the former. was there.
[0010]
In both cases, by using a heat transfer member such as a compound or a rubber sheet, the warpage of the circuit board (bare chip) is absorbed and the heat transfer area is enlarged. It has been difficult to set the thickness of the heat transfer member to a size sufficient to exhibit each function. That is, if the thickness of the heat transfer member is too small, the warp deformation of the bare chip cannot be absorbed, and if it is too large, the heat conductivity of the heat transfer member will be lower than that of the heat sink (aluminum). This is because heat transfer between the heat sink and the bare chip deteriorates because the heat sink is small (about 1/100 of the heat sink). As a result, it is necessary to pay close attention to the work of setting the thickness of the heat transfer member at the time of designing the device, and there is a problem that the device design becomes complicated.
[0011]
Japanese Patent Application Laid-Open No. 7-297560 also discloses a prior art as "a multilayer printed wiring board and its mounting structure".
However, the technology described in the publication discloses that "an absorbent layer is provided between layers of a multilayer printed wiring board to absorb shear strain between layers, and the coefficient of thermal expansion of each layer in the in-plane direction changes stepwise in the laminating direction. Although there is disclosure about the point of "absorbing warpage and delamination due to shear strain", it is to solve the conventional problem of "increase in cost, complicating device design" There is no disclosure of the means.
[0012]
The present invention has been made in view of such circumstances, and provides a thin layer made of a low coefficient of thermal expansion material between layers of a multi-layer substrate using an organic material as a base member, in a direction parallel to the element mounting surface of the circuit board. An object of the present invention is to provide a semiconductor device, a method for manufacturing the same, and a circuit board , which can reduce the cost and simplify the device design by setting the composite thermal expansion coefficient within a predetermined range.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to claim 1 of the present invention is provided with a semiconductor element comprising a bare chip mounted on a circuit board via solder , wherein the circuit board is provided with a base member. Is formed by a multi-layer substrate made of an organic material, and a thin layer made of a single metal material having a low coefficient of thermal expansion is provided between the layers of the multi-layer substrate, and the thin layer is positioned at a position symmetrical with respect to the center in the layer thickness direction. And a composite coefficient of thermal expansion in a direction parallel to the element mounting surface of the circuit board including the thin layer in a range of 4 × 10 −6 / ° C. to 7 × 10 −6 / ° C. There is a configuration.
Therefore, the composite thermal expansion coefficient in the direction parallel to the element mounting surface of the circuit board, including the thin layer in the circuit board, is close to the thermal expansion coefficient of the semiconductor element formed of the bare chip.
[0014]
Further, since the thin layer is formed as a single metal material layer, substrate warpage due to a difference in thermal expansion coefficient in the circuit board is prevented.
[0015]
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the thin layer includes a metal foil layer. Therefore, the composite thermal expansion coefficient in the direction parallel to the element mounting surface of the circuit board, including the metal foil layer in the circuit board, is close to the thermal expansion coefficient of the semiconductor element formed of the bare chip.
[0016]
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the thin layer includes a metal mesh layer. Therefore, the circuit board includes a metal mesh layer, and the composite coefficient of thermal expansion in the direction parallel to the element mounting surface of the circuit board is close to the coefficient of thermal expansion of a semiconductor element formed of a bare chip.
[0017]
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device by forming a circuit board whose base member is made of an organic material by a multilayer board, and then mounting a semiconductor element made of a bare chip on the multilayer board. In forming the circuit board, a thin layer made of a single metal material having a low coefficient of thermal expansion is provided between the layers, and the thin layer is formed of a plurality of metals positioned symmetrically with respect to the center in the layer thickness direction. A method of setting the composite coefficient of thermal expansion in the direction parallel to the element mounting surface of the circuit board including the thin layer in the range of 4 × 10 −6 / ° C. to 7 × 10 −6 / ° C. is there. Therefore, a circuit board including a thin layer and having a composite coefficient of thermal expansion in a direction parallel to the element mounting surface of the circuit board which is close to the coefficient of thermal expansion of a semiconductor element formed of a bare chip is obtained.
[0018]
According to a fifth aspect of the present invention, in a circuit board on which a semiconductor element formed of a bare chip is mounted via solder, the base member is formed of a multilayer board having an organic material, and a single layer having a low coefficient of thermal expansion is formed between layers of the multilayer board. A thin layer made of one metal material is provided, and the thin layer is formed of a plurality of metal layers located symmetrically with respect to the center in the layer thickness direction, and on the element mounting surface of the circuit board including the thin layer. The composite thermal expansion coefficient in the parallel direction is in the range of 4 × 10 −6 / ° C. to 7 × 10 −6 / ° C.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1, a semiconductor device denoted by reference numeral 1 includes a circuit board 2 and a semiconductor element 3 and is housed in an electronic device housing (not shown).
[0020]
The circuit board 2 is formed by a multilayer board formed by laminating two printed wiring boards 2a and 2b. A thin layer 4 made of a material having a low coefficient of thermal expansion is disposed between the circuit boards 2, that is, between the printed wiring boards 2 a and 2 b. The composite thermal expansion coefficient of the circuit board 2 (composite thermal expansion coefficient of the printed wiring boards 2a, 2b and the thin layer 4 in the direction parallel to the element mounting surface a) is adjusted according to the material of the semiconductor element 3 and the thickness of the thin layer 4. Therefore, it is set in the range of 4 × 10 −6 / ° C. to 7 × 10 −6 / ° C.
[0021]
For example, when the thickness of the thin layer 4 is set to a size corresponding to 22% of the board thickness of the circuit board 2, the composite thermal expansion coefficient of the circuit board 2 is 4 × 10 −6 / ° C. When the thickness of the thin layer 4 is set to a size corresponding to 11% of the thickness of the circuit board 2, the composite thermal expansion coefficient of the circuit board 2 is 7 × 10 −6 / ° C.
In this case, a Si chip (a coefficient of thermal expansion of 4.2 × 10 −6 / ° C.) or a Ga-As chip (a coefficient of thermal expansion of 6.5 × 10 −6 / ° C.) is used as the semiconductor element 3, and the thin layer 4 is used. Invar (coefficient of thermal expansion 0.13 × 10 −6 / ° C., elastic modulus 144000 MPa) is used. Further, the thermal expansion coefficients and the elastic coefficients of the printed wiring boards 2a and 2b in the circuit board 2 are set to 15 × 10 −6 / ° C. and 14400, respectively.
[0022]
As a result, the composite thermal expansion coefficient of the circuit board 2 in the direction parallel to the mounting surface a approximates the thermal expansion coefficient of the semiconductor element 3, and warpage of the semiconductor element 3 in the direction parallel to the element mounting surface a is prevented. .
[0023]
If the composite coefficient of thermal expansion of the circuit board 2 is set outside the range of 4 × 10 −6 / ° C. to 7 × 10 −6 / ° C., the difference between this coefficient of thermal expansion and the coefficient of thermal expansion of the semiconductor element 3 increases. Therefore, the circuit board 2 is warped after the semiconductor element 3 is mounted. That is, when the composite thermal expansion coefficient is smaller than 4 × 10 −6 / ° C., the circuit board 2 after the mounting of the semiconductor element 3 is warped to make the surface of the semiconductor element 3 a concave portion, and the composite thermal expansion. If the rate is higher than 7 × 10 −6 / ° C., warpage deformation occurs such that the surface of the semiconductor element 3 has a convex portion.
[0024]
Each printed wiring board 2a, 2b has a through hole (through via hole), for example, a base member (a core member made of an organic material) obtained by impregnating a glass woven fabric with an epoxy resin, and both front and back surfaces of the base member. It is formed by the formed wiring pattern (copper foil, copper plating layer). The coefficients of thermal expansion and elastic coefficients of the printed wiring boards 2a and 2b are set to 15 × 10 −6 / ° C. and 14400 MPa, respectively.
The thermal expansion coefficient of each printed wiring board 2a, 2b is a composite thermal expansion coefficient of glass woven fabric, epoxy resin and copper.
[0025]
The thin layer 4 is arranged at the center of the circuit board 2 in the layer thickness direction. This prevents warpage deformation due to a difference in thermal expansion coefficient in the circuit board 2 (layer thickness direction). The thin layer 4 is formed entirely of a single metal layer or a mesh layer made of, for example, Invar, and has a coefficient of thermal expansion and an elastic coefficient of 0.13 × 10 −6 / ° C. and 144000 MPa, respectively. .
If the layer structure of the circuit board 2 is devised, warpage deformation due to the coefficient of thermal expansion in the circuit board 2 can be prevented without disposing the metal layer at a position symmetrical with respect to the center in the layer thickness direction.
[0026]
The semiconductor element 3 is a bare chip made of silicon (coefficient of thermal expansion 4.2 × 10 −6 / ° C.) or gallium-arsenic (coefficient of thermal expansion 6.5 × 10 −6 / ° C.). It is mounted on the surface (element mounting surface) with solder balls 5 and resin 6. Thus, the semiconductor element 3 is electrically and mechanically connected to the circuit board 2. A heat sink 7 as a heat-dissipating component is attached to the non-mounting side surface of the semiconductor element 3 via a compound 8 as a heat transfer member. Accordingly, when the heat generated from the circuit board 2 reaches the heat sink 7 via the solder balls 5, the resin 6, the semiconductor element 2 and the compound 8, and the heat generated from the semiconductor element 2 reaches the heat sink 7 via the compound 8, Dissipated.
[0027]
The solder balls 5 are composed of a large number of solder balls arranged in a matrix on the back surface of the semiconductor element 3 except for a chip mounting area, and are welded to the surface of the circuit board 2 by using a reflow soldering technique.
[0028]
Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 1 and 2A and 2B.
2A and 2B are cross-sectional views illustrating a method for manufacturing the conductor device according to the first embodiment of the present invention.
That is, the manufacture of the semiconductor device according to the present embodiment is performed sequentially through the steps of “forming a circuit board” and “mounting a semiconductor element”.
[0029]
`` Formation of circuit board ''
First, a wiring conductor layer (not shown) is formed by bonding copper foil to both front and back surfaces of a glass epoxy material serving as a base member of the printed wiring boards 2a and 2b shown in FIG. . The glass epoxy material is formed by impregnating a glass woven fabric with an epoxy resin.
[0030]
Next, exposure, development, and etching are sequentially performed on the wiring conductor layer to form printed wiring boards (glass epoxy copper clad laminates) 2a and 2b having a circuit pattern (not shown). The thickness of each of the printed wiring boards 2a and 2b is set to the same size.
[0031]
Then, as shown in FIG. 2A, a laminate A is formed by applying an adhesive between the two printed wiring boards 2a and 2b and applying pressure. In forming the laminate A, a thin layer 4 is formed between the printed wiring boards 2a and 2b.
Thereafter, a plurality of through-holes (not shown) are formed by drilling the laminate A, and a metal plating process is performed in these through-holes to form a circuit board 2 having through-holes (not shown). I do.
[0032]
"Mounting of semiconductor elements"
First, the semiconductor element 3 is mounted on the circuit board 2 with the solder balls 5 in contact with the surface of the board.
Next, as shown in FIG. 2B, after the circuit board 2 on which the semiconductor element is mounted is housed in a reflow and the semiconductor element 3 is mounted on the surface of the circuit board 2, the semiconductor element 3 and the circuit board 2 are mounted. The resin 6 is injected and solidified.
Then, the heat sink 7 is joined to the surface of the semiconductor element 3 via the compound 8.
[0033]
Therefore, in the present embodiment, the composite thermal expansion coefficient of the circuit board 2 in the direction parallel to the element mounting surface a approximates the thermal expansion coefficient of the semiconductor element 3, and the composite thermal expansion coefficient of the circuit board 2 in the direction parallel to the element mounting surface a Since the warp deformation is prevented, when a heat transfer member such as the compound 8 is interposed between the semiconductor element 3 and the heat sink 7, only the thermal conductivity from the semiconductor element 3 to the heat sink 7 needs to be considered (compound 8 The thickness of the heat transfer member is not required to be as careful as in the prior art when designing the apparatus.
[0034]
Further, in the present embodiment, since the base member of the circuit board 2 is formed of an organic material, the degree of freedom in material selection can be increased as compared with a base member made of an inorganic material.
Furthermore, in this embodiment, since the semiconductor element 3 is not mounted on the circuit board 2 via the interposer, the number of components can be reduced.
[0035]
Note that, in the present embodiment, a case has been described in which the semiconductor device is provided with a printed wiring board having through via holes, but the present invention is not limited to this. Even in this case, the same effects as in the embodiment can be obtained.
[0036]
Further, in the present embodiment, the case where a single thin layer is provided in the circuit board has been described, but the present invention is not limited to this, and as shown in FIG. A plurality of thin layers 31, 32 may be provided on the printed wiring boards 2a to 2c). In this case, in order to prevent warpage due to a difference in the coefficient of thermal expansion in the circuit board 2, it is desirable to dispose the thin layers 31 and 32 at symmetrical positions with respect to the center in the layer thickness direction of the circuit board 2.
[0037]
【The invention's effect】
As described above, according to the present invention, the composite thermal expansion coefficient in the direction parallel to the element mounting surface on the circuit board approximates the thermal expansion coefficient of the semiconductor element, and the warpage deformation in the direction parallel to the element mounting surface on the circuit board. Therefore, when interposing a heat transfer member such as a compound between the semiconductor element and the heat sink, pay close attention to the work of setting the thickness of the heat transfer member as in the past when designing the device. The device design can be easily performed without the need for a device.
[0038]
In addition, the fact that the base member of the circuit board is formed of an organic material and that no interposer is required can increase the degree of freedom in material selection and reduce the number of parts, thereby reducing costs. Can be reduced.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A and 2B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 3 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a sectional view showing a conventional semiconductor device (1).
FIG. 5 is a sectional view showing a conventional semiconductor device (2).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Circuit board 2a, 2b Printed wiring board 3 Semiconductor element 4 Thin layer 5 Solder ball 6 Resin 7 Heat sink 8 Compound a Element mounting surface

Claims (5)

回路基板上に半田を介して実装され、ベアチップからなる半導体素子を備えた半導体装置において、
前記回路基板を、ベース部材を有機系材料とする多層基板によって形成し、この多層基板の層間に低熱膨張率の単一の金属材料からなる薄層を設け、
この薄層を、層厚方向中央部に関して対称な位置に位置する複数の金属層で形成するとともに、
この薄層を含む前記回路基板における素子実装面に平行な方向の複合熱膨張率を、４×１０-6／℃〜７×１０-6／℃の範囲としたことを特徴とする半導体装置。In a semiconductor device equipped with a semiconductor element formed of a bare chip , mounted on a circuit board via solder ,
The circuit board is formed by a multi-layer substrate using an organic material as a base member, and a thin layer made of a single metal material having a low coefficient of thermal expansion is provided between layers of the multi-layer substrate,
This thin layer is formed of a plurality of metal layers located at positions symmetrical with respect to the center in the layer thickness direction,
A semiconductor device, wherein a composite thermal expansion coefficient in a direction parallel to an element mounting surface of the circuit board including the thin layer is in a range of 4 × 10 −6 / ° C. to 7 × 10 −6 / ° C. 前記薄層が、金属箔層からなることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein said thin layer comprises a metal foil layer . 前記薄層が、金属メッシュ層からなることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein said thin layer comprises a metal mesh layer . ベース部材が有機系材料からなる回路基板を多層基板によって形成し、次に、この多層基板上にベアチップからなる半導体素子を実装することにより、半導体装置を製造する方法であって、
前記回路基板を形成するにあたり、層間に低熱膨張率の単一の金属材料からなる薄層を設け、
この薄層を、層厚方向中央部に関して対称な位置に位置する複数の金属層で形成するとともに、
この薄層を含む前記回路基板における素子実装面に平行な方向の複合熱膨張率を、４×１０-6／℃〜７×１０-6／℃の範囲としたことを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device by forming a circuit board made of an organic material with a multilayer substrate on a base member, and then mounting a semiconductor element made of a bare chip on the multilayer board,
In forming the circuit board, a thin layer made of a single metal material having a low coefficient of thermal expansion is provided between layers,
This thin layer is formed of a plurality of metal layers located at positions symmetrical with respect to the center in the layer thickness direction,
The composite thermal expansion coefficient of the circuit board including the thin layer in the direction parallel to the element mounting surface is in the range of 4 × 10 −6 / ° C. to 7 × 10 −6 / ° C. Production method. ベアチップからなる半導体素子を、半田を介して実装する回路基板において、In a circuit board on which a semiconductor element composed of a bare chip is mounted via solder,
ベース部材を有機系材料とする多層基板によって形成し、この多層基板の層間に低熱膨張率の単一の金属材料からなる薄層を設け、  The base member is formed by a multilayer substrate made of an organic material, and a thin layer made of a single metal material having a low coefficient of thermal expansion is provided between layers of the multilayer substrate,
この薄層を、層厚方向中央部に関して対称な位置に位置する複数の金属層で形成するとともに、  This thin layer is formed of a plurality of metal layers located at symmetrical positions with respect to the center in the layer thickness direction,
この薄層を含む前記回路基板における素子実装面に平行な方向の複合熱膨張率を、４×１０  The composite thermal expansion coefficient of the circuit board including the thin layer in the direction parallel to the element mounting surface is 4 × 10 -6-6 ／℃〜７×１０/ ℃ ～ 7 × 10 -6-6 ／℃の範囲としたことを特徴とする回路基板。/ ° C. range.
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