JP3004931B2 - Method for manufacturing semiconductor connection board and bare chip mounting board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor connection board for mounting a semiconductor chip such as a bare chip on a printed circuit board and a bare chip mounting board, and more particularly to mounting a chip having a high wiring density on a printed circuit board having a low wiring density. The present invention relates to a method of manufacturing a semiconductor connection substrate for performing the method and a bare chip mounting board for high-density mounting.

[0002]

2. Description of the Related Art In order to electrically function a semiconductor chip such as an LSI which has been formed on a silicon wafer and then diced, electrodes of the chip must be electrically connected to wiring of a printed wiring board. No. Therefore, in general, a chip is connected to a lead frame and sealed, and a housing in which the chip is sealed (hereinafter, referred to as a chip package) is connected to a printed wiring board.

The functions required for the chip package are protection of the chip, establishment of an electrical connection between the chip and the printed wiring board, and heat dissipation. Here, in order to establish the electrical connection, the minute wiring at the chip level must be a wide wiring connectable to a printed wiring board. That is, it is necessary to increase the pitch of the electrode pins and convert the wiring density.

As a means for expanding the pin pitch, a technique is widely used in which a bonding pad of a chip is connected to a wiring on a lead frame side by wire bonding, and the pin pitch is expanded by connecting each wiring to a pin having a large interval. Have been. However, in recent years, the number of bonding pads and the number of pins of a lead frame have been increasing due to an increase in I / O (Input / Output) accompanying higher performance of chips. Therefore, if wires are bonded one by one to a large number of bonding pads, the bonding time becomes longer in proportion to the number of pads.

[0005] Further, as the number of pins of a chip increases, the pin pitch must be narrowed. Therefore, it is becoming increasingly difficult to connect the lead frame to the printed wiring board without short-circuiting. For these reasons, there is a need for a method that replaces wire bonding.

Therefore, recently, a flip-chip connection method has been proposed in which a bump is provided on a pad on the chip side and the bump is mounted on a semiconductor connection substrate. According to this method, the wiring of each bump can be connected simultaneously,
The increase in working time due to the increase in the number of pads is reduced. Further, compared to the wire bonding method, more connection terminals per unit area can be obtained, and the bonding pads can be arranged at arbitrary positions. Therefore, the problem that the pin pitch is narrowed by increasing the number of pins can be reduced. Further, obtaining more connection terminals per unit area leads to a reduction in the size and density of the package.

[0007] As a technology corresponding to the increase in the number of pins depending on the shape of the package, BGA (ball grid array) has been proposed.
Also, those in which connection terminals are provided in an array (lattice-like) such as described above are being put to practical use. By forming the connection terminals in an array, a limited space can be used efficiently, and the size of the package can be further reduced.

[0008]

By the way, as the technology for miniaturizing and improving the performance of semiconductor chips is remarkable, B
A package method of connecting terminals by arranging them in an array like a GA has been developed to cope with the increase in the number of pins. However, as devices are required to be further reduced in weight and size, a packaging substrate material having finer wiring is required to realize a package in which terminal electrodes are arranged in an array.

Further, ceramics are generally used as a packaging substrate material for chips to be wired at a high density at present. However, there are problems such as low flatness and necessity of hierarchical wiring, resulting in large size and inexpensiveness.

On the other hand, it is possible to connect a high-wiring-density chip to the printed wiring board by increasing the wiring density of the printed wiring board, but in reality, it is mounted on one printed wiring board. It is difficult to assume that all electronic components have a high wiring density. That is, it is considered that mixed mounting of a surface mount component having a relatively large pin pitch and a component having a relatively small pin pitch is performed widely. For example, it is considered that there is a need to connect one or two high performance (high wiring density) chips to a printed wiring board having a relatively low wiring density. Therefore, it is not practical to use a printed wiring board that matches a component having the narrowest pin pitch in terms of manufacturing costs. That is, in order to suppress the cost, it is necessary to mount a chip with a high wiring density without increasing the density of the printed wiring board.

When a semiconductor connection board on which a chip having a high wiring density can be mounted is provided, a bare chip mounting board using the semiconductor connection board can be manufactured. This bare chip mounting board can be a multi-chip module (MCM) by mounting a plurality of bare chips,
Since each bare chip has a large number of electrode terminals, the number of wirings for connecting them is also large. When this wiring is arranged on the surface of the board, the area occupied by the wiring becomes large,
There is a possibility that the bare chip mounting board cannot be sufficiently reduced in size. In addition, in order to improve the function of the bare chip mounting board, it is better that the wiring distance between the semiconductor chip and other electronic components is shorter. That is, it is necessary to efficiently carry out wiring of chips and electronic components to be mounted.

As described above, as a package technology for a bare chip or the like, a substrate that can be connected to a high-density printed wiring board and that can be bonded to a low-wiring-density printed wiring board is inexpensive as a package technology for a chip. There is also a demand for a method of manufacturing such a board, and efficient wiring of a board on which a plurality of bare chips are mounted.

The present invention has been made in view of the above points.
And than, a semiconductor chip at the time of packaging, and aims to provide a relatively little material, and a semiconductor connecting substrate manufacturing method capable of expanding the pin pitch in a short step
I do.

It is another object of the present invention to provide a bare chip mounting board in which wiring between chips is performed at a very short distance.

[0015]

According to the present invention, in order to solve the above problems, a plurality of semiconductor chips are connected to a substrate.
Photolithography in a method of manufacturing a semiconductor connection substrate for
The luffy allows the aforementioned feeling to be in a predetermined position on the photosensitive glass substrate.
Drilling a plurality of holes through the light-sensitive glass substrate,
A conductive film is formed on one side of the glass substrate and
Filling the inside of the hole, and further comprising the photosensitive glass substrate.
By growing the conductor until it rises
The conductor film by photolithography.
By image and etching, the distance between the holes and
A plurality of connection terminals arranged at different intervals and the bumps;
Forming wiring that electrically connects the conductors that form
A method for manufacturing a semiconductor connection substrate is provided.

Further, in a method of manufacturing a semiconductor connection substrate for connecting a semiconductor chip to a printed circuit board , a line is formed on an outer periphery of a photosensitive glass substrate by photolithography.
In a certain position, a plurality of holes are formed through the photosensitive glass substrate, and a conductive film is formed on one of the wiring surfaces of the photosensitive glass substrate and the inner wall of the hole by sputtering, and the conductive film is formed by plating. By growing and conducting and etching the conductor film by photolithography,
Wherein forming a plurality of high density terminals arranged on one surface of the photosensitive glass substrate at intervals corresponding to the wiring density of the semiconductor chip, a wiring for electrically connecting the inner wall of the hole,
Cutting the photosensitive glass substrate along the position of the hole
That, a method of manufacturing a semiconductor connecting substrate, characterized in that it is provided.

According to such a method for manufacturing a semiconductor connection substrate, an inexpensive semiconductor connection substrate capable of connecting a semiconductor chip having a high wiring density such as a semiconductor chip and a printed wiring board having a low wiring density can be manufactured.

Further, in a bare chip mounting board in which various semiconductor components are provided on a substrate, a substrate made of photosensitive glass having a plurality of holes provided at predetermined positions, and a conductive material filled in the holes. , On both sides of the substrate,
A bare chip comprising: a wiring forming a connection terminal on the conductive material; and a plurality of bare chips mounted on both surfaces of the substrate by connecting a predetermined electrode to the connection terminal. A mounting board is provided.

According to such a bare chip mounting board, predetermined electrodes of a plurality of mounted bare chips are connected to each other.
They are electrically connected via a conductive material provided in a hole in the substrate. As a result, the wiring between the chips is performed three-dimensionally, and the chips are connected at an extremely short distance.

Further, various semiconductor parts are provided on the substrate.
On a bare chip mounting board
A printed circuit board provided with a substrate side terminal of
A substrate made of photosensitive glass fixed on a substrate,
The substrate of the printed circuit board provided on an end surface of the substrate
A plurality of end connection terminals electrically connected to the side terminals;
A position corresponding to the electrode of the semiconductor chip on one surface of the substrate;
A plurality of high-density terminals arranged in
A wire for electrically connecting the end face connection terminal;
By connecting an electrode to the high-density terminal,
And a bare chip mounted on a plate.
A bare chip mounting board is provided.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a semiconductor connection substrate. The semiconductor connection board 10 is for connecting the bare chip 20 to the upper side in the figure and for connecting the printed wiring board 30 to the lower side in the figure.

As the semiconductor connection substrate 10, a photosensitive glass substrate 11 having chemical cutting properties is used as a base substrate. The photosensitive glass substrate 11 has the same number of holes 11 a to 11 d as the bumps 21 to 24 of the bare chip 20. The holes 11a to 11d are formed in the photosensitive glass substrate 1
1 through. The positions of the holes 11a to 11d correspond to the positions of the electrodes 31 to 34 of the printed wiring board 30 to be connected, and are provided at sufficiently wide intervals.

On the upper surface of the photosensitive glass substrate 11, wirings 13a to 13d etched into a wiring pattern are adhered by an adhesive 12. The wirings 13a to 13d correspond one-to-one with the bumps 21 to 24 of the bare chip 20, respectively. The wirings 13a to 13d electrically connect the positions where the bumps 21 to 24 are to be connected and the holes 11a to 11d when the bare chip 20 is connected.

The inside of each of the holes 11a to 11d is filled with a conductor provided by plating, and bumps 14a to 14d are formed further ahead. With such a semiconductor connection substrate 10, the wiring 1 on the upper surface in FIG.
3a to 13d include bumps 21 to 24 of bare chip 20.
And the electrodes 31 to 34 of the printed wiring board 30 can be connected to the bumps 14a to 14d on the lower surface in the figure. Thereby, the bare chip 20 of high density wiring
Bumps 21 to 24 and the printed wiring board 30 having a large space
Side electrode and 31 to 34 can be electrically connected.

Next, a method of manufacturing the semiconductor connection substrate 10 shown in FIG. 1 will be described. FIG. 2 shows a semiconductor connection substrate 10.
It is a figure which shows the manufacturing process of. In the following description, the surface on which the bump is provided is referred to as “front surface”, and the surface on which the wiring is provided is referred to as “back surface”. [S1] A via hole mask 41 is provided on the back surface of the photosensitive glass substrate 11, and the photosensitive glass substrate 11 is exposed from above.

The photosensitive glass substrate 11 includes Li 2 O—
Al2O3-SiO2 (Au, Ce) -based chemically cut photosensitive glass is used. Further, both surfaces of the photosensitive glass substrate 11 have sufficient smoothness. Then, a Hg-Xe lamp is used for the exposure process, and light from the lamp is irradiated for 20 seconds. Next, a development process is performed. [S2] As a result of the processing in step S1, via holes 11a to 11d are formed in the photosensitive glass substrate 11. The via holes 11a to 11d are formed in the photosensitive glass substrate 11
And the same number as the number of bare chip electrodes to be connected. Also, via hole 11a
Positions 11 to 11d are positions to be matched with the electrodes on the printed wiring board side. Therefore, they are provided at the same interval as the wiring density of the printed wiring board. [S3] An adhesive 12 is applied to the back surface of the photosensitive glass substrate 11 on which the via holes 11a to 11d are formed, and the conductive film 1
Paste 3 [S4] The conductors are grown in the via holes 11a to 11d by plating, and the bumps 14a to 14d are formed.

When plating, the via holes 11a to 11a
By forming an adhesive layer on the inner wall of 11d and performing plating on the adhesive layer, the adhesion of the metal to be plated can be improved. Then, the plating is sufficiently grown so that the plating process at this time protrudes from the surface of the photosensitive glass substrate 11. Thereby, the via holes 11a to 11d are closed by the conductor, and the bumps 14a to 14d are formed ahead of the via holes 11a to 11d. [S5] A photoresist 42 is applied on the conductor film 13 and exposed with a wiring pattern mask 43. [S6] The photoresist 42 is developed to remove the exposed portions. Further, the portion of the conductor film 13 not covered with the photoresists 42a to 42e is removed by etching. [S7] The conductor film 13 is patterned by the development and etching processes in step S6, and wirings 13a to 13e are formed. Then, if necessary, the wirings 13a to 13e
Is plated to form a protective layer (Ni / Au). These wirings 13a to 13e connect the electrodes for connecting to the bumps of the bare chip and the bumps 14a to 14d for connecting to the printed wiring board on a one-to-one basis.

The bare chip is connected to the printed wiring board using the semiconductor connection substrate 10 manufactured as described above. FIG. 3 is a diagram showing a first example of a printed wiring board on which a bare chip is mounted using the semiconductor connection substrate 10. The bumps 21 to 2 are formed on the electrode pads of the bare chip 20.
4 are provided. The bumps 21 to 24 are connected to the wirings 13a to 13d of the semiconductor connection substrate 10, respectively. On the other hand, on the upper surface of the printed wiring board 30, electrodes 31 to 34 for electrically connecting to the electrodes of the bare chip are provided.
Are connected to the bumps 14a to 14d. Thereby, the bumps 21 to 24 of the bare chip 20 and the electrodes 31 to 34 of the printed wiring board 30 are electrically connected.

FIG. 4 is a view showing a second example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate.
This is an example in which no bump is formed on the electrode pad of the bare chip.

In the semiconductor connection substrate 50 shown in this example, via holes 51 a to 51 d of a photosensitive glass substrate 51 are provided.
Are provided at positions that should match the pads of the bare chip 20a. The via holes 51a to 51d are filled with a conductive material, and bumps are formed. On the other hand, wirings 53a to 53 pasted by the adhesive 52
“d” connects the positions of the via holes 51a to 51d and the positions that should match the electrodes 31a, 32a, 33a, and 34a of the printed wiring board 30a.

Then, the bump 54 of the semiconductor connection substrate 50
a to 54d and the pads for the electrodes of the bare chip 20a are connected, and the wirings 53a to 53d on the opposite side and the printed wiring board 3
0a are connected to the electrodes 31a, 32a, 33a, and 34a. In this manner, the bare chip 20a having no bump provided on the electrode pad can be mounted on the printed wiring board 30a.

FIG. 5 is a view showing a third example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate.
This is an example in which a plurality of bare chips are connected to a printed wiring board to form a multi-chip module.

The photosensitive glass substrate 61 of the semiconductor connection substrate 60 shown in this example has two bare chips 20b and 20c.
Via holes 61a to 61f corresponding to the number of electrodes are provided, and bumps 64a to 64f are formed at the ends of conductors filling the via holes 61a to 61f. The positions of the via holes 61a to 61f are positions that should match the electrodes 31b, 32b, 33b, 34b, 35b, 36b of the printed wiring board 30b. The wirings 63a to 63f attached to the photosensitive glass substrate 61 by the adhesive 62 are the wirings 63a to 63c for the bare chip 20b and the bare chip 2
It is divided into wirings 63d to 63f for Oc. The wirings 63a to 63c for the bare chip 20b are
The positions where the bumps 21b, 22b, and 23b of b should match and the positions of the via holes 61a to 61c are connected. On the other hand, the wirings 63d to 63f for the bare chip 20c connect the positions where the bumps 21c, 22c, and 23c of the bare chip 20c should coincide with the positions of the via holes 61d to 61f.

The wiring 63 of such a semiconductor connection substrate 60
The bumps 21b and 22 of the bare chip 20b are provided on a to 63c.
b, 23b are connected, and the bumps 21c, 22c, 23c of the bare chip 20c are connected to the wirings 63d to 63f. The bumps 64a to 64f provided on the semiconductor connection substrate 60 are connected to the electrodes 3 of the printed wiring board 30b.
1b, 32b, 33b, 34b, 35b, 36b. Thereby, the plurality of bare chips 20b, 2
0c is mounted on the printed wiring board 30b.

FIG. 6 is a diagram showing a fourth example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate.
This is because a plurality of bare chips 20d, 20e without bumps
Is mounted on the printed wiring board 30c to form a multi-chip module.

The photosensitive glass substrate 71 of the semiconductor connection substrate 70 shown in this example has two bare chips 20d and 20e.
Via holes 71a to 71f corresponding to the number of electrodes are provided, and bumps 74a to 74f are formed at the tips of conductors filling the via holes 71a to 71f. The positions of the via holes 71a to 71f are bare chips 20d and 20e.
This is the position that should match the position of the electrode pad. The wirings 73a to 73f attached to the photosensitive glass substrate 71 by the adhesive 72 are the electrodes 31 of the printed wiring board 30c.
The positions to be matched with c, 32c, 33c, 34c, 35c, and 36c are connected to the positions of the via holes 71a to 71f.

The wiring 73 of such a semiconductor connection substrate 70
a to 73f are the electrodes 31c, 3 of the printed wiring board 30c.
2c, 33c, 34c, 35c, 36c. Also, the bumps 74 provided on the semiconductor connection substrate 70
a to 74c are connected to the electrode pads of the bare chip 20d, and the bumps 74d to 74f are connected to the electrode pads of the bare chip 20e. As a result, a plurality of bare chips 20d and 20e having no bumps on the pads are mounted on the printed wiring board 30c.

As described above, the following effects can be obtained by connecting a bare chip to a printed wiring board using the semiconductor connection board of the present invention. The first effect is that, even if the number of electrodes on the chip increases, the time required for connection of the semiconductor chip does not become long, the types of materials used for the semiconductor connection substrate are small, and inexpensive materials such as photosensitive glass are used. It is possible to connect a semiconductor chip having a high wiring density, such as a semiconductor chip, to a printed wiring board having a low wiring density by using a simple material.

The second effect is that since the wire bonding is not performed when connecting the semiconductor connection substrate and the bare chip, the pad for the electrode of the bare chip can be reduced. As a result, the chip area can be reduced.

A third effect is that the pads can be arranged at any position. As a result, restrictions in designing the circuit of the chip are relaxed, and the degree of freedom in design is increased. 4th
The effect of (1) is that the number of connection terminals per unit area can be increased by reducing the size of the electrode pad of the bare chip and arranging the pad at an arbitrary position.

The fifth effect is that even with a chip having bumps,
It is possible to connect even chips without bumps. A sixth effect is that the wiring pitch of the semiconductor connection board of the present invention can be freely determined according to the wiring pitch of the printed wiring board. That is, since the current wiring pitch of the printed wiring board is about 300 to 500 μm, when connecting to such a printed wiring board, the wiring can be expanded to the same wiring pitch. On the other hand, if a high-density printed wiring board is used, a fine wiring pitch corresponding to it can be used.

The seventh effect is that the material of the substrate is not an organic resin film, so that the substrate has an appropriate strength. In addition, since the light transmittance is high, a photocurable adhesive can be used.

These effects are the same in other semiconductor connection substrates described below. By the way, in the method shown in FIG. 2, a conductive film is attached after providing a via hole in a photosensitive glass substrate. However, a semiconductor connection substrate is manufactured using a photosensitive glass substrate on which a conductive film is not formed. Can also. Hereinafter, the manufacturing method will be described.

FIG. 7 is a view showing a manufacturing process of a semiconductor connection substrate when a photosensitive glass substrate on which a conductor film has been formed is used. [S11] A mask 44 for a via hole is provided on the surface of a photosensitive glass substrate 81 having a sufficiently smooth surface and a conductive film 82 formed on the back surface, and the photosensitive glass substrate 81 is exposed from above. Then, development processing is performed. [S12] As a result of the processing in step S11, via holes 81a to 81c are formed in the photosensitive glass substrate 81. The via holes 81a to 81c are holes penetrating the photosensitive glass substrate 81, and are provided in the same number as the number of bare chip electrodes to be connected. Also, via hole 81
The positions a to 81c are positions to be matched with the electrodes on the printed wiring board side. The via holes 81a to 81c
Is kept covered with the conductor film 82. [S13] A conductor is grown in the via holes 81a to 81c by plating, and bumps 83a to 83c are formed. [S14] A photo resist 45 is applied to the back surface, and is exposed with a wiring pattern mask 46. Next, by developing and further etching the photoresist 45, a portion of the conductor film not covered with the photoresist 45 is removed. [S15] The conductor film 82 is patterned by the development and etching processes in step S14, and the wirings 82a to 82 are formed.
c is formed. If necessary, the surfaces of the wirings 82a to 82c are plated to form a protective layer (Ni / Au).

Thus, the semiconductor connection substrate of the present invention can be manufactured from the photosensitive glass substrate on which the conductor film has been formed. According to this method, the number of steps can be reduced as compared with the method shown in FIG. The form when the bare chip is mounted on the printed wiring board using this semiconductor connection board is the same as that shown in FIGS.

In the semiconductor connection board described above, terminals for connecting to the printed wiring board are provided on one surface, but connection terminals may be provided on an end face of the board. An example is shown below.

FIG. 8 is a view showing a process of manufacturing a semiconductor connection substrate in which connection terminals for connecting to a printed wiring board are provided on the end face of the substrate. [S21] A row of via holes is formed in the outer peripheral portion of the photosensitive glass substrate 91 made of a sufficiently thin (1 mm or less) chemically-cuttable photosensitive glass using photolithography.
Specifically, a via hole mask 47 is provided on the upper surface of the photosensitive glass substrate 91, and the photosensitive glass substrate 91
And then a development process is performed. [S22] As a result of the process in step S21, via holes 91a and 91b are formed in the photosensitive glass substrate 91. The via holes 91a and 91b are holes penetrating the photosensitive glass substrate 91, and are provided in a line along the outer periphery by the same number as the number of bare chip electrodes to be connected. [S23] A conductive film 92 is formed by sputtering on the back surface of the photosensitive glass substrate 91 where the via holes 91a and 91b are formed. This conductive film 92 is formed on the back surface of the photosensitive glass substrate 91 and the inner walls of the via holes 91a and 91b. [S24] The conductor film 92 is grown by plating. Thus, a new conductor film 93 is formed on the conductor film 92 formed by sputtering, and a sufficient film thickness can be obtained. [S25] The formed conductor films 92 and 93 are developed and etched by lithography. Thereby, the wiring 93
a to 93e are formed. The surfaces of the wires 93a to 93e are plated to form a protective layer (Ni / Au). [S26] Via holes 9 aligned on the outer periphery
The photosensitive glass substrate 91 is cut along 1a and 91b. As a result, portions where the via holes 91a and 91b are formed become connection terminals 94a and 94b.

FIG. 9 is a view showing a semiconductor connection substrate having connection terminals on an end face of the substrate. (A) is a top view. The semiconductor connection board 90 is provided with connection terminals 94 along the side surface. Each connection terminal 94 is connected to the bare chip connection terminal in the bare chip mounting area 95 one-to-one by a wiring 93.

(B) is a sectional view taken along line XX of (A).
The connection terminals 94 c and 94 are provided on the side surface of the photosensitive glass substrate 91.
d is provided, and a wiring 93f is provided on the upper surface.

FIG. 10 is an enlarged view of the connection terminal provided on the end face of the substrate. The connection terminal 94 is a photosensitive glass substrate 91
The inner surface of the via hole is originally formed on the inner surface of the via hole, so that the surface has the shape of the inner surface of a cylinder. The wiring 93 is electrically connected to a bare chip connection terminal.

FIG. 11 is a diagram showing a first example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate having connection terminals on an end face. On the printed wiring board 30d,
Connection terminals 31d and 32d are provided around the position where the semiconductor connection substrate 90 is arranged.

The bare chip 20f is connected to the upper surface of the semiconductor connection substrate 90. On the other hand, the photosensitive glass substrate 91
Are connected to the connection terminals 31d and 32d of the printed wiring board 30d by conductive adhesive materials 48a and 48b such as solder. The connection terminals 94e and 94f are connected to the bumps 21f and 24f of the bare chip 20f by wires 93g and 93j provided on the upper surface of the photosensitive glass substrate 91, respectively. In addition, bump 2 of bare chip 20f
2f and 23f are connected to wirings 93h and 93i,
The wirings 93h and 93i are connected to connection terminals (not shown) on the printed wiring board 30d via connection terminals (not shown) on the end surface of the photosensitive glass substrate 91.

FIG. 12 is a view showing a second example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate having connection terminals on the end surface. This is an example where a plurality of bare chips are mounted on a semiconductor connection substrate. The printed wiring board 30e is provided with connection terminals 31e and 32e around a position where the semiconductor connection substrate 101 is arranged.

Two bare chips 20g and 20h are connected to the upper surface of the semiconductor connection substrate 100. Connection terminals 104a, 1 provided on the end face of the photosensitive glass substrate 101
04b is a conductive adhesive material 48c, 48 such as solder.
d, the connection terminals 31e, 3 on the printed wiring board 30e side.
2e. Also, the connection terminals 104a, 104
4b, the bare chips 20g, 2g are provided by wires 103a, 103f provided on the upper surface of the photosensitive glass substrate 101.
0h are connected to the bumps 21g and 23h. In addition,
Bumps 22g, 23g, 2 of bare chips 20g, 21h
1h and 22h are connected to wirings 103b to 103e, and the wirings 103b to 103e are connected to the printed wiring board 30e (not shown) via connection terminals (not shown) on the end surface of the photosensitive glass substrate 101. Connected to terminal.

In this way, a bare chip can be mounted on a printed wiring board by using a semiconductor connection board having connection terminals provided on the end face of the board. When the connection terminals are provided on the end face of the board, the semiconductor connection board can be miniaturized, and can be easily mounted on a printed wiring board using a conventionally established technique such as soldering.

Here, when a semiconductor connection board having connection terminals provided on an end face of the board is mounted on a printed wiring board, the positions of the connection terminals and the positions of the terminals on the printed wiring board side are accurately matched (alignment is performed). )There is a need. Therefore,
By using a transparent photosensitive glass as the material of the substrate, alignment can be easily performed.

FIG. 13 is a view showing a position confirmation direction when a semiconductor connection substrate using transparent photosensitive glass and a printed wiring board are connected. The semiconductor connection substrate 200 is made of transparent photosensitive glass, and has a bare chip 20 on its upper surface.
n are connected. When mounting the semiconductor connection substrate 200 on the printed wiring board 300, the semiconductor connection substrate 2
The position of the semiconductor connection substrate 200 is visually recognized from above (in the direction indicated by the arrow in the figure).

FIG. 14 is a diagram showing a scene visually recognized at the time of alignment. (A) is a diagram showing a state before the semiconductor connection substrate 200 approaches a target position. Connection terminals 211 to 214 are provided on the end surface of the semiconductor connection substrate 200, and the connection terminals 211 to 214
224 are electrically connected to the terminals of the bare chip. Wirings 301 to 304 for connecting to a bare chip are provided on the printed wiring board side. In this example, the connection terminals 211 to 214 are connected to the wiring 30 respectively.
1 to 304.

FIG. 7B is a view showing a state in which the semiconductor connection substrate 200 is brought close to a target position. Semiconductor connection board 2
Since 00 is made of a transparent photosensitive glass substrate, the printed wiring board below can be seen through except for the area where the wirings 221 to 224 are provided. Therefore, the wirings 301 to 304 formed on the printed wiring board can be sufficiently visually recognized, and alignment can be easily performed.

On the other hand, when more accurate alignment is required or when alignment is performed by image analysis using a computer, it is convenient to prepare alignment marks (hereinafter referred to as alignment marks). It is.

FIG. 15 is a diagram showing an alignment situation when an alignment mark is provided. (A) is a diagram showing a state before the semiconductor connection substrate 400 approaches a target position. The connection terminal 4 is provided on the end face of the semiconductor connection substrate 400.
11 to 414 are provided, and each connection terminal 411 to 4
14 is electrically connected to terminals of the bare chip by wirings 421 to 424. Further, the semiconductor connection substrate 40
A cross-shaped mark 401 for alignment is provided at the corner of 0. Wirings 511 to 514 for connecting to a bare chip are provided on the printed wiring board side. Furthermore, four squares for positioning are also provided on the printed wiring board side.
Marks 501 are provided in a row. And
In this example, the connection terminals 411 to 414 are
11 to 514.

(B) is a diagram showing a state in which the semiconductor connection substrate 400 is brought close to a target position. At the time of alignment, the cross shape of the mark 401 on the semiconductor connection substrate 400 is adjusted so as to match between the squares of the mark 501 on the printed wiring board. Semiconductor connection board 400
Are transparent, so that both marks 401 and 501 can be marked even when the semiconductor connection substrate 400 is overlaid on the printed wiring board.
Can be visually recognized. Therefore, the semiconductor connection substrate 400
Can be placed in accurate positions.

Incidentally, in many recent chip packages, a pin grid form is adopted. Therefore, a case in which the connection terminal on the semiconductor connection board side for connecting to the printed wiring board is in a pin grid form will be described below.

FIG. 16 is a view showing a process of manufacturing a semiconductor connection board in which connection terminals to a printed wiring board are formed in a pin grid form. [S31] A row of via holes is formed in the outer peripheral portion of the photosensitive glass substrate 111 of a sufficiently thin (1 mm or less) chemically cut photosensitive glass by photolithography. Specifically, a mask 49 for via holes is provided on the upper surface of the photosensitive glass substrate 111, and the photosensitive glass substrate 111 is exposed from above. Next, a development process is performed. [S32] As a result of the processing in step S31, via holes 111a and 111b are formed in the photosensitive glass substrate 111. The via holes 111a and 111b are holes penetrating the photosensitive glass substrate 111, and are provided in a row along the outer periphery by the same number as the number of bare chip electrodes to be connected. [S33] A conductive film 112 is formed by sputtering on the back surface (upper surface in the drawing) of the photosensitive glass substrate 111 in which the via holes 111a and 111b are formed. This conductor film 1
12 is the back surface of the photosensitive glass substrate 111 and the via hole 1
It is formed on the inner walls of 11a and 111b. [S34] The conductive film 112 is grown by plating. Thereby, a new conductor film 113 is formed on the conductor film 112 formed by sputtering, and a sufficient film thickness can be obtained. [S35] The formed conductor films 112 and 113 are developed and etched by lithography. Thus, the wirings 113a to 113e are formed. This wiring 113a ~
Reference numeral 113e connects the connection terminal to be connected to the bare chip electrode and the conductor film on the inner wall of the via hole on the outer periphery in a one-to-one relationship. Therefore, by penetrating the conductive pins through the respective via holes 111a and 111b, it is possible to obtain a semiconductor connection substrate having connection terminals with the printed wiring board.

Here, as a form in which a bare chip is connected to the semiconductor connection substrate and a pin is penetrated, a plurality of forms can be considered depending on a direction in which a conductive pin is penetrated and a connecting direction of the bare chip.

FIG. 17 is a diagram showing an example in which a bare chip is connected to the side opposite to the pin protruding side. [S41] Wirings 113a to 113 of the semiconductor connection substrate 110
On the surface opposite to the surface on which 3e is formed, an insulating adhesive material 115 is provided.
The substrate reinforcing material 114 is adhered by using. Holes 114a and 114b are formed in the substrate reinforcing member 114 at positions overlapping the via holes 111a and 111b.
A through hole is secured at the positions of a and 111b. [S42] The wiring pins 116 and 117 are inserted into the via holes 111a and 111b from the surface of the semiconductor connection substrate 110 where the wirings 113a to 113e are provided. [S43] The bare chip 20i is connected to the surface provided with the wirings 113a to 113e, and the bare chip 20i and the wiring pins 116 and 117 are fixed with the insulating adhesive 118. As a result, a chip package having pin grid type connection terminals is obtained.

In the step S43 of FIG. 17, a lid may be provided above the bare chip 20i. FIG.
FIG. 8 is a diagram showing an example of a case where a bare chip is sealed with a lid. This example corresponds to steps S41 and S41 in FIG.
After the step 42, the bare chip 20i is connected, a lid 119 is put on it, and it is fixed with an insulating adhesive 118a.

Next, a case where a wiring pin is inserted from the opposite direction to the above example will be described. FIG. 19 is a diagram illustrating an example in which a bare chip is connected to the same surface as the pin protruding side. [S51] Wirings 113a to 113 of the semiconductor connection substrate 110
The substrate reinforcing material 121 is bonded to the surface opposite to the surface on which 3e is formed, using the insulating adhesive 122. Holes 121a and 121b are formed in the substrate reinforcing member 121 at positions overlapping with the via holes 111a and 111b.
A through hole is secured at the positions of a and 111b. [S52] The wiring pins 12 are formed in the via holes 111a and 111b from the direction in which the substrate reinforcing material 121 is provided.
Insert 3,124. [S53] A lid 126 for holding down the pins is adhered to the substrate reinforcing member 121 with the insulating adhesive 125. [S54] The bare chip 20j is connected to the surface on which the wirings 113a to 113e are provided. Thus, the bare chip is mounted in the same direction as the projecting direction of the wiring pin.

As described above, the wiring pins may be inserted from any surface of the semiconductor connection substrate. Therefore, by superposing two semiconductor connection substrates, bare chips can be connected to both surfaces to form a multi-chip configuration.

FIG. 20 is a diagram showing an example in which a semiconductor connecting substrate is superposed to form a multi-chip structure. In this example, two semiconductor connection substrates 130 and 140 are used. These semiconductor connection substrates 130 and 140
Are formed with conductive films 132 and 142 on photosensitive glasses 131 and 141, respectively, and further formed with conductive films 13
3,143 are formed. These conductor films are developed and etched by lithography to form wiring.

Two semiconductor connection substrates 130 and 140
The surfaces opposite to the surfaces on which both wirings are provided are bonded together with the insulating substrate 151 interposed therebetween. Bare chips 20k and 20m are connected to each wiring.

The wiring pins 152 and 153 are inserted from the direction of the semiconductor connection substrate 130. The periphery of the wiring pins 152 and 153 and the bare chip 20k is fixed with an insulating adhesive 154. Similarly, the periphery of the bare chip 201 is also fixed with the insulating adhesive 155.

As described above, by bonding two semiconductor connection substrates, the size of a chip package having a multi-chip configuration can be reduced. Note that FIG.
In the example of No. 0, the wiring on both surfaces is connected only at the position where the wiring pins 152 and 153 are provided, but if the wiring holes are provided at other positions, the electrodes of the chips on both surfaces are connected. Can be connected with the shortest distance. With such a configuration, it is possible to obtain a bare chip mounting board on which various chips are mounted at a very high density. An example of this bare chip mounting board is shown below.

FIG. 21 is a diagram showing a bare chip mounting board for high-density mounting. (A) is a top view, and (B) is a YY sectional view of (A). In the bare chip mounting board 160, wirings 162a and 162b are formed on both surfaces of the photosensitive glass substrate 161 by lithography. The photosensitive glass substrate 161 has wirings 1 on both sides.
Numerous holes (via holes) 161a for electrically connecting 62a and 162b are formed. This hole 16
1a is provided mainly at a position that linearly connects the positions of the electrode terminals on both surfaces. The inside of the hole 161a is filled with a conductive material. This conductive material and the wiring 162 on both sides
a and 162b, the wiring 162a and 162b on both surfaces are electrically connected to each other.

On both surfaces of the photosensitive glass substrate 161, a bare chip such as a CPU chip 163 and a memory chip 164 and electronic components such as a chip capacitor 165 are mounted. The CPU chip 163 and some of the memory chips 164a and 164b are mounted on the surface, and the other memory chips 164c to 164f and the chip capacitor 16 are mounted.
5a to 165d are mounted on the back surface. The predetermined electrodes of the bare chip and the electronic component are connected to the electrode terminals above the holes of the photosensitive glass substrate 161.

Thus, the electrodes of the chip mounted on the front surface and the electrodes of the chip mounted on the back surface can be connected with the shortest distance. The thickness of the photosensitive glass substrate 161 is
Since it is about 0.7 to 1.0 mm, the length of the wiring is also about the same. In addition, it is possible to remove the restriction frame that the wiring between chips is limited on one plane, and combine the wiring in the plane direction and the wiring in the vertical direction. Therefore, the size of the bare chip mounting board can be further reduced, and the wiring resistance can be reduced, so that a high-frequency operation clock can be supported.

By mounting on both sides as shown in the figure, a capacitor to be provided between the power supply terminal and the ground terminal of the bare chip can be connected to the back side of the chip. Therefore, when designing a wiring pattern, a place where a capacitor should be mounted can be easily secured. Since this capacitor functions to adjust the waveform of a signal input to and output from the semiconductor chip, if the necessary capacitor is securely mounted, the operation stability of the entire multi-chip module is improved. In addition, since the capacitor itself is very small, even if a large number of capacitors are mounted, the size of the bare chip mounting board does not increase.

The bare chip mounting board as shown in FIG. 21 can constitute one computer system by itself. However, when it is necessary to mount this bare chip mounting board on a printed wiring board, it is shown in FIG. Such wiring pins may be provided.

[0079]

As described above, according to the method for manufacturing a semiconductor connection substrate of the present invention, a semiconductor connection substrate can be manufactured using photosensitive glass as a substrate. However, it is possible to manufacture the semiconductor connection substrate without increasing the manufacturing cost extremely.

In the bare chip mounting board of the present invention, the bare chips are mounted on both sides of the substrate made of photosensitive glass, and wiring is performed through holes provided in the substrate. It is performed three-dimensionally, and the chips mounted on both sides of the substrate are connected at an extremely short distance. Accordingly, the size of the bare chip mounting board can be reduced, and at the same time, high-frequency operation can be performed due to a decrease in wiring resistance.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor connection substrate.

FIG. 2 is a diagram showing a manufacturing process of a semiconductor connection substrate.

FIG. 3 is a diagram showing a first example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate.

FIG. 4 is a diagram illustrating a second example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate.

FIG. 5 is a diagram showing a third example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate.

FIG. 6 is a diagram illustrating a fourth example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate.

FIG. 7 is a diagram showing a manufacturing process of a semiconductor connection substrate when a photosensitive glass substrate on which a conductor film has been formed is used.

FIG. 8 is a diagram illustrating a manufacturing process of a semiconductor connection substrate in which connection terminals for connecting to a printed wiring board are provided on an end face of the substrate.

FIG. 9 is a view showing a specific example of a semiconductor connection substrate having connection terminals on an end face of the substrate. (A) is a top view and (B)
FIG. 3 is a sectional view taken along line XX of FIG.

FIG. 10 is an enlarged view of a connection terminal provided on an end face of a substrate.

FIG. 11 is a diagram showing a first example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate having connection terminals on an end surface.

FIG. 12 is a diagram illustrating a second example of a printed wiring board on which a bare chip is mounted using a semiconductor connection substrate having connection terminals on an end surface.

FIG. 13 is a diagram showing a position confirmation direction when a semiconductor connection substrate using a transparent photosensitive glass is connected to a printed wiring board.

FIG. 14 is a diagram showing a scene visually recognized at the time of alignment. (A) is a figure which shows the state before approaching a semiconductor connection board to a target position, (B) is a figure which shows the state which brought the semiconductor connection board close to the target position.

FIG. 15 is a diagram showing an alignment situation when an alignment mark is provided. (A) is a figure which shows the state before approaching a semiconductor connection board to a target position, (B)
FIG. 4 is a diagram showing a state where the semiconductor connection substrate is brought close to a target position.

FIG. 16 is a diagram illustrating a manufacturing process of a semiconductor connection substrate in which a connection terminal to a printed wiring board is in a pin grid form.

FIG. 17 is a diagram illustrating an example of a case where a bare chip is connected to a side opposite to a pin protruding side;

FIG. 18 is a diagram showing an example of a case where a bare chip is sealed with a lid.

FIG. 19 is a diagram illustrating an example of a case where a bare chip is connected to the same surface as the pin protruding side.

FIG. 20 is a diagram showing an example of a case where a semiconductor connection substrate is overlaid to form a multi-chip configuration.

FIG. 21 is a diagram showing a bare chip mounting board that enables high-density mounting. (A) is a top view, and (B) is a YY sectional view of (A).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor connection board 11 Photosensitive glass substrate 12 Adhesive 13a-13d Wiring 14a-14d Bump 20 Bare chip 21-24 Bump 30 Printed wiring board 31-34 Electrode

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor connection substrate for connecting a plurality of semiconductor chips to a substrate, wherein a plurality of holes penetrating the photosensitive glass substrate are formed at predetermined positions of the photosensitive glass substrate by photolithography. Forming a conductor film on one surface of the photosensitive glass substrate, filling the inside of the hole by plating, and growing a conductor until it rises on the surface of the photosensitive glass substrate to form a bump; By developing and etching the conductive film by photolithography, a plurality of connection terminals arranged at intervals different from the intervals of the holes and wirings for electrically connecting the conductors forming the bumps are formed. A method for manufacturing a semiconductor connection substrate, characterized by comprising: 2. A manufacturing method of a semiconductor connecting substrate for connecting a semiconductor chip to a printed circuit board, by photolithography, on the outer periphery of the photosensitive glass substrate
A plurality of holes penetrating the photosensitive glass substrate are formed in a row , a conductive film is formed on one of the wiring surfaces of the photosensitive glass substrate and the inner wall of the hole by sputtering, and the conductor A plurality of high-density terminals arranged on one surface of the photosensitive glass substrate at intervals according to the wiring density of the semiconductor chip by growing a film and developing and etching the conductive film by photolithography. If, forming a wiring for electrically connecting the inner wall of the hole, to cut the photosensitive glass substrate along the position of the hole
A method of manufacturing a semiconductor connection substrate. 3. A bare chip mounting board in which various semiconductor components are provided on a substrate, wherein a substrate made of photosensitive glass having a plurality of holes provided at predetermined positions, and a conductive material filled in the holes. A wiring forming a connection terminal on the conductive material on both surfaces of the substrate; and a plurality of bare chips mounted on both surfaces of the substrate by connecting a predetermined electrode to the connection terminal. A bare chip mounting board characterized by having: 4. A bare chip mounting board on which various semiconductor components are provided on a board, comprising: a printed board provided with a plurality of board-side terminals at predetermined positions; and a photosensitive glass fixed on the printed board. A board, a plurality of end face connection terminals provided on an end face of the board, and electrically connected to the board-side terminals of the printed board; and a position corresponding to an electrode of the semiconductor chip on one face of the board. A plurality of high-density terminals arranged, wiring for electrically connecting the high-density terminal and the end face connection terminal, and a predetermined electrode connected to the high-density terminal,
A bare chip mounted board, comprising: a bare chip mounted on the substrate.