JP2004071698A - Semiconductor package - Google Patents

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JP2004071698A
JP2004071698A JP2002226065A JP2002226065A JP2004071698A JP 2004071698 A JP2004071698 A JP 2004071698A JP 2002226065 A JP2002226065 A JP 2002226065A JP 2002226065 A JP2002226065 A JP 2002226065A JP 2004071698 A JP2004071698 A JP 2004071698A
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thermal expansion
low thermal
substrate
metal layer
semiconductor package
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Shingo Kumamoto
熊本 晋吾
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Proterial Ltd
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Hitachi Metals Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin and light semiconductor package which is superior in connection reliability in the semiconductor package and which has less warpage deformation. <P>SOLUTION: The semiconductor package has a semiconductor device, a substrate arranged to surround the semiconductor device, and a wiring layer where wiring connected to an inner connection terminal and an insulating layer are laminated on an inner connection terminal side of the semiconductor device and on one face side of the substrate. The substrate is the semiconductor package where a resin layer and a low thermal expansion metal layer around the semiconductor device and whose average thermal expansion coefficient at 30 to 200°C is -5ppm/°C to 10ppm/°C are compounded. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、コンピューター、通信機器等の電子機器に用いられる半導体素子を配線回路基板等に実装するために用いられる半導体パッケージに関するものである。
【0002】
【従来の技術】
近年、コンピューター、携帯情報・通信端末に代表される電子機器では、高機能化および小型化が目覚しい。これら電子機器に用いられる半導体素子と配線回路基板の電気的接続を行うためには、半導体素子を一般にパッケージと呼ばれる実装用部材に搭載し、パッケージを介して配線回路基板に搭載される実装形態が採られてきた。ここで半導体素子をパッケージ側配線に接続する端子の数は、半導体素子の高集積化と電子機器の高機能化に伴い、年々増加する傾向にある。また、機器の小型化および薄型化の要求もあるため、配線回路基板上に半導体素子を高密度に実装できる小型で薄型のパッケージが求められている。さらには、半導体素子をリードフレーム上に搭載しワイヤボンディングにより両者の接続を取る方式や、多層基板で構成されるインターポーザー上にはんだバンプ等を介して半導体素子を搭載する方式のパッケージでは、半導体素子の動作速度の高速化に伴い、電力供給および信号伝送の遅延が問題となりつつある。
【0003】
上述した要求や問題に対し、図2に模式図で示す半導体パッケージが提案されている。図2において、基板(1)は開口部を有し、半導体素子(2)を取り巻く如く配置され、両者は封止樹脂(3)を用いて固定される。そして、半導体素子上の内部接続端子(4)側に絶縁層(5)と配線(6)を逐次積層して多層配線層(7)を形成し、前記多層配線層の外側に入出力用端子(8)をはんだ(9)で接合したパッケージとなっている。
このパッケージは従来と比較して、その構造上薄く、軽くすることが可能である。電気的には、半導体素子(2)と入出力用端子(8)間の配線距離が短いためインダクタンスが低減され、信号遅延やノイズの問題が解消され、さらにコンデンサ(10)を半導体素子(2)の近くに配置できるため、高周波動作に伴う急激な電力供給にも対応できる。また、内部接続端子(4)に直接、配線(6)が形成されるため、ワイヤーやはんだバンプ等の接続用部材が不要であり、半導体素子とパッケージの高密度な内部接続が可能という利点もある。
【0004】
【発明が解決しようとする課題】
上述したパッケージは数々の利点が挙げられる。しかし、基板(1)を一般的な配線回路基板の絶縁体として用いられる樹脂材料、例えばエポキシ樹脂やBT(ビスマレイミドトリアジン)樹脂、ポリイミド樹脂で形成した場合、半導体素子と基板の熱膨張差により封止樹脂(3)の剥離が生じる問題や、基板の熱膨張および収縮により多層配線層内の層間接続部(11)にクラックが生じ易い問題がある。また、基板の剛性不足から反り変形が生じ易い問題がある。
本発明は上述したパッケージ構造におけるこれらの問題点を鑑みてなされたもので、その目的とするところは薄型軽量で内部の接続信頼性に優れ、反り変形の少ない半導体パッケージを提供することにある。
【0005】
【課題を解決するための手段】
本発明者は、基板を樹脂層と低熱膨張金属層とを複合したものとすることにより、接続信頼性や反りの問題を大きく改善できることを見出し、本発明に到達した。
【0006】
すなわち本発明は、半導体素子と、該半導体素子を取り巻く如く配置される基板と、該基板の一方の面側であって半導体素子の内部接続端子側に、該内部接続端子と接続される配線と絶縁層が積層されてなる配線層とを有する半導体パッケージであって、前記基板は、樹脂層と、前記半導体素子を取り巻く30〜200℃の平均熱膨張係数が−5ppm/℃以上10ppm/℃以下の低熱膨張金属層とが複合されている半導体パッケージである。
【0007】
より好ましくは、低熱膨張金属層の硬さがビッカース硬さで200以上400以下である半導体パッケージである。さらに好ましくは、低熱膨張金属層はニッケルを27〜52質量%含み、残部が実質的に鉄からなる鉄−ニッケル系合金、または前記ニッケルを20質量%以下のコバルトで置換した鉄−ニッケル−コバルト系合金のいずれかである半導体パッケージである。
【0008】
【発明の実施の形態】
以下に本発明を詳細に説明する。上述したように本発明の重要な特徴は、パッケージ全体の剛性を担う基板に、低熱膨張金属層を複合したもので形成したことにある。
低熱膨張金属層の存在により剛性が高まり、反り変形を防止出来るとともに、パッケージおよびそれを用いる電子機器製造工程中の熱履歴や、半導体素子の駆動に伴う急激な温度変化、使用環境の温度変化等によりもたらされる、パッケージ内の熱応力の発生を低減でき、パッケージ内部の接続信頼性を高めることができるものである。
低熱膨張金属層は、一層である必要はなく、複数層で合っても良い。また、低熱膨張金属層の配置位置は、基板表面に露出する形でもよいし、基板に内包された形でも良い。
このような配置位置や層数は、基板を構成している樹脂層の膨張特性、パッケージの配線層の膨張特性、あるいはパッケージ全体の放熱効果等を考慮して決定することができる。
【0009】
本発明では、基板に配置する低熱膨張金属層の熱膨張係数として、30〜200℃の平均熱膨張係数が−5ppm/℃以上10ppm/℃以下であることが必要である。この熱膨張範囲より低い場合は、基板を構成するもう一つの部材である樹脂層との熱膨張差が大きくなり、低熱膨張金属層と樹脂層の界面で剥離が生じる恐れがある。逆に高い場合は基板の熱膨張が低減され難く、基板と半導体素子の熱膨張差を緩和する効果が十分得られない。より好ましくは、3ppm/℃〜10ppm/℃の範囲である。
また、本発明の半導体パッケージにおいて、薄型化を考慮すると、これらの低熱膨張金属層の厚さは5〜500μmが望ましいが、特に限定するものではない。
【0010】
本発明に用いる低熱膨張金属層が硬いほど、基板の剛性を向上可能である。ただし極端に硬い場合や、基板に用いる樹脂との硬さの差が著しく大きくなると、開口部の打ち抜きプレスや切削加工が困難になる。そこで、低熱膨張金属層の硬さがビッカース硬さで200以上400以下であることが望ましい。より好ましくは、210以上300以下である。
上述した特性を兼備した低熱膨張金属層として、モリブデンやタングステン等の高融点金属材料も適用可能であるが、これらの金属材料と比較して加工性に優れ、比較的入手が容易な鉄系の合金を使用することが好ましい。
【0011】
具体的には、低熱膨張特性が得られるニッケルを27〜52質量%含み、残部が実質的に鉄からなる鉄−ニッケル系合金、または前記ニッケルを20質量%以下のコバルトで置換した鉄−ニッケル−コバルト系合金である。さらに具体的には、インバー合金や42アロイに代表される鉄−36質量%ニッケル合金および鉄−42質量%ニッケル合金、鉄−50質量%ニッケル合金、コバールと称される鉄−29質量%ニッケル−17質量%コバルト合金が挙げられる。
【0012】
また、本発明の基板を構成する樹脂層としては、エポキシ、フェノール、BT、ポリイミド、ポリアミド、フッ素樹脂、液晶ポリマー等の樹脂フィルムや、これらの樹脂をガラス等の無機質繊維やポリアミド等の有機質繊維等からなる織布、不織布に含浸させたプリプレグが使用できる。
低熱膨張金属層と樹脂層とは、たとえば、真空加熱プレス等により温度と圧力を用いて、両者を積層接着することが可能である。
十分な密着力が得られない場合は、必要に応じて接着剤層を介して低熱膨張金属層と樹脂層を接着すれば良い。また、低熱膨張金属上に直接樹脂ワニスを塗工、乾燥させて接着し、低熱膨張金属層と樹脂層の積層体を形成しても良い。
【0013】
低熱膨張金属層側の密着力向上手段として表面の粗化を行い、アンカー効果により樹脂との密着力を向上させることも有効である。粗化処理方法としては薬液によるエッチング法や、表面を荒らしたロールを用いて圧延し、低熱膨張金属層表面に転写させる方式が可能である。また、低熱膨張金属層表面に銅めっきを行い、さらに黒化処理を行って別金属の層を設け、樹脂との密着性を向上させることも可能である。特に低熱膨張金属層として鉄−ニッケル系合金あるいは鉄−ニッケル−コバルト系合金を用いる場合、銅めっきを施すと表面が防食されるため好ましい。
【0014】
図1に本発明の半導体パッケージの一例である断面模式図で示す。
図1において、基板(1)は、半導体素子(2)を取り巻く如く配置され、両者は封止樹脂(3)を用いて固定される。そして、半導体素子上の内部接続端子(4)側に絶縁層(5)と配線(6)を逐次積層して配線層(7)を形成し、前記配線層の外側に入出力用端子(8)をはんだ(9)で接合したパッケージとなっている。このように基本構造は、上述した従来の構造である図2と同じである。
本発明の特徴は、基板(1)の構成に関し、従来のように樹脂のみで構成された基板ではなく、樹脂層(12)と30〜200℃の平均熱膨張係数が−5ppm/℃以上10ppm/℃以下の低熱膨張金属層(13)が複合された構造としたことにある。図1で配線層(7)は2層の絶縁層(5)と配線(6)を有するが、これらの層数は必要に応じて決定されるものであり、各1層の配線層でも良いし、さらに多層の配線層を形成しても良い。また図1で、入出力用端子(8)はピンの形状を示しているが、はんだボール等のバンプ状の形態を取ることも可能である。
【0015】
本発明である半導体パッケージの製造方法としては、例えば図3に示すように、(a)樹脂層(12)と低熱膨張金属層(13)からなる積層板(14)を準備し、(b)半導体素子を搭載するための開口部(15)を加工して基板(1)を作製する。積層板は、樹脂層と低熱膨張金属層を真空加熱プレスまたは加熱ラミネート等で加熱圧着することにより製造可能である。開口部は打ち抜きプレスまたは切削等の機械加工が適用できる。
また、(c)先に低熱膨張金属層(13)に開口部(15)をエッチングまたは機械加工で設け、(d)その後樹脂層との積層を行って開口部にも樹脂を充填し、(e)開口部に相当する樹脂部分を機械加工により開口すると、開口部の内壁に樹脂と低熱膨張金属の異種材質が露出せず、加工が容易である。
【0016】
次に(f)半導体素子(2)を開口部に配置し、封止樹脂(3)を用いて基板と半導体素子を接合する。そして、(g)半導体素子上の内部接続端子(4)側に絶縁層(5)を積層配置し、(h)層間接続用のビアホール(16)をレーザー加工により開口する。続いて、(i)層間接続部(11)および配線(6)を銅めっきにより形成し、多層配線層の1層目となる。層間接続部は導電ペーストを充填しても良い。さらに(g)〜(i)の工程を繰り返し、(j)配線層(7)が形成される。その後、(k)はんだ(9)を介して入出力用端子(8)、コンデンサ(10)を接合し、本発明の基本構造を有する半導体パッケージとなる。
【0017】
本発明では、基板に低熱膨張金属層を配置する形態として、低熱膨張金属層を多層にした例を図4に示す。図4に示すように2層の低熱膨張金属層(13)を配置した場合、2層の間隔を離すことにより、同じ体積率の低熱膨張金属層を1層含む基板(図1)よりも曲げ剛性が高くなる利点が生じる。もちろん、さらに多層に分割して低熱膨張金属層を配置することも可能であり、基板表面に低熱膨張金属層(13)が露出する形でも良い。
また、基板の側面に露出する低熱膨張金属層の面積を低減した本発明例を図5に示す。樹脂層(12)が低熱膨張金属層(13)を包含することにより、樹脂/低熱膨張金属界面の露出が避けられ、両者の接合界面の腐食や剥離の危険性が大きく低減される。図6に示すように、低熱膨張金属層をさらに多層に分割して配置することも可能である。
【0018】
図7は、低熱膨張金属層(13)に多数の孔(17)を形成した本発明例を示す。孔内で樹脂と樹脂の接合部(18)が得られ、樹脂層(12)と低熱膨張金属層(13)との接合強度が高まり、半導体パッケージとしての耐久性が飛躍的に向上する。孔の形状は円形でも矩形でも良く、その配置も格子状、千鳥状が可能である。孔の形成は、低熱膨張金属にエッチングあるいはプレス加工等の機械加工を用いて穿孔すれば良い。また、図8に示すように、低熱膨張金属層を多層に分割して配置しても良い。
【0019】
【発明の効果】
本発明によれば、基板を樹脂層と低熱膨張金属層の積層体で構成することにより、薄型軽量で内部の接続信頼性に優れ、反り変形の少ない半導体パッケージを提供することが可能となる。
【図面の簡単な説明】
【図1】本発明の半導体パッケージの一例を示す断面模式図である。
【図2】従来の半導体パッケージの一例を示す断面模式図である。
【図3】本発明の半導体パッケージの製造工程の一例を示す概略図である。
【図4】本発明の半導体パッケージの一例を示す断面模式図である。
【図5】本発明の半導体パッケージの一例を示す断面模式図である。
【図6】本発明の半導体パッケージの一例を示す断面模式図である。
【図7】本発明の半導体パッケージの一例を示す断面模式図である。
【図8】本発明の半導体パッケージの一例を示す断面模式図である。
【符号の説明】
1.基板、2.半導体素子、3.封止樹脂、4.内部接続端子、5.絶縁層、6.配線、7.配線層、8.入出力用端子、9.はんだ、10.コンデンサ、
11.層間接続部、12.樹脂層、13.低熱膨張金属層、14.積層板、
15.開口部、16.ビアホール、17.孔、18.樹脂と樹脂の接合部
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package used for mounting a semiconductor element used in an electronic device such as a computer or a communication device on a printed circuit board or the like.
[0002]
[Prior art]
In recent years, electronic devices represented by computers and portable information / communication terminals have been remarkably improved in function and size. In order to electrically connect the semiconductor element used in these electronic devices and the printed circuit board, there is a mounting form in which the semiconductor element is generally mounted on a mounting member called a package and mounted on the printed circuit board via the package. Have been taken. Here, the number of terminals for connecting the semiconductor element to the package-side wiring tends to increase year by year as the integration of the semiconductor element and the higher functionality of the electronic device increase. In addition, since there is a demand for downsizing and thinning of equipment, a small and thin package capable of mounting semiconductor elements on a printed circuit board with high density is demanded. Furthermore, in a package of a method in which a semiconductor element is mounted on a lead frame and the both are connected by wire bonding, or a package in which a semiconductor element is mounted via a solder bump on an interposer formed of a multilayer substrate, the semiconductor As the operation speed of elements increases, delays in power supply and signal transmission are becoming a problem.
[0003]
In response to the above-described demands and problems, a semiconductor package schematically shown in FIG. 2 has been proposed. In FIG. 2, the substrate (1) has an opening and is arranged so as to surround the semiconductor element (2), and both are fixed using a sealing resin (3). Then, a multilayer wiring layer (7) is formed by sequentially laminating an insulating layer (5) and a wiring (6) on the internal connection terminal (4) side on the semiconductor element, and an input / output terminal is formed outside the multilayer wiring layer. It is a package in which (8) is joined with solder (9).
This package can be made thinner and lighter than the conventional package. Electrically, since the wiring distance between the semiconductor element (2) and the input / output terminal (8) is short, the inductance is reduced, the problem of signal delay and noise is eliminated, and the capacitor (10) is further connected to the semiconductor element (2). ), It is possible to cope with a rapid power supply accompanying high-frequency operation. Further, since the wiring (6) is formed directly on the internal connection terminal (4), connection members such as wires and solder bumps are unnecessary, and there is an advantage that high-density internal connection between the semiconductor element and the package is possible. is there.
[0004]
[Problems to be solved by the invention]
The package described above has a number of advantages. However, when the substrate (1) is formed of a resin material used as an insulator of a general printed circuit board, for example, an epoxy resin, a BT (bismaleimide triazine) resin, or a polyimide resin, due to a difference in thermal expansion between the semiconductor element and the substrate. There are problems in which the sealing resin (3) is peeled off and cracks are likely to occur in the interlayer connection (11) in the multilayer wiring layer due to thermal expansion and contraction of the substrate. Further, there is a problem that warp deformation is likely to occur due to insufficient rigidity of the substrate.
The present invention has been made in view of these problems in the above-described package structure, and an object of the present invention is to provide a semiconductor package that is thin and lightweight, excellent in internal connection reliability, and less warped.
[0005]
[Means for Solving the Problems]
The present inventor has found that the problem of connection reliability and warpage can be greatly improved by combining the resin layer and the low thermal expansion metal layer as the substrate, and has reached the present invention.
[0006]
That is, the present invention relates to a semiconductor element, a substrate disposed so as to surround the semiconductor element, wiring connected to the internal connection terminal on one surface side of the substrate and on the internal connection terminal side of the semiconductor element, A semiconductor package having a wiring layer in which an insulating layer is laminated, wherein the substrate has a resin layer and an average thermal expansion coefficient of 30 to 200 ° C. surrounding the semiconductor element of −5 ppm / ° C. to 10 ppm / ° C. This is a semiconductor package in which the low thermal expansion metal layer is combined.
[0007]
More preferably, it is a semiconductor package in which the hardness of the low thermal expansion metal layer is 200 to 400 in terms of Vickers hardness. More preferably, the low thermal expansion metal layer contains 27 to 52% by mass of nickel, and the balance is substantially an iron-nickel alloy composed of iron, or iron-nickel-cobalt in which the nickel is replaced with 20% by mass or less of cobalt. It is a semiconductor package which is one of the system alloys.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is described in detail below. As described above, an important feature of the present invention resides in that a low thermal expansion metal layer is formed on a substrate that bears the rigidity of the entire package.
The presence of a low thermal expansion metal layer increases rigidity and prevents warpage deformation, as well as thermal history during the manufacturing process of the package and the electronic equipment using the package, rapid temperature changes due to driving of semiconductor elements, temperature changes in the usage environment, etc. The occurrence of thermal stress in the package caused by the above can be reduced, and the connection reliability inside the package can be improved.
The low thermal expansion metal layer does not need to be a single layer, and a plurality of layers may be combined. In addition, the low thermal expansion metal layer may be disposed on the surface of the substrate or may be included in the substrate.
Such an arrangement position and the number of layers can be determined in consideration of an expansion characteristic of the resin layer constituting the substrate, an expansion characteristic of the wiring layer of the package, a heat radiation effect of the entire package, or the like.
[0009]
In the present invention, as the thermal expansion coefficient of the low thermal expansion metal layer disposed on the substrate, the average thermal expansion coefficient of 30 to 200 ° C. needs to be −5 ppm / ° C. or more and 10 ppm / ° C. or less. If it is lower than this thermal expansion range, the difference in thermal expansion from the resin layer, which is another member constituting the substrate, becomes large, and there is a possibility that peeling occurs at the interface between the low thermal expansion metal layer and the resin layer. On the other hand, if it is high, it is difficult to reduce the thermal expansion of the substrate, and the effect of reducing the difference in thermal expansion between the substrate and the semiconductor element cannot be sufficiently obtained. More preferably, it is in the range of 3 ppm / ° C. to 10 ppm / ° C.
Further, in the semiconductor package of the present invention, considering the reduction in thickness, the thickness of these low thermal expansion metal layers is preferably 5 to 500 μm, but is not particularly limited.
[0010]
As the low thermal expansion metal layer used in the present invention is harder, the rigidity of the substrate can be improved. However, when it is extremely hard, or when the difference in hardness from the resin used for the substrate becomes remarkably large, it becomes difficult to perform punching press or cutting of the opening. Therefore, the hardness of the low thermal expansion metal layer is desirably 200 to 400 in terms of Vickers hardness. More preferably, it is 210 or more and 300 or less.
Refractory metal materials such as molybdenum and tungsten can also be used as the low thermal expansion metal layer having the above-mentioned characteristics, but it is superior in workability compared to these metal materials and is relatively easily available. It is preferable to use an alloy.
[0011]
Specifically, an iron-nickel alloy containing 27 to 52% by mass of nickel with which low thermal expansion characteristics can be obtained, and the balance being substantially iron, or iron-nickel in which the nickel is replaced with 20% by mass or less of cobalt. -Cobalt-based alloy. More specifically, iron-36 mass% nickel alloy and iron-42 mass% nickel alloy represented by Invar alloy and 42 alloy, iron-50 mass% nickel alloy, iron-29 mass% nickel called Kovar A -17 mass% cobalt alloy is mentioned.
[0012]
The resin layer constituting the substrate of the present invention includes resin films such as epoxy, phenol, BT, polyimide, polyamide, fluororesin, and liquid crystal polymer, inorganic fibers such as glass, and organic fibers such as polyamide. A prepreg impregnated in a woven fabric or non-woven fabric made of the like can be used.
The low thermal expansion metal layer and the resin layer can be laminated and bonded to each other using temperature and pressure by, for example, a vacuum heating press.
If sufficient adhesion is not obtained, the low thermal expansion metal layer and the resin layer may be bonded via an adhesive layer as necessary. Further, a resin varnish may be directly coated on a low thermal expansion metal, dried and bonded to form a laminate of the low thermal expansion metal layer and the resin layer.
[0013]
It is also effective to roughen the surface as means for improving the adhesive strength on the low thermal expansion metal layer side and improve the adhesive strength with the resin by the anchor effect. As a roughening treatment method, an etching method using a chemical solution or a method of rolling using a roll having a rough surface and transferring it to the surface of the low thermal expansion metal layer is possible. It is also possible to improve the adhesion to the resin by copper plating on the surface of the low thermal expansion metal layer and further blackening to provide another metal layer. In particular, when an iron-nickel alloy or an iron-nickel-cobalt alloy is used as the low thermal expansion metal layer, it is preferable to apply copper plating because the surface is prevented from corrosion.
[0014]
FIG. 1 is a schematic sectional view showing an example of the semiconductor package of the present invention.
In FIG. 1, the substrate (1) is disposed so as to surround the semiconductor element (2), and both are fixed using a sealing resin (3). Then, the insulating layer (5) and the wiring (6) are sequentially laminated on the internal connection terminal (4) side on the semiconductor element to form the wiring layer (7), and the input / output terminal (8) is formed outside the wiring layer. ) With solder (9). Thus, the basic structure is the same as FIG. 2 which is the conventional structure described above.
The feature of the present invention relates to the structure of the substrate (1), not the substrate composed of resin only as in the prior art, but the resin layer (12) and the average thermal expansion coefficient of 30 to 200 ° C. is −5 ppm / ° C. or more and 10 ppm. The low thermal expansion metal layer (13) at / ° C. or less is combined. In FIG. 1, the wiring layer (7) has two insulating layers (5) and wirings (6). The number of these layers is determined as necessary, and each wiring layer may be one. Further, a multilayer wiring layer may be formed. In FIG. 1, the input / output terminal (8) shows the shape of a pin, but it can also take the form of a bump such as a solder ball.
[0015]
As a method for manufacturing a semiconductor package according to the present invention, for example, as shown in FIG. 3, (a) a laminate (14) comprising a resin layer (12) and a low thermal expansion metal layer (13) is prepared, and (b) A substrate (1) is manufactured by processing an opening (15) for mounting a semiconductor element. A laminated board can be manufactured by heat-pressing a resin layer and a low thermal expansion metal layer with a vacuum heating press or a heating laminate. Machining such as punching press or cutting can be applied to the opening.
Also, (c) the opening (15) is first formed in the low thermal expansion metal layer (13) by etching or machining, (d) the resin layer is then laminated to fill the opening with resin, e) When the resin portion corresponding to the opening is opened by machining, the dissimilar materials of the resin and the low thermal expansion metal are not exposed on the inner wall of the opening, and the processing is easy.
[0016]
Next, (f) the semiconductor element (2) is placed in the opening, and the substrate and the semiconductor element are bonded using the sealing resin (3). Then, (g) the insulating layer (5) is laminated on the side of the internal connection terminal (4) on the semiconductor element, and (h) a via hole (16) for interlayer connection is opened by laser processing. Subsequently, (i) the interlayer connection portion (11) and the wiring (6) are formed by copper plating to become the first layer of the multilayer wiring layer. The interlayer connection portion may be filled with a conductive paste. Furthermore, the steps (g) to (i) are repeated, and (j) the wiring layer (7) is formed. Thereafter, (k) the input / output terminal (8) and the capacitor (10) are joined via the solder (9) to obtain a semiconductor package having the basic structure of the present invention.
[0017]
In the present invention, FIG. 4 shows an example in which the low thermal expansion metal layer is arranged in multiple layers as a form in which the low thermal expansion metal layer is arranged on the substrate. When two low thermal expansion metal layers (13) are arranged as shown in FIG. 4, the two layers are separated from each other to bend more than a substrate (FIG. 1) including one low thermal expansion metal layer having the same volume ratio. The advantage of increased rigidity arises. Of course, the low thermal expansion metal layer can be further divided into multiple layers, and the low thermal expansion metal layer (13) may be exposed on the substrate surface.
Moreover, the example of this invention which reduced the area of the low thermal expansion metal layer exposed to the side surface of a board | substrate is shown in FIG. By including the low thermal expansion metal layer (13) in the resin layer (12), exposure of the resin / low thermal expansion metal interface is avoided, and the risk of corrosion and peeling at the joint interface between the two is greatly reduced. As shown in FIG. 6, the low thermal expansion metal layer can be further divided into multiple layers.
[0018]
FIG. 7 shows an example of the present invention in which a large number of holes (17) are formed in the low thermal expansion metal layer (13). A resin-resin bonding portion (18) is obtained in the hole, the bonding strength between the resin layer (12) and the low thermal expansion metal layer (13) is increased, and the durability as a semiconductor package is dramatically improved. The shape of the hole may be circular or rectangular, and the arrangement thereof may be a lattice shape or a staggered shape. The hole may be formed by drilling a low thermal expansion metal using a machining process such as etching or pressing. Further, as shown in FIG. 8, the low thermal expansion metal layer may be divided into multiple layers.
[0019]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor package that is thin and light, has excellent internal connection reliability, and has less warping deformation by constituting the substrate with a laminate of a resin layer and a low thermal expansion metal layer.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor package of the present invention.
FIG. 2 is a schematic cross-sectional view showing an example of a conventional semiconductor package.
FIG. 3 is a schematic view showing an example of a manufacturing process of a semiconductor package of the present invention.
FIG. 4 is a schematic cross-sectional view showing an example of a semiconductor package of the present invention.
FIG. 5 is a schematic cross-sectional view showing an example of a semiconductor package of the present invention.
FIG. 6 is a schematic cross-sectional view showing an example of a semiconductor package of the present invention.
FIG. 7 is a schematic cross-sectional view showing an example of a semiconductor package of the present invention.
FIG. 8 is a schematic cross-sectional view showing an example of a semiconductor package of the present invention.
[Explanation of symbols]
1. Substrate, 2. 2. semiconductor element; 3. Sealing resin Internal connection terminal, 5. 5. insulating layer; Wiring, 7. Wiring layer, 8. 8. Input / output terminal 10. solder Capacitors,
11. Interlayer connection, 12. Resin layer, 13. Low thermal expansion metal layer, 14. Laminated board,
15. Opening, 16. Via hole, 17. Hole, 18. Resin-resin joint

Claims (3)

半導体素子と、該半導体素子を取り巻く如く配置される基板と、該基板の一方の面側であって半導体素子の内部接続端子側に、該内部接続端子と接続される配線と絶縁層が積層されてなる配線層とを有する半導体パッケージであって、前記基板は、樹脂層と、前記半導体素子を取り巻く30〜200℃の平均熱膨張係数が−5ppm/℃以上10ppm/℃以下の低熱膨張金属層とが複合されていることを特徴とする半導体パッケージ。A semiconductor element, a substrate disposed so as to surround the semiconductor element, and a wiring and an insulating layer connected to the internal connection terminal are laminated on one surface side of the substrate and on the internal connection terminal side of the semiconductor element. The substrate includes a resin layer, and a low thermal expansion metal layer having an average coefficient of thermal expansion of 30 to 200 ° C. surrounding the semiconductor element of −5 ppm / ° C. to 10 ppm / ° C. A semiconductor package characterized by being combined. 低熱膨張金属層の硬さがビッカース硬さで200以上400以下であることを特徴とする、請求項1に記載の半導体パッケージ。The semiconductor package according to claim 1, wherein the low thermal expansion metal layer has a Vickers hardness of 200 or more and 400 or less. 低熱膨張金属層はニッケルを27〜52質量%含み、残部が実質的に鉄からなる鉄−ニッケル系合金、または前記ニッケルを20質量%以下のコバルトで置換した鉄−ニッケル−コバルト系合金のいずれかであることを特徴とする、請求項1または2に記載の半導体パッケージ。The low thermal expansion metal layer contains 27 to 52% by mass of nickel, and the balance is substantially an iron-nickel alloy composed of iron, or an iron-nickel-cobalt alloy in which the nickel is replaced with 20% by mass or less of cobalt. The semiconductor package according to claim 1 or 2, wherein
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007245393A (en) * 2006-03-14 2007-09-27 Toyobo Co Ltd Metal/resin laminate
JP2009032824A (en) * 2007-07-25 2009-02-12 Tdk Corp Electronic component-embedded board and method of manufacturing the same
JP2009032823A (en) * 2007-07-25 2009-02-12 Tdk Corp Electronic component-embedded board and method of manufacturing the same
US8261618B2 (en) * 2010-11-22 2012-09-11 General Electric Company Device for measuring properties of working fluids
JP2016219798A (en) * 2015-05-15 2016-12-22 サムソン エレクトロ−メカニックス カンパニーリミテッド. Electronic component package and package-on-package structure
US10109588B2 (en) 2015-05-15 2018-10-23 Samsung Electro-Mechanics Co., Ltd. Electronic component package and package-on-package structure including the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007245393A (en) * 2006-03-14 2007-09-27 Toyobo Co Ltd Metal/resin laminate
JP2009032824A (en) * 2007-07-25 2009-02-12 Tdk Corp Electronic component-embedded board and method of manufacturing the same
JP2009032823A (en) * 2007-07-25 2009-02-12 Tdk Corp Electronic component-embedded board and method of manufacturing the same
JP4518114B2 (en) * 2007-07-25 2010-08-04 Tdk株式会社 Electronic component built-in substrate and manufacturing method thereof
JP4518113B2 (en) * 2007-07-25 2010-08-04 Tdk株式会社 Electronic component built-in substrate and manufacturing method thereof
US8237059B2 (en) 2007-07-25 2012-08-07 Tdk Corporation Electronic component-embedded board and method of manufacturing the same
US8261618B2 (en) * 2010-11-22 2012-09-11 General Electric Company Device for measuring properties of working fluids
JP2016219798A (en) * 2015-05-15 2016-12-22 サムソン エレクトロ−メカニックス カンパニーリミテッド. Electronic component package and package-on-package structure
US10109588B2 (en) 2015-05-15 2018-10-23 Samsung Electro-Mechanics Co., Ltd. Electronic component package and package-on-package structure including the same

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