JP2005302968A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board that has no core substrate and can be reduced in warping. <P>SOLUTION: The wiring board has a laminate BU formed by alternatively laminating two or more dielectric layers and two or more conductor layers upon another so that the first and second main surfaces MP1 and MP2 of the laminate BU may be formed of dielectric layers, a plurality of metallic terminal pads PD1 and PD2 formed on the first and second main surfaces MP1 and MP2, and a reinforcing frame ST which secures flatness by reinforcing the laminate BU. Semiconductor chips and the reinforcing frame ST are arranged on the first main surface MP1 and at least part of the metallic terminal pads PD1 and PD2 are electrically connected to internal conductor layers positioned in the laminate BU through via holes. At the same time, the metallic terminal pads PD1 and PD2 and semiconductor chips are flip-chip connected to each other through soldered connections and the coefficients of thermal expansion of all dielectric layers are adjusted to 15-40 ppm/°C and the coefficient of thermal expansion of the reinforcing frame ST is also adjusted to 15-40 ppm/°C. Since the difference between the coefficients of thermal expansion of the dielectric layers and reinforcing frame ST is small, the warping of the wiring board can be reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring board.

  In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration has rapidly progressed in electronic components such as IC chips and LSIs. There is a demand for higher-density wiring and multi-terminals than ever before.

  As such a package substrate, a build-up multilayer wiring substrate is currently used. The build-up multilayer wiring board uses the rigid property of an insulating core substrate (glass epoxy substrate such as FR-4) in which a reinforcing fiber is impregnated with a resin, and a dielectric layer and a conductor are formed on both main surfaces thereof. A build-up layer in which layers are alternately arranged is formed. In such a build-up multilayer wiring board, high-density wiring is realized in the build-up layer (hereinafter also referred to as a laminate), while the core board plays a role of reinforcement. Therefore, the core substrate is configured to be very thick compared to the multilayer body, and wiring (for example, referred to as a through-hole conductor) for establishing electrical connection between the multilayer bodies disposed on the respective main surfaces is provided in the core substrate. It is formed penetrating in the thickness direction. However, at the present time when the signal frequency to be used has become a high frequency band exceeding 1 GHz, there is a problem that the wiring penetrating such a thick core substrate contributes as a large inductance.

Therefore, in order to solve such a problem, a wiring board has been proposed that enables high-density wiring by not having a core board as in Patent Document 1 below. In such a wiring board, since the core board is omitted, the entire wiring length is short, which is suitable for use in high frequency applications. In order to manufacture such a wiring board, as described in paragraphs 0012 to 0029 and FIGS. 1 to 4 of Patent Document 1, after forming a laminate on a metal plate, the metal plate is etched. Thus, only a thin film laminate is obtained. And this laminated body is used as a wiring board.
JP 2002-26171 A

  In the thin film laminate separated from the metal plate, a reinforcing frame (hereinafter also referred to as a stiffener) for securing the rigid property of the wiring board is installed on the IC connection side. Copper alloy or SUS304 is used as the material of the reinforcing frame, and epoxy resin is used as the dielectric layer. When connecting the reinforcing frame to the laminate, an adhesive is used, and vacuum curing is performed at about 150 ° C. in order to solidify the adhesive. The thermal expansion coefficient of the copper alloy used for the reinforcing frame is about 17.7 ppm / ° C. The dielectric layer is mainly composed of an epoxy resin, and its thermal expansion coefficient is about 55 ppm / ° C. In the conventional wiring board, there is a problem that the wiring board is warped due to the difference in the coefficient of thermal expansion. In other words, when the vacuum curing is finished and the cooling is completed, the reinforcing frame is slightly shrunk, but the wiring board including the dielectric layer is shrunk so that it has a bow shape as shown in FIG.

  On the other hand, there is also a warp caused by a difference in wiring density of the conductor layer. The conductor layer has a different wiring density depending on each layer. For example, the conductor layer on the semiconductor chip connection side has a low wiring density, and the conductor layer on the motherboard connection side has a high wiring density. This is because the metal terminal pads on the semiconductor chip connection side are generally made small. When a copper alloy is used for the conductor layer, the coefficient of thermal expansion is about 17.7 ppm / ° C., and the dielectric layer mainly composed of epoxy resin is about 55 ppm / ° C. Therefore, a difference in thermal expansion coefficient occurs between the surface on the semiconductor chip connection side where the wiring density is low and the surface on the motherboard connection side where the wiring density is high, causing warpage. Since a high temperature of about 170 ° C. is applied in the build-up process, stress is applied to the cooled wiring board after the build-up process is completed, and warping occurs. Since the metal terminal pad for connecting the semiconductor chip is disposed in the central portion of the wiring board, it is deformed so that the central portion is recessed as shown in FIG.

  The present invention has been made in the background as described above, and includes a laminated body in which conductor layers and dielectric layers are alternately laminated, a reinforcing frame that reinforces the laminated body to ensure flatness, It is an object to provide a wiring board that can be reduced.

Means for Solving the Problems and Effects of the Invention

  In order to solve the above problems, a wiring board of the present invention is a wiring board that does not have a core board and connects a semiconductor chip, and the first main surface and the second main surface are formed of a dielectric layer. A laminate in which two or more dielectric layers and two or more conductor layers are alternately laminated, and a plurality of metal terminal pads formed on the first main surface and the second main surface; A reinforcing frame that reinforces the laminated body to ensure flatness, and the semiconductor chip and the reinforcing frame are disposed on the first main surface, and at least a part of the metal terminal pads are: Conductive to the internal conductor layer located in the multilayer body through vias, and the metal terminal pads and the semiconductor chip are flip-chip connected through solder connection parts, the thermal expansion coefficient of all the dielectric layers 15 ppm / ° C or higher and 40 ppm / ° C or lower , And the is mainly characterized in that the thermal expansion coefficient of said reinforcing frame is 15 ppm / ° C. or higher 25 ppm / ° C. or less.

  In the wiring board of the present invention, the thermal expansion coefficients of all the conductor layers are 15 ppm / ° C. or more and 25 ppm / ° C. or less.

  Further, in the wiring board of the present invention, the wiring density of the conductor layer closest to the first main surface is 50% or more and 90% or less, and the wiring density of the conductor layer closest to the second main surface is 50% or more. 90% or less.

  When the warp generated in the wiring board is caused by the difference in the thermal expansion coefficient between the dielectric layer and the reinforcing frame, the materials may be combined so that the respective thermal expansion coefficients are substantially the same. In the present invention, the difference in the thermal expansion coefficient between the dielectric layer and the reinforcing frame is 25 ppm / ° C. or less, thereby providing a wiring board with less warpage. Warpage occurs when the difference in thermal expansion coefficient is 25 ppm / ° C. or more. Specifically, it is desirable that the thermal expansion coefficient of all the dielectric layers is 15 ppm / ° C. or more and 40 ppm / ° C. or less, and the thermal expansion coefficient of the reinforcing frame is 15 ppm / ° C. or more and 25 ppm / ° C. or less. For example, when pure copper or a copper alloy having a thermal expansion coefficient of 16 ppm / ° C. or higher and 20 ppm / ° C. or lower is used as the material of the reinforcing frame, a material having a thermal expansion coefficient of 20 ppm / ° C. or higher and 30 ppm / ° C. or lower is used as the dielectric layer. That's fine. An example of such a material is ABF-GX TH3 (trade name: manufactured by Ajinomoto Fine Techno Co., Ltd.).

  When the warp of the wiring board is caused by the difference in the wiring density of the conductor layer, the warp can be reduced by making the thermal expansion coefficients of the conductor layer and the dielectric layer substantially the same. In the present invention, a wiring board with less warpage is provided by setting the difference in thermal expansion coefficient between the dielectric layer and the conductor layer to 25 ppm / ° C. or less. Specifically, the thermal expansion coefficients of all the dielectric layers are 15 ppm / ° C. or more and 40 ppm / ° C. or less, and the thermal expansion coefficients of the conductor layers constituting the wiring are 15 ppm / ° C. or more and 25 ppm / ° C. or less. Is desirable. Although it is desirable that the thermal expansion coefficients of the dielectric layer and the conductor layer are completely the same, in reality, it is difficult to apply such a combination of materials. Therefore, warpage can be further reduced by reducing the difference in thermal expansion coefficient and reducing the difference in wiring density of the conductor layer. Specifically, the wiring density of the conductor layer closest to the main surface on the semiconductor chip connection side is set to 50% or more and 90% or less, and the wiring density of the conductor layer farthest from the main surface on the semiconductor chip connection side is set to 50% or more. 90% or less. In this way, the difference in wiring density between the conductor layers is 40% or less, and the warpage can be reduced.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
Fig.1 (a) is a schematic sectional drawing which shows one Embodiment of this invention. Dielectric layers and conductor layers are alternately stacked to form a stacked body BU. On the first main surface MP1, a protruding metal terminal (solder bump) FB made of a well-known solder for connecting to the semiconductor chip is formed. Further, a reinforcing frame (stiffener) ST for reinforcing the wiring substrate 100 and ensuring flatness is bonded to the first main surface MP1. Since the wiring board of the present invention does not have a core board, it is easy to bend unless a reinforcing frame is used, and it becomes difficult to connect the solder bump FB and the semiconductor chip.

  Next, it will be described in more detail with reference to FIG. FIG.1 (b) is principal part sectional drawing of the wiring board of this invention. The laminate 100 is formed by alternately laminating conductor layers M1 to M4 and dielectric layers B1 to B4. A solder resist SR is formed on the surface of the dielectric layer B4. The conductor layers M1 to M4 are mainly composed of copper. A plurality of metal terminal pads PD1 are formed on the first main surface MP1. The metal terminal pad PD1 constitutes a solder land that is a pad for flip-chip connection of a semiconductor chip or the like. The metal terminal pad PD2 on the second main surface MP2 side is used as a back surface land for connecting the wiring board itself to the mother board by a pin grid array (PGA) or a ball grid array (BGA). On the other hand, the conductor layers M1 and M2 are interconnected by a via V1. Similarly, the conductor layers M2 and M3 are interconnected by a via V2, and the conductor layers M3 and M4 are interconnected by a via V3. In this manner, an electrical conduction path from the solder bump FB to the metal terminal pad PD2 is formed.

  Compared with the metal terminal pad PD1 for connecting the semiconductor chip, the metal terminal pad PD2 for connecting the mother board is made larger. Therefore, the wiring density of the conductor layer M1 is low, and the wiring density of the conductor layer M4 is high. As described above, this difference in wiring density causes a warp.

  As shown in FIG. 2A, the metal terminal pads PD1 are arranged in a lattice pattern at the central portion of the wiring substrate 1, and the chip mounting portions 40 are formed together with the solder bumps FB formed thereon. Further, as shown in FIG. 2B, the metal terminal pads PD2 are also arranged in a grid pattern.

  The laminated body BU described above can be manufactured, for example, by stacking and forming a metal substrate using a known build-up method, and removing the metal plate by etching. FIG. 3 is a conceptual diagram showing the occurrence of warping when the reinforcing frame is bonded. In this embodiment, an epoxy resin is used as the dielectric layer. As shown in FIG. 3, a reinforcing frame ST for ensuring flatness is bonded to the first main surface MP1 side of the stacked body BU. Adhesion of the reinforcing frame ST is performed using an adhesive, and a high temperature (for example, about 150 ° C.) is applied to solidify the adhesive. Here, since the epoxy resin is used as the dielectric layers B1 to B4, the thermal expansion coefficient thereof is about 55 ppm / ° C. The value is significantly different from the coefficient of thermal expansion of the reinforcing frame ST, compared with 16 ppm / ° C. or more and 20 ppm / ° C. or less. Thus, when the difference in thermal expansion coefficient is large, the contraction rate of the laminated body BU is large when cooled, so that it is deformed into an arcuate shape. However, if the material of the dielectric layers B1 to B4 is changed so that the difference between the thermal expansion coefficient thereof and the thermal expansion coefficient of the reinforcing frame ST is 25 ppm / ° C. or less, the warpage is reduced. Specifically, the thermal expansion coefficient of all the dielectric layers is 15 ppm / ° C. or more and 40 ppm / ° C. or less, and the thermal expansion coefficient of the reinforcing frame is 15 ppm / ° C. or more and 25 ppm / ° C. or less.

  FIG. 4 is a schematic cross-sectional view for explaining the occurrence of warpage due to the wiring density between conductor layers. In FIG. 4, epoxy resin is used as the dielectric layers B1 to B4. When the metal plate is removed by etching to separate the stacked body BU, warpage occurs. As described above, the density of the conductor layer is different between the first main surface side and the second main surface side. The first main surface MP1 side (flip chip connection side) with a low wiring density has a high thermal expansion coefficient, and the second main surface MP2 side (motherboard connection side) with a high wiring density has a low thermal expansion coefficient. At the time of the build-up process, a high temperature state of about 170 ° C. is obtained. However, after cooling, if the metal plate is removed by etching to separate the stacked body BU, the central portion is recessed. The reason why the central portion is particularly recessed is that a metal terminal pad is disposed in the central portion. However, if the difference between the thermal expansion coefficient of the dielectric layer and the thermal expansion coefficient of the conductor layer is 25 ppm / ° C. or less, such warpage is reduced. Specifically, the thermal expansion coefficients of all dielectric layers are 15 ppm / ° C. or more and 40 ppm / ° C. or less, and the thermal expansion coefficients of all conductor layers are 15 ppm / ° C. or more and 25 ppm / ° C. or less. The wiring density of the conductor layer M1 closest to the first main surface is set to 50% or more and 90% or less, and the wiring density of the conductor layer M4 closest to the second main surface is set to 50% or more and 90% or less. More preferably, the difference in wiring density between the conductor layers M1 and M4 is 40% or less.

  As shown in FIG. 4, in the method of laminating the laminated body BU on the metal plate and then removing the metal plate by etching, it is necessary to maintain the strength of the metal plate as a support base. It needs to be about 8m. In this case, a relatively long time of about 30 minutes is required to remove the metal plate by etching. Such a problem can be solved by the following manufacturing method. 5 and 6 show an example of a method for manufacturing a wiring board. This manufacturing method is characterized in that it uses a metal foil contact body in which metal foils M1 and M1 'are in close contact. In step 1, the laminated body BU is formed on the base dielectric sheet 21 formed on the support substrate 20. Further, a metal foil adhesion body is disposed so as to be included in the main surface of the base dielectric sheet 21, and a first dielectric layer B2 is disposed so as to wrap the metal foil adhesion body. And dielectric material layer B2-B4 and conductor layer M2-M4 are laminated | stacked on the metal foil adhesion body using the well-known buildup process. Pure copper or a copper alloy having a thermal expansion coefficient of 16 ppm / ° C. to 20 ppm / ° C. is used for the conductor layer, and a polymer material having a thermal expansion coefficient of 20 ppm / ° C. to 30 ppm / ° C. is used for the dielectric layer. Next, the peripheral part (broken line part in the figure) of the laminated body BU is removed, and the end surface 101 of the laminated body is exposed (step 2). Then, the laminated body BU is separated from the support base 20 and the base dielectric sheet 21 by peeling the metal foil adhesion body (step 3). Next, the metal foil M1 attached to the laminated body BU side is patterned and etched to form the metal terminal pad PD1 on the semiconductor chip connection side (step 4). That is, the metal foil M1 is used as a conductor layer for constituting the metal terminal pad PD1. Thereafter, the dielectric layer B1 is laminated on the metal terminal pad PD1 side and selectively etched so that the metal pad PD1 is opened. When the reinforcing frame is bonded to the semiconductor chip connection side (PD1 side) of the laminated body BU thus formed, the wiring substrate 1 having the structure shown in FIGS. 1A and 1B is formed. According to the above method, since it is not necessary to etch the metal plate, the process time can be shortened. Further, since the difference in coefficient of thermal expansion between the conductor layer and the dielectric layer is small, warpage can be reduced.

  In order to confirm the effect of the present invention, the following experiment was conducted. First, a thin film stack BU having the structure of FIG. 1B was obtained using the above-described manufacturing method. In Examples belonging to the present invention, ABF-GX TH3 (trade name: manufactured by Ajinomoto Fine Techno Co., Ltd.) having a thermal expansion coefficient of 23 ppm / ° C. was used as the dielectric layers B1 to B4. On the other hand, ABF-GX Code 3 (trade name: manufactured by Ajinomoto Fine Techno Co., Ltd.) mainly composed of an epoxy resin having a thermal expansion coefficient of 55 ppm / ° C. is used as the dielectric layers B1 to B4 in the sample of the comparative example outside the present invention. used. Thereafter, the reinforcing frame ST was bonded at 150 ° C. to the first main surfaces of the examples and comparative examples. In each sample, a copper alloy having a thermal expansion coefficient of 17.7 ppm / ° C. was used as a material for the conductor layers M1 to M4 and the reinforcing frame ST. The wiring densities of the example and the comparative example were 60% on the semiconductor chip connection side and 80% on the motherboard connection side. The contents described above are summarized in Table 1.

  The results of measuring the amount of warpage of each sample are shown in FIGS. 7 (a) and 7 (b). FIG. 7A shows the result measured before bonding the stiffener, and FIG. 7B shows the result measured after bonding the stiffener. For each sample, the height of 25 points from the motherboard connection side was measured, and the value that maximized the difference in the measured values was taken as the warp value. 6 samples each for FIG. 7A and 12 samples each for FIG. 7B. From FIG. 7A, it can be seen that the amount of warpage in the example and the comparative example is about the same before the stiffener is bonded, but the variation in the amount of warpage is smaller in the example. Further, FIG. 7B shows that after the stiffener is bonded, the amount of warpage of the example is smaller than that of the comparative example, which is improved.

  Further, FIG. 8 shows the result of measuring the warpage amount of the semiconductor chip area of the wiring board. FIG. 8A is a graph showing the amount of warpage of the semiconductor chip area as seen from the motherboard connection side. The height of only the semiconductor chip area was measured, and the value that maximized the difference in the measured values was taken as the warpage value. FIG. 8B is a graph showing the flatness of the solder bump FB. The height of 25 solder bumps FB per sample was measured, and the value that maximized the difference in the measured values was taken as the warp value. In FIGS. 8A and 8B, 12 samples each were measured after the stiffener was bonded. FIG. 8A shows that the amount of warpage of the semiconductor chip area is smaller in the example. Further, from FIG. 8B, it can be seen that the flatness of the solder bumps is improved in the example compared to the comparative example.

BRIEF DESCRIPTION OF THE DRAWINGS (a) schematic sectional drawing and (b) principal part sectional drawing which show one Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS (a) Front view and (b) Back view which show one Embodiment of this invention. Sectional drawing which shows curvature generation | occurrence | production when the reinforcement frame was adhere | attached. Sectional drawing which shows generation | occurrence | production of the curvature resulting from the wiring density between conductor layers. Process drawing which shows an example of the manufacturing method of a wiring board. Process drawing following FIG. The graph which shows the relationship between the material of a dielectric material layer, and curvature amount. The graph which shows the relationship between the material of a dielectric material layer, and the curvature amount of a semiconductor chip area.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 20 Support base 21 Base dielectric layer BU Laminate MP1 1st main surface MP2 2nd main surface M1 1st conductor layer (metal foil)
B1 First dielectric layer PD1 Metal terminal pad ST Reinforcement frame FB Solder bump

Claims (3)

A wiring board that does not have a core board and connects a semiconductor chip,
A laminate in which two or more dielectric layers and two or more conductor layers are alternately laminated so that the first main surface and the second main surface are formed of a dielectric layer;
A plurality of metal terminal pads formed on the first main surface and the second main surface;
A reinforcing frame that reinforces the laminate and ensures flatness;
The semiconductor chip and the reinforcing frame are disposed on the first main surface,
At least a part of the metal terminal pad is electrically connected to an internal conductor layer located in the multilayer body through a via,
The metal terminal pad and the semiconductor chip are flip-chip connected via a solder connection portion,
The thermal expansion coefficient of all the dielectric layers is 15 ppm / ° C. or more and 40 ppm / ° C. or less,
A wiring board, wherein the reinforcing frame has a thermal expansion coefficient of 15 ppm / ° C. or more and 25 ppm / ° C. or less. The wiring board according to claim 1, wherein the thermal expansion coefficient of all the conductor layers is 15 ppm / ° C. or more and 25 ppm / ° C. or less. The wiring density of the conductor layer closest to the first main surface is 50% to 90%, and the wiring density of the conductor layer closest to the second main surface is 50% to 90%. Or the wiring board of Claim 2.