JP3241140B2 - Semiconductor device and chip deformation prevention method - Google Patents

Abstract

PURPOSE:To provide a highly reliable semiconductor device having a superior thermal cycle characteristic, and to provide a method for preventing the deformation of a chip to obtain such a semiconductor device. CONSTITUTION:A semiconductor device is provided with a mounting board 3, and a semiconductor chip 1 which is electrically connected to the board 3 via bump electrodes 2. A polyimide film 5A is sandwiched between the chip 1 and the board 3, and the chip 1 and the board 3 are adhered to each other. An adjusting plate 7A is disposed on the top of the chip 1, whereby the flexure and deformation of the chip 1 is adjusted. With this construction, the chip 1 and the board 3 are bonded to each other by the film 5A, and hence the expansion and contraction of the board 3 induces the flexure and deformation of the chip 1. For this reason, the concentration of stress on the bump electrode 2 is suppressed, and a thermal cycle characteristic is improved. The adjusting plate 7 disposed on the chip 1 simultaneously makes it possible to solve the problem of the cracking of the chip 1 caused by the flexure and deformation of the chip 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device mounted on a mounting board.

[0002]

2. Description of the Related Art Conventionally, there is a flip-chip type semiconductor device as a semiconductor device used for a multi-pin product.
FIG. 9 shows a flip-chip type semiconductor device.
(A) is a cross-sectional view of an ideal product, and (b) is a cross-sectional view of an actual product.

[0003] As shown in FIG.
A bump electrode 2 is provided on the surface of the substrate. The bump electrode 2 is connected to a wiring pattern 4 formed on a mounting substrate 3 by soldering.

[0004] The material constituting the chip 1 and the material constituting the substrate 3 are different from each other, and there is a difference between the respective coefficients of linear expansion. For example, if the coefficient of linear expansion of the substrate 3 is larger than that of the chip 1, when the device is returned to room temperature after the completion of the mounting process, the substrate 3 is greatly shrunk, and the bump electrodes 2 are formed as shown in FIG. Distorted.

After commercialization, the chip 1 generates heat every time it is operated. Therefore, the tip 1 is expanded /
Repeat the contraction. The application of such a heat cycle causes the bump electrode 2 to repeatedly generate strain, eventually causing fatigue and becoming brittle. Therefore, the reliability of the semiconductor device is deteriorated.

[0006]

As described above, the conventional semiconductor device has a structure in which the chip 1 is supported only on the substrate 3 by the bump electrodes 2, and the bump electrodes 2 reduce the stress caused by the difference in linear expansion coefficient. Receive it directly. For this reason, stress concentrates on the bump electrode 2, and in particular, fatigue (thermal fatigue) due to a thermal cycle is likely to occur.

The present invention has been made in view of the above points, and has as its object to provide a semiconductor device having good thermal cycle characteristics and high reliability, and a chip deformation for obtaining such a semiconductor device. It is to provide a prevention method.

[0008]

A semiconductor device according to the present invention comprises a semiconductor chip flip-chip connected on a mounting substrate via a conductive electrode, and a conductive chip between the chip and the mounting substrate. A fixing means for fixing the provided chip to the mounting substrate; and an adjusting means for adjusting the bending of the chip.
It is characterized in that it is provided on a chip facing the step .

Further, in the chip deformation preventing method according to the present invention, a fixing means for fixing the chip and the mounting substrate is provided between the chip and the mounting substrate in addition to the conductive electrodes, so that the chip is expanded and contracted in accordance with the expansion and contraction of the mounting substrate. It is characterized in that the chip is bent, and the deformation of the chip is prevented by providing an adjusting means for adjusting the bending of the chip so as to offset the bending by the fixing means on the chip in opposition to the fixing means .

[0010]

According to the semiconductor device and the chip deformation preventing method having the above-described structures, the chip is bent and deformed in accordance with the expansion and contraction of the mounting substrate by the fixing means provided between the chip and the mounting substrate. Can be distributed not only to the conductive electrodes but also to the chip itself. Therefore, stress does not concentrate on the conductive electrode, and the conductive electrode has a structure that is less likely to cause thermal fatigue. further,
When the tip is bent and deformed, the tip may be broken. In order to improve this point, an adjustment means for adjusting the bending deformation of the chip is provided on the chip to correct the bending of the chip,
Or try to relax.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. In this description, common portions will be denoted by common reference symbols throughout the drawings, and redundant description will be avoided.
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

As shown in FIG. 1, a bump electrode 2 is provided on a surface of a semiconductor chip 1. The bump electrode 2 is connected to a wiring pattern 4 formed on a mounting substrate 3 by soldering. The substrate 3 is made of alumina. A polyimide film 5A is sandwiched between the surface of the chip 1 and the substrate 3. An adhesive is attached to the front and back surfaces of the polyimide film 5A, respectively, and the front and back surfaces are bonded to the chip 1 and the substrate 3, respectively. Thus, the chip 1 and the substrate 3 are fixed to each other. On the back surface of the chip 1, an adjusting plate 7A is attached via an adhesive layer 6 made of an insulating and low elastic modulus adhesive. In this embodiment, the heat dissipation of the chip 1 is also considered by using a copper plate for the adjustment plate 7A. When the substrate 3 is made of alumina and the adjusting plate 7A is made of copper, the thickness of the adjusting plate 7A is made smaller than the thickness of the substrate 3 due to the linear expansion coefficient.

Next, a method of adjusting the bending deformation of the chip by the adjusting plate will be described. This adjusting method includes the following steps: substrate 3, adhesive layer 5 (corresponding to polyimide film 5A in FIG. 1),
Assuming that the portion including the chip 1, the adhesive layer 6, and the adjusting plate 7 is a multilayer composite "beam", the calculation is performed by applying a calculation formula based on material mechanics. Prior to the description of the adjustment method, the thermal stress of the multilayer composite beam model will be described with reference to FIG. FIG. 2 is a diagram schematically showing a multilayer composite beam. The stress of the i-th layer of the multilayer composite beam as shown in FIG. 2 can be expressed by the following equation.

[0014]

(Equation 1)

In the above equation, σ _i is the stress of the i-th layer, ε _i
The i layer of the thermal strain, (t-δ) / ρ the coordinates between the first distortion by bending of the i layer, t is t _{i + 1} ~t _i, [delta] is the neutral line coordinates,
ρ is the radius of curvature, and E _i is the Young's modulus of the i-th layer. Here, the thermal strain of the i-th layer is represented by the following equation.

[0016]

(Equation 2)

Assuming that the coordinate δ and the radius of curvature ρ of the neutral line are δ = B / A and ρ = C / A, respectively, A = −6 [ΣE _j ε _j (t _{j + 1} −t _j ) · ΣE _j (T _{j + 1} ² −t _j ² ) −ΣE _j ε _j (t _{j + 1} ² −t _j ² ) · ΣE _j (t _{j + 1} −t _j )] B = −4ΣE _j ε _j (t _{j + 1} −t _j ) · ΣE _j (t _{j + 1} ³ −t _j ³ ) + 3ΣE _j ε _j (t _{j + 1} ² −t _j ² ) · ΣE _j (t _{j + 1} ² −t _j ² ) C = 3 [ΣE _j (t _{j + 1} ² −t _j ² )] ² -4ΣE _j (t _{j + 1} ³ −t _j ³ ) · ΣE _j (t _{j + 1} −t _j ).

FIGS. 3A and 3B schematically show a cross-sectional structure of a semiconductor device according to the present invention. FIG. 3A shows a state where a chip 1 is mounted on a substrate 3 and FIG. 1 shows a stage in which the adjustment plate 7 is mounted on each of the components.

Assuming that the structure shown in FIG. 3A is a “beam”, the stress and warpage generated in the chip 1 are calculated as follows based on the above-described multi-layer composite beam model based on the material dynamics. The material properties are as shown below.

Chip 1: thickness t 1 = 0.6 mm, linear expansion coefficient α 1 = 0.35 ×
Ten^-Five/ ° C, Young's modulus E1 = 17000 kg / mm^Two  Adhesive layer 5: thickness t2 = 0.2 mm, coefficient of linear expansion α2 = 5.00 x
Ten^-Five/ ° C, Young's modulus E2 = 100 kg / mm^Two  Substrate 3: thickness t3 = 1.0 mm, coefficient of linear expansion α3 = 1.60 x
Ten^-Five/ ° C, Young's modulus E3 = 2000 kg / mm^Two  The load condition is -200 ° C (that is, the temperature is lowered by 200 ° C).
).

According to such a condition, in the structure shown in FIG. 3A, 8 kg / mm ² Also tensile stress occurs. The lower surface is compressed. Radius of curvature is -5
08mm, and if the size of chip 1 is 10mm,
It also bends 25 μm.

Therefore, as shown in FIG. 3B, an adjusting plate 7 is attached to the upper surface of the chip 1 to improve the stress generated in the chip 1 and the overall bending. The board is a copper plate,
When the optimum value of the thickness tx is obtained, the following is obtained.
The material properties are as shown below.

Chip 1: thickness t1 = 0.6 mm, coefficient of linear expansion α1 = 0.35 ×
Ten^-Five/ ° C, Young's modulus E1 = 17000 kg / mm^Two  Adhesive layer 5: thickness t2 = 0.2 mm, coefficient of linear expansion α2 = 5.00 x
Ten^-Five/ ° C, Young's modulus E2 = 100 kg / mm^Two  Substrate 3: thickness t3 = 1.0 mm, coefficient of linear expansion α3 = 1.60 x
Ten^-Five/ ° C, Young's modulus E3 = 2000 kg / mm^Two  Adjustment plate 7: thickness tx (described below), coefficient of linear expansion αx = 1.70 ×
Ten^-Five/ ° C, Young's modulus Ex = 11000kg / mm^Two  Adhesive layer 6: thickness ty = 0.2 mm, coefficient of linear expansion αy = 5.00 ×
Ten^-Five/ ° C, Young's modulus Ey = 100 kg / mm^Two  The load condition is -200 ° C (that is, the temperature is lowered by 200 ° C).
).

According to such conditions, the thickness tx is set to 0.3 m
If m, the stress generated in the chip is all compressive. The radius of curvature is 5920 mm, and it bends in the opposite direction (upper surface side). Further, when the plate thickness tx is 0.2 mm, all the stresses generated in the chip are also compressive stresses, and the radius of curvature is -3594 mm. This shows that the tip does not bend when the thickness of the adjusting plate is between 0.2 mm and 0.3 mm. However, in either case, the stress generated in chip 1 is -15 kg / mm ² This is a compressive stress of a certain degree, and no tensile stress is generated, so that the chip 1 is not broken.

Incidentally, the breaking strength of the chip surface (element formation surface) is 20 kg / mm ² tensile. Degree, compression 30kg / mm ² Despite that, the back surface of the chip is processed, and the breaking strength is 8kg / mm.
^Two Degree, compression 30kg / mm ² It is a degree and is weak to tension.

FIGS. 4A and 4B show a semiconductor device according to a second embodiment of the present invention. FIG. 4A is a plan view showing the arrangement of bump electrodes, and FIG. It is sectional drawing which follows the bb line.

As shown in FIGS. 4A and 4B, the bump electrodes 2 are arranged only on the outer periphery of the chip 1,
Are bonded to the substrate 3 via the bump electrodes 2. Further, the chip 1 is bonded to the substrate 3 via the bonding layer 5B. The adhesive layer 5B is an insulating resin (for example, silicone). On the back surface of the chip 1, a plastic plate having a larger linear expansion coefficient than that of the chip 1 is adhered as an adjusting plate 7B via an adhesive layer 6.

In the structure according to the second embodiment, the space between the chip 1 and the substrate 3 can be widened because the space between the chip 1 and the substrate 3 is filled with the adhesive layer 5B made of insulating resin. Can be increased.

FIGS. 5A and 5B are views showing a semiconductor device according to a third embodiment of the present invention. FIG. 5A is a plan view showing the arrangement of bump electrodes, and FIG. 5B is a view in FIG. It is sectional drawing which follows the bb line.

As shown in FIGS. 5A and 5B, the bump electrodes 2 are arranged in a concentrated manner on a part of the chip 1 surface. In this embodiment, the bump electrodes 2 have a grid shape and are concentrated on one corner of the chip 1. The other three corners are provided with dummy bumps 8 unrelated to signal transmission. The dummy bump 8 does not transmit a signal,
The size is made larger than that of the bump electrode 2 in order to improve heat transfer. The chip 1 is bonded to the substrate 3 by the bump electrodes 2 and the dummy bumps 8. Further, the chip 1 is also adhered to the substrate 3 by the adhesive layer 5B. The adhesive layer 5B in this embodiment is an insulating adhesive (for example, an epoxy resin). On the back surface of the chip 1, the same material as the chip 1 (for example, silicon) having a size larger than that of the chip 1 is adhered via an adhesive layer 6 as an adjustment plate 7C.

In the configuration according to the third embodiment, since the bump electrodes 2 are arranged intensively at a part on the surface of the chip 1, the fatigue progress of the bump electrodes 2 can be suppressed. This is because when the bump electrode 2 is provided on the outer periphery of the chip 1, the difference in distortion between the chip 1 and the substrate 3 increases, but when the bump electrode 2 is partially concentrated so as to be off the outer periphery of the chip 1, the distortion is small. This is because the difference can be reduced.

FIGS. 6A and 6B are views showing a semiconductor device according to a fourth embodiment of the present invention. FIG. 6A is a plan view showing the arrangement of bump electrodes, and FIG. It is sectional drawing which follows the bb line.

From the viewpoint described in the third embodiment, as shown in FIGS. 4A and 4B, the bump electrodes 2 are formed in a grid shape and concentrated at the center of the chip 1. You may do it. The effect is that the fatigue progress of the bump electrode 2 can be suppressed as in the third embodiment.
In this embodiment, an apparatus having a small heat value is used as an example, so that no dummy bump is provided, and a plastic plate 7B is used as an adjusting plate. In addition, the arrangement pattern of the bump electrodes 2 in the third and fourth embodiments is not only grid-shaped but also
It may be staggered. FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

As shown in FIG. 7, a plurality of chips 1-1, 1
In this case, the adjusting plate 7 is shared by a plurality of chips 1-1 and 1-2. Thus, even if the adjusting plate 7 is shared by the plurality of chips 1-1 and 1-2, each of the chips 1-1 and 1-2 can prevent destruction due to bending deformation. Note that a copper plate, plastic, silicon, or the like can be used for the adjustment plate 7. FIG.
FIG. 14 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

The size of the adjusting plate 7 is not limited to the size larger than the chip 1, and as shown in FIG.
The size of the adjustment plate 7 may be smaller than that of the chip 1 if the adjustment can be made so as to cancel the deflection of the chip 1 due to the above.
Note that a copper plate, plastic, silicon, or the like can be used for the adjustment plate 7. However, when the adjustment plate 7 having a small size is used, it is desirable that a material having a high breaking strength be selected.

According to the semiconductor device having the structure described in each of the above embodiments, the chip 1 and the mounting substrate 3 are fixed to each other by the adhesive layer 5, and the chip 1 and the substrate 3 are connected to each other even in portions other than the bump electrodes 2. It is designed to be fixed.
Therefore, when the substrate 3 expands and contracts, the chip 1 itself bends and deforms in accordance with the deformation. Thereby, the stress accompanying the expansion and contraction deformation of the substrate 3 is also distributed to the chip 1 and the concentration of the stress on the bump electrode 2 can be prevented. Therefore,
The amount of distortion of the bump electrode 2 is reduced, the thermal fatigue resistance is increased, and the thermal cycle characteristics of the semiconductor device are improved.

In each of the above embodiments, the substrate 3 is made of alumina, and has a larger linear expansion coefficient than the silicon constituting the chip 1. For this reason, when the device changes from a high temperature state to a normal temperature (low temperature) state, the chip 1 warps so that its back surface becomes convex. When the chip 1 warps in this manner, a tensile stress is generated on the back surface of the chip 1, and the back surface of the chip 1 is cracked or broken, or the internal integrated circuit is broken. In order to prevent such destruction of the chip 1, an adjusting plate 7 made of a material having a linear expansion coefficient larger than the linear expansion coefficient of the chip 1 is mounted on the back surface of the chip 1. By attaching such an adjusting plate 7, the deformation of the chip 1 itself accompanying the deformation of the substrate 3 is adjusted or reduced, and the above problem can be solved.

It is preferable that the adjustment plate 7 be made of a material having a coefficient of linear expansion larger than that of the chip 1.
If such a material cannot be procured, it is possible to consider the adhesive layer 6 as a part of the adjustment plate 7 and adjust the coefficient of linear expansion by adjusting the material and the applied thickness. Also, the adjusting plate 7
The effect equivalent to adjusting the coefficient of linear expansion can also be obtained by changing the thickness and the rigidity thereof.

In each of the above embodiments, a plate-like member such as a copper plate or a plastic plate is used as the adjusting member for adjusting the bending of the chip. In addition, a film having a linear expansion coefficient larger than that of the chip 1 is used. It is also possible to use a shape-like material or a thermosetting resin.

Further, the position at which the adjusting member is mounted is not limited to the position on the back surface of the chip 1, but may be mounted from the back surface to the side surface of the chip 1, or may be mounted only on the side surface of the chip 1. In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0041]

As described above, according to the present invention, it is possible to provide a semiconductor device having good thermal cycle characteristics and high reliability, and a chip deformation preventing method for obtaining such a semiconductor device. .

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a schematic view of a multilayer composite beam.

FIGS. 3A and 3B are schematic views of a cross-sectional structure of a semiconductor device according to the present invention. FIG. 3A is a view showing a stage in which a chip is mounted on a substrate, and FIG. The figure which shows the attached stage.

FIGS. 4A and 4B are views showing a semiconductor device according to a second embodiment of the present invention, wherein FIG. 4A is a plan view and FIG.
Sectional drawing which follows the bb line | wire in a figure.

FIGS. 5A and 5B are diagrams showing a semiconductor device according to a third embodiment of the present invention, wherein FIG. 5A is a plan view and FIG.
Sectional drawing which follows the bb line | wire in a figure.

FIGS. 6A and 6B are diagrams showing a semiconductor device according to a fourth embodiment of the present invention, wherein FIG. 6A is a plan view and FIG.
Sectional drawing which follows the bb line | wire in a figure.

FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

9A and 9B are views showing a flip-chip type semiconductor device. FIG. 9A is a cross-sectional view of an ideal product, and FIG. 9B is a cross-sectional view of an actual product.

[Explanation of symbols]

1,1-1,1-2 ... semiconductor chip, 2 ... bump electrode, 3 ...
Mounting substrate, 4 ... wiring pattern, 5, 5A, 5B ... adhesive layer, 6 ... adhesive layer, 7, 7A, 7B, 7C ... adjustment plate, 8 ...
Dam-bump.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 311

Claims (6)

(57) [Claims] A semiconductor chip which is flip-chip connected on a mounting board via a conductive electrode; and the chip and the mounting board provided between the chip and the mounting board except for the conductive electrode. Fixing means for fixing the tip, and adjusting means for adjusting the bending of the chip ,
The means for adjusting the deflection of the chip is opposed to the fixing means.
A semiconductor device provided on a chip . 2. The device according to claim 1, wherein the conductive electrode is a bump electrode provided on the chip, and the bump electrode is concentrated on a part of the chip. Semiconductor device. 3. A method for preventing chip deformation of a semiconductor device having a structure in which a semiconductor chip is flip-chip connected via a conductive electrode on a mounting board, wherein the conductive chip is provided between the chip and the mounting board. Fixing means for fixing the chip and the mounting substrate other than the electrodes is provided so that the chip bends in accordance with expansion and contraction of the mounting substrate, and the bending of the chip is adjusted so as to cancel the bending by the fixing means. Adjustment means facing the fixing means
A chip deformation preventing method, wherein the chip deformation is prevented by providing the chip on a chip. 4. The tip according to claim 3, wherein the deflection of the tip is adjusted by adjusting the thickness of the material constituting the adjusting means, its Young's modulus and its linear expansion coefficient. Deformation prevention method. 5. The adjustment of the bending of the chip is performed by calculating a multi-layer composite beam by material mechanics, assuming that the multi-layer composite portion including the mounting substrate, the fixing means, the chip and the adjusting means is a multi-layer composite beam. The method according to claim 4, wherein the method is performed by applying an equation. 6. The flexure adjusting means is provided on the mounting substrate.
The method according to claim 1, wherein the material is made of different materials.
Semiconductor device.