JP2000236042A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce stresses applied to a semiconductor chip and a connection member in the connection of the semiconductor chip and wiring board typified by flip-chip mounting. SOLUTION: A semiconductor chip 1 and a wiring board 2 for mounting it are bonded by a melted solder bump 3. The thickness ratio of the semiconductor chip 1 and the wiring board 2 is determined, based on the modulus of elasticity of the semiconductor chip 1 and that of wiring board 2 so that the maximum deflection of the semiconductor chip 1 and that of the wiring board 2 are made the same value. Consequently, the stress applied to the semiconductor chip 1 and solder bump 3 by thermal stress or an external force is reduced and optimized at the same time. Also, the reliability of a semiconductor device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a semiconductor package in which a semiconductor chip is flip-chip connected to a wiring board.

[0002]

2. Description of the Related Art A conventional example of the present invention will be described. FIG.
Shows a conventional flip-chip mounted semiconductor device. Generally, this semiconductor device is a semiconductor chip
11, a wiring board 12, solder bumps 13, and a filling resin (underfill resin) 14. The semiconductor chip 11 has a plurality of solder bumps 13 formed on the bottom surface. By melting and connecting the solder bumps 13 to connection patterns (not shown) formed on the upper surface of the wiring board 12, a semiconductor chip is formed.
11 is mounted on the wiring board 12. The wiring substrate 12 is made of, for example, an epoxy resin containing glass fiber. If this material is used, the product cost of the entire semiconductor device can be reduced. However, a resin substrate made of another material can also be used. The filling resin (underfill resin) 14 is, for example, an epoxy resin, which is a thermosetting plastic, and is filled in the gap between the semiconductor chip 11 and the wiring board 12 after the solder bumps 13 are melted and connected, and is heat-cured. Have been. The underfill resin 14 seals the lower surface of the semiconductor chip 11, so that the entire joint portion of the underfill resin 14 can receive the stress applied when the semiconductor chip 1 and the wiring board 12 are joined.
Can be alleviated.

[0003]

SUMMARY OF THE INVENTION A semiconductor chip mounted on a semiconductor device and bumps for electrical and mechanical connection between the semiconductor chip and the wiring board have a coefficient of thermal expansion between the wiring board and the semiconductor chip. Since the difference between the wiring board and the semiconductor chip greatly varies by about 5 times due to a temperature change of the semiconductor device, a thermal stress is generated between the two and a mechanical stress due to an external force is generated between the two.

In the prior art, by filling an underfill resin between the semiconductor chip and the wiring board, the above-mentioned stress generated between the wiring board and the semiconductor chip is prevented from being concentrated only on the bump, and is applied to the bump. Trying to reduce stress.

However, since the elastic modulus of the wiring board is smaller than the elastic modulus of the semiconductor chip, the stress applied to the solder bump is generated unevenly on the side of the solder bump to which the semiconductor chip is connected. This is because the elastic modulus of the semiconductor chip is very large compared to the wiring board, and the semiconductor chip is difficult to deform.When stress is applied to the semiconductor device, the entire wiring board bends and the stress is relaxed. On the other hand, in a semiconductor chip, the effect of stress relaxation due to flexural deformation is small.
Further, by filling the underfill resin between the semiconductor chip and the wiring board, the stress applied to the solder bump is reduced, but the stress applied to the semiconductor chip is increased accordingly.
For this reason, the electrical characteristics of the semiconductor chip may be affected,
Further, when the size of the semiconductor chip is further increased, there has been a problem that cracking of the semiconductor chip is more likely to occur than breakage of the solder bumps.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a semiconductor chip and a wiring board are connected to each other, and to provide a semiconductor device and a method for manufacturing the same, which reduce stress applied to the semiconductor chip and members connecting the semiconductor chip. thing,
And to improve the reliability of the semiconductor device.

[0007]

According to the present invention, there is provided a semiconductor device in which a semiconductor chip and a wiring board are connected to each other when the same stress acts on the same area of the semiconductor chip and the wiring board. The thickness ratio between the semiconductor chip and the wiring board is determined based on the elastic modulus of the semiconductor chip and the wiring board so that the maximum deflection is substantially the same.

Accordingly, when a thermal stress due to a temperature change of the semiconductor device or a mechanical stress due to an external force acts on the semiconductor device, the amount of deflection between the semiconductor chip and the wiring substrate can be made substantially equal. . From this, it is possible to prevent the stress from being generated unevenly between the semiconductor chip and the member connecting the semiconductor chip, and to simultaneously reduce the stress applied to the semiconductor chip and the member connecting the semiconductor chip. It is possible to reduce and optimize.

Further, when the semiconductor chip and the wiring board are electrically and mechanically connected by flip-chip connection using bump electrodes (bumps) made of a brazing material, stress applied to the bumps is reduced. In addition, it is possible to prevent the occurrence of a failure in the electrical operation of the bump, thereby improving the reliability of the semiconductor device.

When the underfill resin is filled around the bumps located in the gap between the semiconductor chip and the wiring board, the stress applied between the semiconductor chip and the wiring board is bonded by the underfill resin. The entire part can be received in a wider area than before, and the stress applied to the bump can be reduced. In addition, the stress applied to the semiconductor chip can be reduced, and the reliability of the electrical characteristics of the semiconductor chip can be ensured.

The effect of the present invention is that the ratio of the thickness of the semiconductor chip to the wiring substrate is 0.9 to 1.1 times the cube root of the reciprocal of the elastic modulus of the semiconductor chip and the wiring substrate. This can be achieved by setting the value to a range.

In particular, in a semiconductor device in which the main component of the wiring board is an epoxy resin containing glass fiber and the material of the semiconductor chip is silicon, the thickness of the wiring board is set to 2.2 to 2.0 of the thickness of the semiconductor chip. By setting the thickness in the range of 2.8 times, the effect of the present invention can be achieved, and the stress applied to the semiconductor chip and the bump can be reduced.

According to another aspect of the present invention, there is provided a semiconductor device having a semiconductor package having a semiconductor chip mounted thereon and a base wiring board on which the semiconductor package is mounted, wherein the semiconductor chip has the same area as the base wiring board. The thickness ratio between the semiconductor chip and the base wiring board is determined based on the elastic modulus of the semiconductor chip and the base wiring board so that the maximum amount of deflection when the stress acts is substantially the same. It is characterized by having been done.

[0014] According to this, when a thermal stress due to a temperature change of the semiconductor device or a mechanical stress due to an external force acts on the semiconductor device, the amount of deflection between the semiconductor chip and the base wiring substrate can be made substantially equal. it can. Thus, stress applied to the member between the semiconductor chip and the base wiring board and the semiconductor chip can be reduced.

The effect of the present invention is that the ratio of the thickness of the semiconductor chip to the base wiring board is set to 0.93 which is the reciprocal of the ratio of the elastic modulus of the semiconductor chip to the base wiring board.
This can be achieved by setting the value in the range of １．１1.1 times.

A method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device having a semiconductor chip and a wiring board, the method including a step of connecting the semiconductor chip and the wiring board. When connecting a substrate, the thickness and the material of the semiconductor chip and the material are so set that the maximum deflection amount when the same stress acts on the same area of the semiconductor chip and the wiring substrate is substantially the same. The thickness and material of the wiring board are determined.

Another method of manufacturing a semiconductor device according to the present invention includes a semiconductor package having a semiconductor chip mounted thereon and a base wiring board on which the semiconductor package is mounted.
In the method of manufacturing a semiconductor device having a step of connecting the semiconductor package and the base wiring board, when connecting the semiconductor chip and the base wiring board, the semiconductor chip and the base wiring board have the same area. The thickness and the material of the semiconductor chip and the thickness and the material of the base wiring substrate are determined so that the maximum amount of deflection when the stress acts is substantially the same.

[0018]

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention. In the present embodiment, flip-chip mounting in which the so-called element forming surface of the semiconductor chip 1 is mounted so as to face the wiring board 2 is employed. This semiconductor device generally includes a semiconductor chip 1, a wiring board 2, solder bumps 3, and a filling resin (underfill resin) 4. The semiconductor chip 1 has a plurality of solder bumps 3 formed on the bottom surface. The semiconductor chip 1 is mounted on the wiring board 2 by melting and connecting the solder bumps 3 to connection patterns (not shown) formed on the upper surface of the wiring board 2. The underfill resin 4 is, for example, a thermosetting resin, and the undersurface of the semiconductor chip 1 is sealed by the underfill resin 4. As a result, the stress applied between the semiconductor chip 1 and the wiring board 2 at the time of joining or the like is received by the entire joint portion of the underfill resin 4, and the stress applied to the solder bumps 3 can be reduced. Silicon is mainly used as a material of the semiconductor chip 1. The wiring board 2 is made of glass epoxy. As the solder bumps 3, those containing 90% or more of lead having low elasticity and high melting point are often used. As the underfill resin 4, for example, an epoxy resin or the like is used.

Here, the relationship between the amount of deflection of the semiconductor chip 1 and the wiring board 2 and the stress will be described.

FIG. 2 is a cross-sectional view showing a state in which a semiconductor device having a semiconductor chip 1, a wiring board 2, and a solder bump 3 for connecting the semiconductor chip 1 is bent by being heated. Here, it is assumed that the semiconductor chip 1 and the wiring board 2 are connected by the solder bumps 3a and 3c at both ends in FIG. 2 and the solder bump 3b at the center in FIG.
When the semiconductor device having the semiconductor chip 1 and the wiring board 2 of the above-described materials is heated, the coefficient of thermal expansion of the wiring board 2 is usually about 5 times larger than the coefficient of thermal expansion of the semiconductor chip 1. As shown, a downwardly convex deflection occurs. Usually, since the elastic modulus of the semiconductor chip 1 is larger than the elastic modulus of the wiring board 2, if the thickness of the semiconductor chip 1 and the wiring board 2 are almost the same, the deflection W1 of the semiconductor chip 1 is Is smaller than the deflection amount W2.

For this reason, the distance between the semiconductor chip 1 and the wiring board 2 is larger than that of the solder bumps 3a and 3c.
And a large stress acts on the solder bumps 3b, their joints, and the semiconductor chip 1 in the vertical direction in the figure. When the gap between the semiconductor chip 1 and the wiring board 2 is filled with the underfill resin 4 as shown in FIG. 1, the stress applied to the solder bump 3b can be reduced, but the deformation of the solder bump 3b is suppressed by the underfill resin 4. And the amount of deformation is reduced.
Will be further stressed. Therefore, it can be considered that such stress can be reduced by making the amount of deflection of the semiconductor element 1 and that of the wiring board 2 equal.

The theoretical formula for the maximum deflection of a flat plate is shown in the following formula 1.

Wmax = α (p · a) ⁴ / (E · t ³ ) (Equation 1) (Wmax: maximum deflection, α: coefficient, p: load, a: area,
(E: elastic modulus, t: substrate thickness) Next, it is considered that the maximum deflection amounts of the semiconductor chip 1 and the wiring substrate 2 are made equal. That is, when the load p and the area a applied to the semiconductor chip 1 and the wiring board 2 are under the same condition, the deflection amounts of the two are set to be equal to each other so that the semiconductor chip 1 and the wiring board 2 are connected. It is considered that both have the same amount of deflection when a load is applied in. Therefore, the elastic modulus and the substrate thickness of the semiconductor chip 1 are set to E respectively.
When the elastic modulus of the wiring board 2 and the board thickness are E2 and t2, respectively, when the elastic modulus and the board thickness of the wiring board 2 are E1 and t1, respectively, the following equation 2 only needs to be satisfied in order to make the maximum deflection amount Wmax equal.

E1 / E2 = t2 ³ / t1 ³ = A ³ (Equation 2) By this, for example, when the thickness and the elastic modulus of the semiconductor chip 1 and the elastic modulus of the wiring board 2 are set, the equation 2
Accordingly, the thickness of the wiring board 2 can be determined so that the maximum deflection amount of the semiconductor chip 1 and the wiring board 2 becomes the same. FIG. 3 shows a result of a change in stress applied to the solder bump 3 and the semiconductor chip 1 when the thickness t2 of the wiring board 2 is changed around the obtained value by a stress analysis using a structural analysis simulator. , 4. 3, as the ratio A = (t2 / t1) of A ₀ of the substrate thickness if the expression 2 is satisfied, there is shown the variation of stress applied to the solder bumps when changing this ratio. FIG. 4 shows a change in the stress applied to the semiconductor chip 1 when the ratio of the substrate thickness is changed as in FIG. In FIGS. 3 and 4, an index proportional to the stress is shown on the vertical axis. This index indicates a maximum value in a plane where the semiconductor chip 1 and the wiring board 2 are in contact with each other.

According to FIGS. 3 and 4, the overall fluctuation tendency differs between the solder bump 3 and the semiconductor chip 1. In any case, the ratio A = (t2 / t1) of the substrate thickness satisfies the equation 2 the stress applied in the vicinity of a ₀ is the minimum is the ratio of.
According to FIG. 3, the range of the ratio at which the stress applied to the solder bump 3 becomes almost constant is the substrate thickness ratio A = (t2 / t1).
It can be said that the 0.9 times to 1.1 times the range of A _0. According to FIG. 4, the stress applied to the semiconductor chip 1 is represented by the ratio of the substrate thickness A =
(T2 / t1) but is substantially constant value in a wide range of 1.2 times the A _0, increases sharply exceeds 1.2 times. These results, by determining the practical substrate thickness ratio A = the range of (t2 / t1) and 0.9A ₀ ~1.1A _0, and reduce the stress applied to the semiconductor chip 1 and the solder bumps 3 semiconductor It can be seen that the device can be realized.

The definition of the range of the substrate thickness ratio A = (t2 / t1) is, for example, that the semiconductor chip 1 is made of silicon having an elastic modulus of about 17000 kg / m and has an elastic modulus of about 1700 kg / m. Wiring board 2 with glass epoxy which is n
Is equivalent to setting the thickness of the wiring board 2 to be 2.2 to 2.8 times the thickness of the semiconductor chip 1. That is, in this case, the semiconductor chip 1
Is 0.5 mm, the thickness of the wiring board 2 is 1.1 mm.
Semiconductor chip 1 according to the present invention,
In addition, the effect of reducing the stress applied to the semiconductor bump 3 can be realized. When the thickness of the wiring board 2 is 1.25 mm, the applied stress is minimum. In this case, FIGS. 3 and 4 show the case where the thickness of the wiring board 2 is changed to 0.6 to 1.8 mm.

In order to manufacture the semiconductor device of the present invention, there is a method of determining the thickness of the wiring board 2 from the thickness and the material of the semiconductor chip 1 and the material of the wiring board 2 determined as described above. Easy to apply. If the thickness of the wiring board 2 determined by this method is difficult in manufacturing a semiconductor device, the thickness or the material of the semiconductor chip 1 or the material of the wiring board 2 is changed to change the semiconductor. The deflection amounts of the chip 1 and the wiring board 2 may be the same. That is, in the semiconductor device of the present invention, the thickness and material of the semiconductor chip 1 and the wiring board 2
The thickness and material of the semiconductor chip 1 and the wiring board 2 are selected so that the maximum deflection amount is the same. In practice, three of these four parameters
By fixing the condition and adjusting the remaining one, the amount of deflection of the semiconductor chip 1 and the wiring board 2 can be made equal.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a cross-sectional view of a flip-chip mounted semiconductor device according to the second embodiment. The flip-chip mounted semiconductor device according to the second embodiment has a semiconductor chip 1, a wiring board 7, a solder bump 3, and an underfill resin 4, as in the first embodiment. The feature of the second embodiment is that the wiring board 7 is made of a composite material in which a plurality of boards manufactured by different manufacturing methods are laminated. That is, the wiring board 7 has the build-up layer 6 in which a plurality of boards manufactured by different manufacturing methods are stacked on the core board 5. Such a wiring board is generally called a build-up board. When such a wiring board is used, if the ratio of the board thickness is determined by obtaining the maximum deflection amount of the entire wiring board 7 including the build-up layer 6, the same stress reduction effect as in the first embodiment can be expected. it can. However, even if the maximum amount of deflection of the wiring board 7 having such a structure is not calculated by a complicated method, the ratio of the substrate thickness of the core substrate 9 to the semiconductor chip 1 is determined by the method described in the first embodiment. If done, the stress can be reduced. this is,
The thickness of the build-up layer 6 is 1/20 to 1/1 / the thickness of the core substrate 5
This is because the thickness is about 50, and the contribution of the build-up layer 6 to the maximum deflection amount of the wiring board 7 is small. However, compared to the first embodiment, the effect of reducing the stress is considered to be smaller in the case of the present embodiment.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a schematic cross-sectional view of a semiconductor device in which a semiconductor package 9 is mounted on a base wiring board 10 as a third embodiment. 6, the semiconductor package 9 is electrically and mechanically connected to the semiconductor chip 1, the wiring board 2, the adhesive 8 for connecting the semiconductor chip 1 and the wiring board 2, and the base wiring board 10 by fusion bonding. And solder bumps 3 for performing the operation. The semiconductor chip 1 and the wiring board 2 are electrically connected by wires or solder bumps (not shown).

Referring to FIG. 6, the method of manufacturing a semiconductor device according to the present invention can be applied between a semiconductor chip 1 and a wiring board 2 first. That is, the thickness or the material of the wiring board 2 or the thickness or the material of the semiconductor chip 1 is determined by the method described in the first embodiment so that the deflection amounts of the two become equal, so that the semiconductor via the adhesive 7 is formed. It is possible to reduce the stress applied to the chip 1.

In the present embodiment, only the stress applied via the adhesive 8 is considered as the stress applied to the wiring board 2.
Actually, in the configuration shown in FIG. 6, the stress applied to the wiring board 2 is not only the stress applied via the adhesive 8 but also the solder bump 3.
There is a stress applied through. However, it is generally considered that the amount of deflection of the base wiring board 10 is generally larger than that of the semiconductor chip 1, and that the base wiring board 10 and the wiring board 2 are made of the same material, and that the difference in the coefficient of thermal expansion is small. Seem. Therefore, the amount of deflection of the wiring board 2 due to the stress applied to the wiring board 2 from the base wiring board 10 via the solder bumps 3 as compared with the stress applied from the semiconductor chip 1 to the wiring board 2 via the adhesive 8. Is considered to have a small effect. Therefore, in the present embodiment, the effect of the present invention is achieved by considering only the same amount of deflection of the semiconductor chip 1 and the wiring substrate 2 without considering the amount of deflection of the base substrate 10 on which the semiconductor package 9 is mounted. Can be realized.

According to this method, the effects of the present invention can be realized without considering what kind of base substrate 10 the semiconductor package 9 is mounted in at the stage of manufacturing the semiconductor package 9. Also, at the stage of manufacturing the semiconductor package 9, assuming that the semiconductor package 9 is mounted on the standard base wiring board 10, the maximum deflection amount of the wiring board 2 is smaller than the maximum deflection amount of the semiconductor chip 1. May be set.

Next, the semiconductor chip 1 and the base wiring board 1
It is also conceivable to apply the method of manufacturing a semiconductor device according to the present invention to a value between 0 and 0. That is, the thickness and the material of the semiconductor chip 1 and the thickness and the material of the base wiring board 10 are determined by the method described in the first embodiment so that the deflection amounts of the two become equal. In this case, the semiconductor chip 1 and the semiconductor chip 1 and the base wiring board 1
It is possible to reduce the stress applied to the member between zero. The effect of reducing the stress applied to the member between the semiconductor chip 1 and the base wiring board 10 is particularly effective in reducing the stress applied to the solder bumps 3, thereby improving the reliability of the electrical connection via the solder bumps 3. .

In this case as well, it is considered that the influence of the wiring board 2 is small, as in the case where the method of manufacturing a semiconductor device according to the present invention is applied to the semiconductor chip 1 and the wiring board 2. Also in this case, the maximum deflection amount of the base wiring substrate 10 may be set to be smaller than the maximum deflection amount of the semiconductor chip 1 in consideration of the influence of the wiring substrate 2.

[0036]

As described above, according to the method of manufacturing a semiconductor device of the present invention, in a semiconductor device in which a semiconductor chip and a wiring board are connected, the semiconductor chip and the semiconductor chip are connected to the wiring board. Stress applied to the member can be reduced. By reducing the stress applied to the semiconductor chip, the reliability of the electrical operation of the semiconductor chip can be increased. In the case where the connection between the semiconductor chip and the wiring board also serves as an electrical connection, the reliability of the electrical connection can be increased by reducing the stress applied to the members connecting the semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view when a semiconductor device is bent.

FIG. 3 is a diagram showing a change in stress applied to a solder bump in the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a change in stress applied to a semiconductor chip in the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional structural view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 6 is a cross-sectional view illustrating a semiconductor package according to a third embodiment of the present invention.

FIG. 7 is a sectional structural view showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Semiconductor chip 2, 7, 12 Wiring board 3, 13 Solder bump 4, 14 Underfill resin (filling resin) 5 Core board 6 Build-up layer 8 Adhesive 9 Semiconductor package 10 Base wiring board

Claims (9)

[Claims] In a semiconductor device in which a semiconductor chip and a wiring board are connected to each other, the maximum deflection amount when the same stress acts on the same area of the semiconductor chip and the wiring board is substantially the same. A ratio of the thickness of the semiconductor chip to the thickness of the wiring board based on the elastic modulus of the semiconductor chip and the wiring board. 2. The semiconductor device according to claim 1, wherein the semiconductor chip and the wiring board are electrically and mechanically connected by flip-chip connection using a bump made of a brazing material. 3. The semiconductor device according to claim 2, wherein an underfill resin is filled around said bump located in a gap between said semiconductor chip and said wiring board. 4. A value of the thickness ratio between the semiconductor chip and the wiring board in a range of 0.9 to 1.1 times the cube root of the reciprocal of the elastic modulus ratio between the semiconductor chip and the wiring board. The semiconductor device according to claim 1, wherein: 5. A main component of the wiring board is an epoxy resin containing glass fiber, a material of the semiconductor chip is silicon, and a thickness of the wiring board is 2.2 to 2.2 of a thickness of the semiconductor chip. 4. The semiconductor device according to claim 1, wherein the thickness is in a range of 2.8 times. 5. 6. In a semiconductor device having a semiconductor package on which a semiconductor chip is mounted and a base wiring board on which the semiconductor package is mounted, the maximum when the same stress acts on the same area of the semiconductor chip and the base wiring board. The thickness ratio between the semiconductor chip and the base wiring board is determined based on the elastic modulus of the semiconductor chip and the base wiring board so that the amount of deflection is substantially the same. Semiconductor device. 7. The semiconductor chip and the base wiring board have a thickness ratio in a range of 0.9 to 1.1 times a cube root of a reciprocal of an elastic modulus ratio of the semiconductor chip and the base wiring board. The semiconductor device according to claim 6, which is a value. 8. A method for manufacturing a semiconductor device, comprising: a semiconductor chip and a wiring board; and a step of connecting the semiconductor chip and the wiring board, wherein when connecting the semiconductor chip and the wiring board, The thickness and the material of the semiconductor chip and the thickness and the material of the wiring board are set such that the maximum deflection amount when the same stress acts on the same area of the semiconductor chip and the wiring board becomes substantially the same. A method for manufacturing a semiconductor device, comprising: 9. A method for manufacturing a semiconductor device, comprising: a semiconductor package having a semiconductor chip mounted thereon; and a base wiring board on which the semiconductor package is mounted, the method including a step of connecting the semiconductor package and the base wiring board. When connecting the semiconductor chip and the base wiring board, the semiconductor chip is so formed that the maximum deflection amount when the same stress acts on the same area of the semiconductor chip and the base wiring board becomes substantially the same. A method for determining the thickness and material of the base wiring board and the thickness and material of the base wiring substrate.