JPH0775253B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a lead and chip bonding suitable for mounting a large-sized LSI chip in a package with a narrow width. The present invention relates to a dual line package type semiconductor device having an improved pad portion and a manufacturing method thereof.

[Conventional technology]

Conventionally, as a method of mounting an LSI chip in a plastic package, a tab having a chip size large for mounting the chip is arranged in the central part of the package, and a chip in which a bonding pad part is arranged on four sides of the chip is placed on the tab. The so-called wire bonding structure has been adopted in which the lead tip portions of the lead frame are arranged in the four side directions of the chip and the pad portions and the lead tip portions are interconnected with a gold wire.

However, in this structure, it is necessary to maintain a certain distance between the chip and the lead tip of the lead frame, and in particular, the distance between the short-side end of the rectangular chip and the package end is required. It was unsuitable to fit in a small package. In addition, since the tab with a large size is arranged in the center, the resin interface peeling under the tab due to thermal stress and the crack of the resin under the tab are often experienced, which may cause temperature cycle or reflow crack resistance. The structure was not suitable for satisfying the test results.

In order to solve this problem, as proposed in JP-A-60-167454, all the lead tips of the lead frame are arranged on the short side of the chip, tabs are eliminated, and an insulating film is formed on the frame. Has been proposed, a chip is die-bonded on the film, and a so-called tabless package, which is a wire bonding structure in which a bonding pad part of the chip and a lead tip part are mutually connected by a gold wire, is proposed. However, in this structure, the cost is increased due to an increase in the step of attaching the insulating film, and the bonding accuracy is deteriorated due to the thermal expansion of the insulating film during wire bonding, so it is necessary to recognize and control the bonding position to deal with it. There were inconveniences such as the increase in tact time.

Furthermore, for chips with large dimensions on the long side of the chip,
If the size of the long side of the package is not made larger, the chip end and the gold wire will contact when connecting the gold wire.
In the true sense, it cannot be said that the structure is suitable for mounting a large chip.

USP4 as other conventional technology for tabless packages
612564 is known.

[Problems to be solved by the invention]

In the above conventional technology, the distance between the chip edge and the package edge is at least 1.2 mm or more, and since a large tab is used, thermal stress cannot be reduced and a large LSI chip can be stored in a small package. However, there is a structural limitation and there is a problem in temperature cycle resistance and reflow resistance.

Further, the above-mentioned so-called tabless package technology has disadvantages in the process such as securing the insulation film attachment accuracy, increasing the number of production steps, and degrading the wire bonding accuracy, and has a large dimension on the long side. It was necessary to design the dimension of the long side of the package to be large with respect to the chip.

An object of the present invention is to provide a semiconductor device having a structure in which a distance between a chip end and a package end is 1.0 mm or less regardless of a long side and a short side, a large chip is housed in a package having a particularly small width, and at the same time thermal stress can be reduced. And to provide a manufacturing method thereof. Further, another object is to provide a semiconductor device having a package structure characterized by high reliability and low cost, which can reduce the production man-hours as compared with the conventional plastic package process without the step of attaching an insulating film and the manufacturing method thereof. To provide.

[Means for solving problems]

The above-mentioned object is to arrange a plurality of bond pad parts of the LSI chip on the chip and to dispose a heat-resistant organic polymer film on the surface excluding the pad part of the chip, which is thinner than the external lead as a lead. At the tip of the internal lead extending in the LSI chip area, a protrusion having a thickness corresponding to the thickness of the external lead is provided corresponding to each pad portion, and a through hole is formed in the internal lead excluding the protrusion. And a gap is formed between the back surface of the internal lead and the front surface of the LSI chip by electrically connecting the protrusion portion and the pad portion with a conductive paste, and the LS including at least the gap.
This is achieved by a semiconductor device in which the I chip and the internal lead are resin-sealed.

Further, the above-mentioned object is to bond the LSI chip to the tip of the internal lead by selectively etching the internal lead region in the plate thickness direction while leaving the tip of the internal lead located on the LSI chip of the lead frame. Forming a protrusion for contacting the pad portion, forming a through hole in the internal lead excluding the protrusion,
The step of forming a heat-resistant organic polymer film on the surface of the I chip excluding the bonding pad section, the step of applying a conductive paste on the bonding pad section of the LSI chip, and the bonding pad section and the protruding section of the lead A step of aligning, and a step of pressing and heating the aligned lead frame and LSI chip to connect the protruding portion at the tip of the lead to the bonding pad portion of the LSI chip via the conductive paste. And a method of manufacturing a semiconductor device including a step of resin-sealing the LSI chip to which the leads are connected. To describe the first specific structural example, the pad rows of the bonding pads of the LSI chip are locally arranged at both ends of the chip so as to face each other, and the tips of the internal leads corresponding to the pads of the pad row are arranged. A protrusion is provided on the inner lead, the protrusion of the internal lead and the pad are electrically connected with a soft conductive paste, and the pad row and the pin rows of the dual line package are arranged so as to be orthogonal to each other. This is achieved by taking a stationary structure. Furthermore, to describe the second specific structural example, a plurality of bonding pad portions of the LSI chip are formed on the region of the chip where the active elements are provided, and the internal lead corresponding to each pad portion is formed. This is achieved by providing a projection at the tip, electrically connecting the projection of the lead and the pad with a soft conductive paste, and sealing them with a resin. By forming a heat-resistant insulating film with a thickness of 1 μm or more and 30 μm or less, for example, a heat-resistant organic polymer film such as a polyimide film, on the surface of the LSI chip other than the pad portion in advance in the wafer process, the interfacial tension causes soft conductive The paste can be evenly and collectively applied to the pad portion by multi-head microshrinking. Bonding between the lead protrusion and the pad is done by precisely aligning one of them and then pressing with a heat block head.
By adopting the manufacturing method of collectively bonding, it is possible to eliminate the conventional wire bonding process, reduce the distance between the chip end and the package end, and reduce the production process. Furthermore, the elastic modulus is 400 kgf / mm ² or less (practically 10
By bonding with a soft conductive paste in the range of kgf / mm ² ), it is not necessary to apply a large load to the chip at the time of bonding, and the bonding pad part is on the area (active area) where the active element of the chip is provided. Even if it exists, it does not cause damage, and since the joint portion can relieve the thermal stress due to the difference in linear expansion coefficient between the lead frame material and the chip material, it is possible to prevent disconnection failure due to thermal cycle. The conductive paste is preferably an epoxy resin or a polyimide resin filled with silver powder or nickel powder, but the composition is not limited, and the elastic modulus is 10 to 40.
It is sufficient that the conductivity is secured at 0 kgf / mm ² . By arranging the bonding pad part near the center of the chip, the embedding area of the lead part after resin molding can be widened, so the stress in the lead cutting / bending process after resin molding is restricted. Does not affect the joint with. Further, when the bonding pad portion is arranged on the active area, it can be designed to have a size larger than the conventional pad area, the accuracy of applying the soft conductive paste may be somewhat poor, and the amount of application can be increased. Therefore, the bonding area is wide, and it is easy to secure the reliability of adhesion. Further, in order to reinforce the bonding strength between the chip and the frame, a tab having a width less than twice the lead width is provided, and the chip surface is bonded with an adhesive so that external force such as vibration during the process can be prevented. The joint between the pad and the lead is not broken. In this case, by using the matrix resin of the base without the conductive filler of the soft conductive paste as the adhesive, it is possible to bond the tab and the chip surface at the same time during the gang bonding of the chip and the lead tip. . The so-called tab-hanging lead that hangs the tab may be cut at the outer end of the package after resin molding at the time of cutting the lead. The protrusions are formed on the end portions of the inner leads of the lead frame by a well-known etching technique, that is, the inner leads (lead portions extending to the LSI chip area in the package) are selectively etched while leaving the tip portions thereof. Thereby, a protrusion having a desired shape and a desired height can be formed. Generally, if the etching depth is 30 μm or more as a columnar protrusion, the lead frame does not contact the chip surface and does not damage the polyimide film on the surface. The bent portion of the lead located in the package of the lead frame By making a through hole near the resin, the resin is filled and bonded in the gap of about 30 μm between the lead frame and the chip surface after resin molding. Is restrained, and the structure becomes stronger.

Furthermore, as a result of thermal stress analysis, as a material for the lead frame, an iron-nickel alloy with a linear expansion coefficient in the range of 0.8 × 10 ^{-5 to} 1.4 × 10 ^-5 / ° C was selected. 70 to 80 Vol% quartz filler or 70 to 80 Vol% filler containing at least one third of spherical filler
% Combined with a resin whose coefficient of linear expansion is 0.7 × 10 ^{-5 to} 1.4 × 10 ^-5 / ° C, the thermal stress generated at the interface between the chip or the lead and the resin during the temperature cycle of the package is reduced. It can be reduced, and temperature cycle resistance and reflow crack resistance can be improved. Further, when the linear expansion coefficient of the mold resin is not set to 1.4 × 10 ⁻⁵ / ° C. or less, after mounting the chip on the lead frame by the above-described method, for example, after chip coating with a silicon resin-based chip coat resin, a normal resin is used. It may be molded with a resin having a coefficient of linear expansion of 1.7 × 10 ^-5 / ° C or more.

The combination of the above technologies makes it possible to store a large chip in a small and thin package, eliminate the wire bonding process, and reduce the thermal stress of the joint and dissimilar materials. A package structure and its manufacturing method can be provided.

Furthermore, for highly reliable use, gold bumps or copper bumps with gold plating of 0.1 to 3 μm are formed on the pads arranged in the active area of the chip, and the height is set to 30 μm or more. Use a TAB (Tape Automated Bore)
After performing gang bonding with the inner bonder of (nding) and then resin-molding, a package capable of mounting a large chip can be provided. In this case, the bump hardness should be Knoop hardness 80 or less, and the load during inner bonding should be
It should be below 30g / pad. Furthermore, the aluminum bonding pad is plated with gold of 0.1 to 3 μm, and the lead-
The bumps may be formed with tin solder, and the leads whose gold tips are partially plated may be collectively inner-bonded. However, in both cases, the cost is higher than the method of joining with the above-mentioned conductive paste.

[Action]

According to the first specific structural example of the present invention, the pad rows of the bonding pads of the chip are locally arranged so as to face each other at both ends of the chip, and the protrusions provided at the tip of the lead frame are arranged on the chip. Since it has a structure in which it is concentrated on the pad row of and is bonded via a conductive paste, it can be designed to be 1 mm or less even in the narrowest distance portion between the chip end and the package end, and a large chip can be mounted. This is particularly advantageous when mounting a large rectangular chip having a large memory capacity.

When using a chip having a passivation film such as a polyimide film on its surface, a soft conductive paste such as a silver paste is easily wettable to the aluminum film of the bonding pad portion and hard to wet to the polyimide film. When the paste is applied by the shrinkage, the paste has a feature that it forms spherical droplets at the bonding pad portion and is easily applied uniformly.

Since the tip of the lead frame is formed with a projection of at least 30 μm by etching in the plate thickness direction, the back surface of the frame and the surface of the chip do not come into contact with each other after the tip of the lead frame and the bonding pad portion are joined by a paste.

Since the tip projection of the lead frame and the pad are joined using a soft conductive paste with an elastic modulus of 400 kgf / mm ² or less, for example, silver paste, the thermal stress due to the difference in the linear expansion coefficient between the chip and the lead frame is The package can reduce disconnection defects during temperature cycling. Furthermore, since the mold resin fills the gap between the lead frame and the chip by providing the through hole near the bent portion of the lead frame, the stress in the longitudinal direction of the lead can be restrained and the thermal stress can be further reduced.

By selecting a conductive paste with a viscosity in the range of 50 to 1300 poise, it is possible to precisely and evenly apply it to the area corresponding to the pad position of the chip with microshrinkage.
The ink-like paste in the range of 500 poises to 10,000 poises can be applied by screen printing using a mask for precise and uniform application by utilizing its thixotropic property.

Further, according to the second specific structural example of the present invention, since the bonding pad portion of the LSI chip is formed on the region where the active element of the chip is formed, that is, on the so-called active area, the pad area can be designed to be wide. The bonding area can be widened and the connection can be made near the center of the chip, so the bonding area can be brought to the area with low thermal stress, and the reliability of connection between leads and pads and the humidity resistance can be improved. it can. Since the embedded length of the lead can be increased, the joint is less susceptible to mechanical stress during the lead cutting / bending process. Further, by providing the lead through hole in the lead bent portion of the lead frame as in the case of the first specific structural example, it is possible to make the structure less susceptible to this influence.

According to the present invention, the protrusion and the bonding pad portion at the tip of the lead frame are directly connected together with a soft conductive paste, so that the wire bonding step can be abolished, and the conventional wire bonding tension height, Although a distance was required, it is a thin and compact package structure that can be mounted on a large chip and that is thin and that the distance between the chip edge and the package edge can be designed to be 1 mm or less. The conductive paste has an elastic modulus of 400 kgf / mm ² or less, the lead frame material is an iron-nickel alloy having a linear expansion coefficient in the range of 0.8 × 10 ^{-5 to} 1.4 × 10 ^-5 / ° C, and the resin is a wire. Coefficient of expansion
Since the combination of 1.4 × 10 ^-5 / ° C or less is used, the thermal stress applied to the joint between the protrusion of the lead tip and the pad, the lead frame and the interface between the chip and the resin can be reduced, Temperature cycle resistance and reflow crack resistance can be improved.

As described above in detail, according to the present invention, since the wire bonding step can be omitted, even if the melt viscosity of the resin becomes higher than that of the conventional mold resin by highly filling the quartz filler to reduce the linear expansion coefficient of the resin. In addition, there is no contact failure due to wire bending during molding, and the production yield can be improved.

〔Example〕

Example 1 Hereinafter, a first specific structural example will be described as an example of the present invention with reference to FIGS. 1 to 11.

Design the pattern of the lead frame 1 as shown in FIG. 1, and make sure that all the lead tips are A on the two short sides of the chip.
Rows and rows B were concentrated. A tab 4 for supporting the chip may be provided in the central portion. However, the width of the tab in this case is designed to be twice the lead width or less. The bonding pads of the LSI chip 2 are A on the two short sides of the chip.
The pattern of the lead frame was designed so as to be arranged as a row and a row B and to be joined to the lead tip portion 3 of the lead frame.

As shown in the sectional view of FIG. 1, the LSI chip 2 was joined to the lead frame 1 in a face-up state. As shown in the cross-sectional view of FIG. 3, the external leads 1a extending from the mold resin 5 may be bent into a J-vent shape if necessary.

As shown in FIG. 4, the tip of the lead of the lead frame 1 was etched in the plate thickness direction of the lead frame to form the tip projection 7. The etching at this time is based on a well-known etching technique. If a mask having a desired shape is formed on the surface of the lead 7 on which the projection is to be formed, a projection having a shape corresponding to the mask shape can be formed. . For example, by forming a circular mask, it is possible to realize a cylindrical protrusion as shown in the figure. The height of the protrusion can be adjusted by appropriately selecting etching conditions such as etching time. At this time, the etching depth 6 was 30 μm, the frame material was oxygen-free copper, the thickness was 150 μm, and the surface treatment was nickel plating 5 μm and tin plating 5 μm.

FIG. 5 shows a cross-sectional view of the joint between the lead tip protrusion 7 and the Al bonding pad 8 of the LSI chip 2. The lead tip projecting portion 7 and the Al bonding pad 8 are joined via a soft silver paste 11, and the inner lead back surface 1b of the lead frame 1 and the LSI chip front surface 2a are separated by an etching depth of about 30 μm, and are directly The structure does not touch.

As the silver paste, a polyimide silver paste having a modulus of elasticity of 350 kgf / mm ² (trade name: RZ041C manufactured by Hitachi Chemical Co., Ltd.) was used.

On the surface of the LSI chip, a chip in which a registered trademark PIQ film manufactured by Hitachi Chemical Co., Ltd., that is, a polyimide passivation film 10 having a thickness of 2.3 μm is formed on the SiN (silicon nitride) inorganic passivation film 9 formed by plasma. Was used.

The back surface 1b of the lead frame 1 and the front surface 2a of the LSI chip 2 are reinforced by strengthening the joint between the pad portion 8 and the inner lead tip protrusion portion 7.
In order to reinforce the adhesion between the lead frame 1 and the lead frame 1, it is desirable to provide a lead through hole 12 in the bent portion of the lead frame 1 as shown in FIG. In this case, a circular through hole is used, but the shape does not matter. By doing so, as shown in FIG. 7, the inner lead back surface 1b of the lead frame 1 and the front surface 2a of the chip 2 are
The mold range 5 is filled more reliably in the gap between
The structure is more resistant to thermal stress in the joint.

FIG. 8 shows a manufacturing method for precisely applying the soft silver paste 11 to the bonding pad portion 8 of the LSI chip 2. A fine movement XY having the LSI chip 2 mounted thereon is filled with the soft silver paste 11 in the head in which the microshringes 14 are aligned at the positions suitable for the arrangement of the bonding pads 8 of the LSI chip 2.
The table 13 is used to precisely align the bonding pad 14 and the shrunk tip 14 and then the head is lowered to drop a small amount of the soft silver paste 11 by air pressure (arrow) and raise the head. It has been found that silver paste having a viscosity range of 50 to 1300 poise can be precisely applied by the above method. The inner diameter of the nozzle of the microshrink 14 was 0.25 mmφ. Viscosity range of silver paste 11
Those over 1000 poise can be precisely applied by the screen printing method shown in FIG. Mask 15 pad part 8
After fine alignment, the silver paste 11 can be applied with a squeegee 17 through the screen 16.

FIG. 10 shows the lead frame 1 and the bonding pad portion 8
The method of joining and was shown. After mounting the LSI chip 2 precisely coated with the silver paste 11 on the fine movement XY table 13 and precisely aligning it with the frame 1, the lead frame support 18 is lowered and the projection 7 at the tip of the lead frame is bonded to the bonding pad portion. Then, the heater block 19 was pressed and the silver paste was thermally cured. The silver paste is a polyimide-based silver paste (Hitachi Chemical Co., Ltd. product name RZ041C)
In the case of, it was confirmed that the adhesive was sufficiently adhered by curing at 300 ° C. for 20 seconds.

The frame to which the chips are bonded in this way is subjected to the usual molding process, lead cutting and bending processes to obtain the semiconductor device shown in FIGS.

The case in which the longitudinal direction of the chip 2 is long can be dealt with by adopting the lead frame arrangement as shown in FIG.

70 vol% of spherical quartz filler as mold resin
When using the filled cresol novolac curable epoxy resin (Hitachi Chemical Co., Ltd., prototype), -55 ℃ ~ 150
In a temperature cycle test at ℃, no disconnection defect was observed even after 1000 cycles, and it was found that the connection portion maintained good adhesion. Others, reflow crack resistance test, 65
Together with the results of a high temperature storage test at 95 ° C, it was found to be comparable to conventional large packages.

Second Embodiment Hereinafter, a second concrete structural example will be described as another embodiment of the present invention with reference to FIGS. 12 to 18.

As shown in FIG. 12, a lead frame pattern 1 was designed in which all the tip projections 70 of the leads facing the inside of the package are bent toward the center of the chip. As shown in FIG. 13, the bonding pad portion 8 of the LSI chip 2 is arranged near the central portion of the chip, which is the area of the active element of the chip,
The lead tip portion 70 and the pad portion 8 are made of soft conductive paste.
Joined at 11. As shown in the sectional view of FIG. 3, the lead frame 1 on which the LSI chip 2 bonded face up is mounted is resin-molded by a normal transfer molding method, preferably a multi-plunger molding method, and a normal lead cutting The product was obtained through the bending process.

As shown in FIG. 15, the tip portion of the lead frame 1 was etched in the plate thickness direction of the frame in the same manner as in Example 1 to form the tip projection portion 70. At this time, the etching depth was 30 μm, the material of the frame was 42 alloy frame (iron / nickel alloy), and the surface of the tip projection 70 was partially plated with gold to a thickness of 0.5 μm.

FIG. 15 shows a cross-sectional view of the joint between the lead tip protrusion 70 and the Al bonding pad 8 of the LSI chip 2. The lead tip protruding portion 70, Al and the bonding pad portion 8 are joined via a soft conductive paste 11, and the inner lead back surface 1b of the lead frame 1 and the front surface 2a of the LSI chip 2 are separated by an etching depth of about 30 μm. It has a structure that does not directly contact. In the LSI chip 2, a registered trademark PIQ film, that is, a polyimide passivation film 10 manufactured by Hitachi Chemical Co., Ltd., that is, a polyimide passivation film 10 having a thickness of 2.3 μm is formed on the inorganic passivation film 9 of SiN (silicon nitride) film formed by plasma. Used chips. As the soft conductive paste, a polyimide silver paste (RZ041C manufactured by Hitachi Chemical Co., Ltd.) having an elastic modulus of 350 kgf / mm ² was used.

As shown in FIG. 16, the pad portion 8 and the lead tip projection portion
In order to reinforce the joint with 70 and prevent the lead / resin interface from peeling due to mechanical stress in the lead bending step, it is desirable to provide a lead through hole 12 near the bent portion of the lead. By doing so, as shown in FIG. 17, the molded resin 5 is attached to the back surface 1b of the lead 1 and the chip 2
The gap between the surface 2a and the surface 2a is reliably filled, and it becomes a restraining force against the pulling of the lead, and the structure becomes stronger against the thermal stress of the joint.

The manufacturing technique of applying the soft conductive paste to the bonding pad portion 8 of the chip 2 will be described below in the first embodiment.
As in the case shown in FIG. 8 and also in the screen printing method, as in the case shown in FIG. 9, the projection 70 of the lead frame and the bonding pad 8 are further joined. The method was also the same as that shown in FIG.

FIG. 18 shows a lead frame layout diagram in the case where the length of the chip is long and the margin with the package end is small. In order to reinforce the bonding portion between the pad 8 and the lead tip portion 70 from the influence of vibration and the like during the process, the tab 4 having a width less than twice the lead width is provided and bonded to the chip surface as in the above embodiment. Glued. The adhesive used was a polyimide silver paste, RZ041C (trade name of Hitachi Chemical Co., Ltd.) Matrex resin not containing a silver filler.

Thus, the lead frame having the chip mounted thereon was subjected to the transfer mode process, the lead cutting process, and the bending process to obtain the intended semiconductor device. As the mold resin, a cresol novolac-curing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., prototype) filled with 70 vol% of spherical quartz filler was used. The linear expansion coefficient was 1.2 × 10 ^-5 / ℃, and the melt viscosity at 180 ℃ was 700 poise (minimum), indicating that the multi-pot mold method is suitable.

For products obtained through the above-mentioned processes,
As a result of carrying out a test at a temperature endurance cycle of 150 ° C. (30 min each), no defect of disconnection was observed even after 1000 cycles, and it was found that the joint portion made of the soft silver paste maintained good adhesion.

In addition, both the reflow crack resistance test (215 ℃ vapor reflow, 90s) and the 65 ℃ 95% RH high temperature and high humidity storage test results were found to be comparable to the conventional large package.

〔The invention's effect〕

According to the first specific structural example of the present invention, the distance between the chip end and the package end can be designed to be 1 mm or less, so that a large chip can be mounted in a small package.

Furthermore, since the tab can be eliminated or the tab can be designed with the minimum required size to support the chip, stress during temperature cycling is not concentrated on the tab end,
The structure is strong against resin cracks.

Further, wire bonding such as a conventional gold wire can be eliminated, and since gang bonding is performed by using a soft silver paste, the production man-hour can be reduced as compared with the conventional package.

Furthermore, since the joint is made of a soft silver paste, the strength of the joint is maintained, and the temperature cycle resistance is not inferior to that of the conventional package.

According to the second specific structural feature of the invention, since the bonding pad portion of the LSI chip is arranged in the vicinity of the central portion of the chip, the area of each connecting portion can be wide and the stress is low in the area. There is an effect that the reliability of the connection between the word frame and the pad portion by the soft silver paste is improved.

In addition, since the joint is made of soft silver paste, mechanical stress is not applied to the chip during connection, the chip is not damaged, and the wire is not deformed during molding to cause poor contact, improving the assembly yield. To do.

As described above, according to the present invention, it is possible to ensure high reliability of a thin and small package mounting a large chip and to improve productivity.

[Brief description of drawings]

FIG. 1 is an upper sectional view of a package of an embodiment of the present invention, FIG. 2 is a lateral sectional view, and FIG. 3 is a longitudinal sectional view. Figure 4 shows
FIG. 6 is a horizontal cross-sectional view showing a main part of a lead frame in which the leads of the present invention are subjected to an etching treatment, and FIG. FIG. 7 is a top view showing a connection state between the lead through hole and the chip upper surface portion, and FIG. 7 is a transverse sectional view thereof. FIG. 8 is a conceptual diagram showing a method of applying a soft conductive paste to a bonding pad portion, and FIG. 9 is a conceptual diagram showing a screen printing method. FIG. 10 is a conceptual diagram showing a pressing / thermosetting mechanism for bonding the lead frame and the bonding pad portion with a conductive paste. FIG. 11 is a top cross-sectional view of a package as a layout example of a lead frame, which is applicable to a case where the chip is long in the longitudinal direction. FIG. 12 is a top sectional view of a package of another embodiment of the present invention,
FIG. 13 is a chip top view showing the pad arrangement, and FIG. 14 is a vertical sectional view of the package. FIG. 15 is a cross-sectional view showing the connection between the pad portion of the LSI chip and the tip of the lead, and FIG. 16 is a top view showing the connection between the lead through hole and the chip surface.
FIG. 17 is a sectional view thereof, and FIG. 18 is an upper sectional view of a package showing another embodiment of the present invention applied when the longitudinal direction of the chip is long. In the figure, 1 ... Lead frame, 2 ... LSI chip 3 ... Bonding part 7, 70 ... Lead tip projection part 8 ... Chip Al bonding pad part 10 ... Polyimide passivation film 11 ... Soft silver paste, 12 …… Lead through hole 14 …… Multi-head microshrinkage 19 …… Heater block head

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Gen Murakami, 1450 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Masao Mitani 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi, Ltd., Production Engineering Laboratory

Claims (14)

[Claims] 1. A plurality of bonding pads of an LSI chip are provided on the chip, and a heat-resistant organic polymer film is provided on the surface of the chip excluding the pads, and the leads are thinner than external leads. At the tip of the internal lead extending in the LSI chip area, a protrusion having a thickness corresponding to the thickness of the external lead is provided corresponding to each pad portion, and a through hole is formed in the internal lead excluding the protrusion. And a gap is formed between the back surface of the internal lead and the front surface of the LSI chip by electrically connecting the protrusion portion and the pad portion with a conductive paste, and the LS including at least the gap.
A semiconductor device characterized in that an I chip and an internal lead are resin-sealed. 2. A bonding pad row of an LSI chip is localized and arranged at both ends of the chip so as to face each other, and a protrusion is provided at a tip of an internal lead corresponding to each pad of the pad row, The protrusions of the internal leads are electrically connected to the pads with a soft conductive paste, and the pad rows and the pin rows of the dual line package are arranged so as to be orthogonal to each other and are resin-sealed. The semiconductor device according to claim 1. 3. A plurality of bonding pad portions of an LSI chip are formed on a region of a chip where active elements are provided, and a projection portion is provided at the tip of the internal lead corresponding to each pad portion, 2. The semiconductor device according to claim 1, wherein the protruding portion and the pad portion are electrically connected with a soft conductive paste, and these are resin-sealed. 4. The semiconductor device according to claim 1, wherein the height of the protrusion provided at the tip of the inner lead is at least 30 μm. 5. The projection and the pad portion provided at the tip of the lead are bonded with a soft conductive silver paste having an elastic modulus of 10 to 400 kgf / mm ² , and the pads are bonded. The semiconductor device according to any one of item 4. 6. The tip of the lead including the protrusion has a thickness of 0.1 to 3 μm.
The semiconductor device according to any one of claims 1 to 5, wherein a gold plating layer of m is provided. 7. The semiconductor device according to claim 1, wherein the heat-resistant organic polymer film is a polyimide film. 8. The coefficient of linear expansion of the lead is 0.8 × 10 ^{−5 to} 1.4 × 10.
^-5 / ℃ made of iron-nickel alloy, resin for resin encapsulation contains spherical silica filler at least 70 ~ 80Vol%, the coefficient of linear expansion is 0.7 × 10 ^-5 ~ 1.4 × 10 ^-5 / ℃. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 9. A bonding pad of an LSI chip on the tip of the internal lead by selectively etching the internal lead region in the plate thickness direction while leaving the tip of the internal lead located on the LSI chip of the lead frame. Forming a protrusion for contacting the semiconductor chip, forming a through hole in the internal lead excluding the protrusion, and forming a heat-resistant organic polymer film on the surface of the LSI chip excluding the bonding pad A step of applying a conductive paste to a bonding pad portion of an LSI chip, a step of aligning the bonding pad portion and a protrusion of the lead, and the aligned lead frame and LSI
A step of pressing and heating the chip to connect the protruding portion at the tip of the lead to the bonding pad part of the LSI chip via the conductive paste, and a step of resin-sealing the LSI chip to which the lead is connected A method of manufacturing a semiconductor device, comprising: 10. The step of applying a conductive paste comprises:
10. The method for manufacturing a semiconductor device according to claim 9, wherein a silver paste having a viscosity of 50 to 1300 poise is applied to the bonding pad portion using a multi-microshrink. 11. The method for manufacturing a semiconductor device according to claim 9, wherein a multi-microshringe having an inner diameter of the nozzle of 0.3 mmφ or less is used. 12. The step of applying a conductive paste comprises:
The method for manufacturing a semiconductor device according to claim 9, wherein an ink-like paste having a viscosity of 500 to 10,000 poise is screen-printed through a mask. 13. A method for forming a protrusion on an end of a lead by etching one surface of the lead, the protrusion having a cylindrical shape and having a height of at least 30 μm. 10. A method of manufacturing a semiconductor device according to claim 9. 14. A linear expansion coefficient of 0.7 × 10 ^{−5 to} 1.4 × 10 ⁻⁵ / ° C.
10. The method for manufacturing a semiconductor device according to claim 9, wherein the resin sealing resin is used for transfer molding with a multipot.