JP2002217514A - Multichip semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multichip semiconductor device with deterioration of connection between substrates restrained, in which the substrates mounting components are laminated. SOLUTION: Electronic components 3-5 are mounted on a first substrate 1 and a second substrate 2, which are laminated with spacers 20 having leads 22 between them. Lands 1b, 2b for connection which are formed on a surface of the first substrate 1 and the back of the second substrate 2 are electrically connected via the leads 22. The leads 22 have elasticity so as to be able to bend by the thermal stress generated between the first substrate 1 and the second substrate 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip semiconductor device formed by stacking substrates on which semiconductor chips, passive components and the like are mounted.

[0002]

2. Description of the Related Art In recent years, in order to meet the demand for miniaturization of electronic equipment, high-density mounting of electronic components such as semiconductor chips and passive components in semiconductor devices has been required. As one of the methods, there is a multi-chip semiconductor device having a three-dimensional mounting without increasing the effective mounting area, that is, a laminated structure. This technology is disclosed in Japanese Patent No. 2541487 and Japanese Patent No. 2728432.

FIG. 8 is a schematic sectional view of such a multichip semiconductor device. As shown in FIG. 8, semiconductor chips and passive components (hereinafter, simply referred to as components) 103 are mounted on a plurality of substrates (two in the illustrated example) 101 and 102, and these substrates 101 and 102 are frame-shaped. Of the member (hereinafter,
(Hereinafter referred to as a frame) 104.

FIG. 9 is a view showing the frame 104 in detail, wherein (a) is a plan view and (b) is a side view.
As shown in FIG.
Connection lands 10 for electrically connecting to the first and the second 102
5 are formed, and the connection lands 105 on the front surface and the connection lands 105 on the back surface are electrically connected by the wiring portion 106 formed on the side surface of the frame 104. In addition,
These connection lands 105 and wiring portions 106 can be formed by plating or the like.

[0005] Then, as shown in FIG.
The connection land 107 formed on the frame 102 and the connection land 105 of the frame 104 are electrically connected via a connection member 108 such as a solder or a conductive paste.

[0006] With such a configuration, the parts 10
The mounting area when mounting 3 on a board such as a motherboard is:
It is not the sum of the mounting areas of all the components mounted on the semiconductor device, but the mounting area of the lowermost substrate of the stacked substrates 101 and 102. Therefore, the mounting area of the components can be significantly reduced, and the components can be mounted at a high density in the semiconductor device.

[0007]

However, the frame 1
The semiconductor device was operated because the materials of the upper and lower substrates 101 and 102 sandwiching 04 were different from each other, or the materials of the components 103 mounted on the upper and lower substrates were different from each other between the upper and lower substrates 101 and 102. Upper and lower substrates 10
If the degrees of thermal distortion of the substrates 1 and 102 are different, thermal stress is concentrated at a connection portion between the frame 104 and the substrates 101 and 102, and electrical connection between the substrates is likely to deteriorate.

As described above, the frame 104 and the substrates 101, 10
The reason why the thermal stress is concentrated at the connection portion with the substrate 2 is that the laminated substrates 101 and 102 and the frame 104 are completely fixed, and the thermal stress is not dispersed or absorbed. It is.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a multi-chip semiconductor device in which a substrate on which components are mounted is stacked, in which deterioration of connection between the substrates is suppressed. .

[0010]

In order to achieve the above object, according to the first aspect of the present invention, first and second substrates (1, 2) on which electronic components (3 to 5) are mounted are provided. And the first
In a multichip semiconductor device in which a first substrate and a second substrate are stacked with a spacer (20) interposed therebetween, the spacer is a lead (2) for electrically connecting the first and second substrates.
2), wherein the lead has elasticity so that it can bend by thermal strain generated between the first and second substrates.

Thus, when different thermal strains occur between the first and second substrates, the leads bend, thereby absorbing thermal stress caused by the different thermal strains. Therefore, the connection is secured without applying excessive thermal stress to the connection between the substrate and the lead, so that it is possible to provide a multi-chip semiconductor device in which the deterioration of the connection between the substrates is suppressed.

More specifically, a plurality of first lands (1b) are formed on a surface of the first substrate facing the second substrate, as in the second aspect of the present invention. A plurality of second lands (2b) are formed on a surface of the second substrate facing the first substrate, the spacer has a plurality of leads, and each of the first lands is connected to the second land. Are electrically connected to each other through each of the leads.

The reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) The embodiment shown in the drawings will be described below. FIG. 1 is a schematic sectional view of the multi-chip semiconductor device of the present embodiment. As shown in FIG. 1, electronic components 3 to 5 are mounted on a plurality of substrates 1 and 2. In the present embodiment, two substrates 1 and 2 are used. In FIG. 1, the substrate disposed on the lower side is referred to as a first substrate 1 and the substrate disposed on the upper side is referred to as a second substrate 2.
A printed board or a ceramic substrate can be used as the first and second substrates 1 and 2.
Is, for example, a motherboard.

On the surface of the first substrate 1, a component land 1a is provided.
Are formed, and the semiconductor chip 3 as an electronic component is electrically connected to the component land 1 a via the bump 6. The semiconductor chip 3 is mounted face down by a flip chip method. As the bump 6, solder, Au (gold), or the like can be used. The space between the semiconductor chip 3 and the first substrate 1 is filled with an underfill resin 7 to improve the thermal fatigue life of the connection due to the difference in the coefficient of thermal expansion between the semiconductor chip 3 and the first substrate 1. I try to make it.

On the surface of the second substrate 2, a semiconductor chip 4
Are joined face-up via the connection member 8. The semiconductor chip 4 and the second substrate 2 are electrically connected via wires 9 by a wire bonding method. Au or Al (aluminum) can be used as the wire 9. The semiconductor chip 4 and the wire 9 are sealed with a resin 10 and protected (for example, improvement in moisture resistance).

A passive component 5 such as a chip resistor or a chip capacitor as an electronic component is mounted on the surface of the second substrate 2. These passive components 5 are electrically connected to component lands 2 a formed on the surface of the second substrate 2 via connection members such as solder and conductive paste. The passive component 5 is mounted on the back surface of the second substrate 2 in the same manner as on the front surface.

The first substrate 1 and the second substrate 2 are stacked with a spacer 20 interposed therebetween. FIG. 2 is a plan view of the spacer 20. As shown in FIG. 2, the spacer 20 includes a frame-shaped member (hereinafter, referred to as a frame) 21 and a lead 22. A plurality of leads 22 are arranged on each side of the frame 21.

The frame 21 is made of, for example, epoxy resin, and the lead 22 is made of an electrically conductive member. Further, as described later, the leads 22 are elastic so that when connected to the first and second substrates 1 and 2, they can be bent by thermal strain generated between the first and second substrates 1 and 2. It has what has.

As these leads 22, a 42 alloy, a Cu alloy or the like can be used. Further, it is desirable that the first and second substrates 1 and 2 have thermal expansion coefficients close to each other. Specifically, when a glass epoxy substrate is used as the first and second substrates 1 and 2, a Cu alloy is used. And good.

Each of the leads 22 has a central portion disposed inside the frame 21 and fixed thereto, and has both ends in the thickness direction of the frame 21 of the frame 21 (in the direction of the first and second substrates 1 and 2). (In the line direction). One end of the lead 22 is bent upward and the other end is bent downward, so that each lead 22 has a gull-wing shape. Also,
The tips at both ends are plated with solder or the like.

Then, as shown in FIG. 1, the first substrate 1
A plurality of connection lands (first and second lands in the present invention) 1 b and 2 b are formed on the front surface of the second substrate 2 and the back surface of the second substrate 2. The connection lands 1b of the substrate 1 and the connection lands 2b of the second substrate 2 are electrically connected, and the first and second substrates 1 and 2 are connected.
Are electrically connected.

The lead 22 and the connecting lands 1b, 2b
Are electrically connected via a connection member such as solder or conductive paste. Also, the lead 22 is connected to the first and second leads.
In the state of being connected to the first and second substrates 1 and 2, there is a gap between the frame 21 and the first and second substrates 1 and 2.

When the multichip semiconductor device having such a configuration is operated and different thermal strains occur in the first and second substrates 1 and 2, the leads 22 bend.

In the present embodiment, the first
And the second substrates 1 and 2, and the frame 21 and the first
And the second substrates 1 and 2 are not bonded,
In the case where different thermal strains occur between the second substrate 2 and the second substrate 2, the leads 22 can bend.

Accordingly, since the thermal stress caused by the thermal strain can be absorbed by the leads 22, excessive thermal stress is applied to the connection between the first and second substrates 1, 2 and the leads 22. In this way, the connection between the first and second substrates 1 and 2 and the leads 22 can be ensured. Therefore, it is possible to provide a multi-chip semiconductor device in which the deterioration of the connection between the first and second substrates 1 and 2 is suppressed.

Next, a method of manufacturing a multi-chip semiconductor device having such a configuration will be described. First, the first and second
Various components 3 to 5 are mounted on the substrates 1 and 2.
These can be mounted by a known flip chip method, a wire bonding method, or the like. For the second substrate 2, after mounting components on one of the front and back surfaces,
It is sufficient to mount components on the other side.

Further, a spacer 20 is prepared. 3 to 5 are views showing a method of forming the spacer 20, wherein (a) is a plan view and (b) is a cross-sectional view taken along the line AA in (a).

First, a mold having a frame-shaped space (a mold or the like)
Prepare Then, as shown in FIG. 3, the lead member 23 in which the plurality of leads 22 are integrated is arranged in a mold (the mold is not shown).

Then, the softened resin constituting the frame 21 is injected into the mold, and the lead member 23 is molded. After the resin in the softened state is cured, the resin is taken out of the mold, and both ends of the lead member 23 project from the frame 21 as shown in FIG. In other words, QFP (Quad Flat P
The spacer 20 is formed in a form in which a core is placed in the ackage).

Thereafter, the connected portion of the lead member 23 is cut, and the end of the lead 22 is plated with solder or the like.
Then, both ends of the lead 22 protruding from the frame body 21 are bent upward and downward to obtain the state shown in FIG. Thus, the spacer 20 is completed. That is, the spacer 20 can be formed in the same manner as the mold package.

Then, the spacer 20 is connected to the first substrate 1.
The lead 22 is connected to a connection land 1b formed on the first substrate 1 via a connection member.
Then, the second substrate 2 is arranged on the spacer 20, and the connection lands 2b of the second substrate 2 and the leads 22 are connected via the connection members. Thus, the multichip semiconductor device of the present embodiment is completed.

(Second Embodiment) The present embodiment differs from the first embodiment in the shape of the spacer 20. Hereinafter, parts different from the first embodiment will be mainly described. FIGS. 6A and 6B are views partially showing one side of the frame 21 of the spacer 20 according to the present embodiment, wherein FIG. 6A is a plan view and FIG. 6B is a cross-sectional view.

As shown in FIG. 6, the center of the lead 22 is fixed inside the frame 21 and the second
Lead 22 from substantially the same height as one surface facing substrate 2
Are protruding at both ends. Both ends of the lead 22 are extended and bent toward the other surface opposite to the one surface of the frame 21.

FIG. 7 is a schematic sectional view showing a connection structure between the first and second substrates 1 and 2 when such a spacer 20 is used. As shown in FIG. 7, a spacer 20 is disposed between the first and second substrates 1 and 2, and the first and second substrates 1 and 2 are connected to the leads 22 via connecting members. At this time, the frame 21 and the second substrate 2 come into contact with each other, and a gap is formed between the frame 21 and the first substrate 1.

With such a configuration, the same effect as in the first embodiment can be exhibited.

(Other Embodiments) The spacer 20 having the structure shown in the second embodiment may be disposed between the first and second substrates 1 and 2 with the upside down of FIG. good. Further, the leads 22 are projected from both sides of the frame 21, but may be projected from only one side. Further, the frame body 21 and the second substrate 2 may be joined.

In each of the above embodiments, the spacer 20
Has been described as comprising a frame 21 and a lead 22, but a member composed of a linear member, an L-shaped member, or a U-shaped member and a lead 22 is used. May be.

In this case, if necessary, a plurality of linear members may be used, two L-shaped members may be used, or a U-shaped member and a linear member may be combined to form a spacer. 20 may be arranged in a frame shape. Further, instead of being arranged in a frame shape, they may be arranged in a U-shape or L-shape, or linear members may be arranged substantially in parallel.

In particular, the spacer 20 is formed by using a linear member.
In the case of the second embodiment, both ends of the lead 22 are projected from the same height as one surface of the linear member as in the second embodiment,
If the straight member is extended to the other surface side and bent, the spacer 20 can be stably arranged when the spacer 20 is arranged between the first and second substrates 1 and 2.

In each of the above embodiments, the lead 22 has a gull-wing shape.
It is desirable to make 2 flexible so that thermal stress can be more easily absorbed. Specifically, each lead 22 can be bent so as to have a Z-shape, or the number of times of bending can be increased. However, the leads 22 should be strong enough to support the second substrate 2 to some extent. The lead 22 may be made of a material having electrical conductivity and elasticity other than the 42 alloy and the Cu alloy.

Although the case where the spacer 20 is formed by molding has been described, the spacer 20 may be formed by sandwiching and bonding the lead 22 with a plate-like resin. In addition, the frame 21 and the spacer 20 that fixes the lead 22 using a ceramic substrate without using an epoxy resin as the U-shaped member or the U-shaped member may be used. May be used.

As the spacer 20, a lead 22 is used.
The central part of the lead 22 does not have to be fixed inside the frame 21, a linear member, an L-shaped member, or a U-shaped member, but the lead 22 may be exposed on the surface. Specifically, in the spacer 20 having the structure as shown in the second embodiment, the lead 22 is made to protrude even at a portion facing the second substrate 2, and the portion protruding from this surface and the second The connection lands 2b of the substrate 2 may be connected.

In the first embodiment, the structure may be such that the first and second substrates 1 and 2 and the frame 21 are in contact with each other. In the second embodiment, the first substrate 1 and the frame The configuration may be such that the body 21 is in contact with the body 21. Also, two layers of substrates 1, 2
Although the example of laminating is shown, three or more layers of substrates may be laminated.

When manufacturing such a multi-chip semiconductor device, the spacers 20 may be mounted simultaneously when various components are mounted on the first substrate 1.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a multi-chip semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the spacer according to the first embodiment of the present invention.

FIG. 3 is a schematic view illustrating a method for manufacturing a spacer according to the first embodiment of the present invention.

FIG. 4 is a schematic view showing a step following FIG. 3;

FIG. 5 is a schematic view showing a step following FIG. 4;

FIG. 6 is a schematic view of a spacer according to a second embodiment of the present invention.

FIG. 7 is a schematic sectional view partially showing a multi-chip semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a schematic sectional view of a conventional multi-chip semiconductor device.

FIG. 9 is a view showing a frame used in a conventional multi-chip semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st board | substrate, 1b ... Connection land (1st land), 2 ... 2nd board, 2b ... Connection land (2nd land), 3-5 ... Electronic components, 20 ... Spacer, 22 ... lead.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 1/18 3/36 F-term (Reference) 5E336 AA04 AA14 BB02 CC31 CC36 CC51 CC52 CC53 CC58 EE01 EE05 EE08 EE17 EE20 GG01 5E344 AA01 AA16 AA19 AA22 BB02 BB06 CC23 CD14 CD27 DD02 DD06 EE01

Claims (2)

[Claims] An electronic device includes first and second substrates (1 and 2) on which electronic components (3 to 5) are mounted, and the first and second substrates have a spacer (20) interposed therebetween. In the multi-chip semiconductor device formed by stacking, the spacer has a lead (22) for electrically connecting the first and second substrates, and the lead is provided between the first and second substrates. A multi-chip semiconductor device having elasticity so that it can be bent by thermal strain generated in the multi-chip semiconductor device. 2. A plurality of first lands (1b) are formed on a surface of the first substrate facing the second substrate, and a plurality of first lands are formed on the surface of the second substrate facing the first substrate. A plurality of second lands (2b) are formed on a surface to be formed, the spacer has a plurality of the leads, and each of the first lands and each of the second lands are 2. The multi-chip semiconductor device according to claim 1, wherein said multi-chip semiconductor device is electrically connected through each of said leads.