JP2001351946A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001351946A JP2001351946A JP2000167737A JP2000167737A JP2001351946A JP 2001351946 A JP2001351946 A JP 2001351946A JP 2000167737 A JP2000167737 A JP 2000167737A JP 2000167737 A JP2000167737 A JP 2000167737A JP 2001351946 A JP2001351946 A JP 2001351946A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- chip
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05563—Only on parts of the surface of the internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップ実
装方法を用いて、ＩＣチップを基板に実装した半導体装
置に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having an IC chip mounted on a substrate by using a flip chip mounting method.
【０００２】[0002]
【従来の技術】各種電子機器の小型・軽量化が進むにつ
れ、ＩＣチップなどの半導体部品を基板に直接実装する
ＣＯＢ（Chip on Board）技術や、パッケージの下面に
マトリックス状に半田ボールを配置して実装するＢＧＡ
（Ball Grid Array）技術などが開発されてきた。その
結果、単位面積あたりに、数多くのＩＣチップ−基板間
の接合部を形成することができ、高い集積度で半導体装
置を実装することができるようになった。2. Description of the Related Art As electronic devices become smaller and lighter, COB (Chip on Board) technology for directly mounting semiconductor components such as IC chips on a substrate, and solder balls arranged in a matrix on the lower surface of a package. BGA to mount
(Ball Grid Array) technology has been developed. As a result, many junctions between the IC chip and the substrate can be formed per unit area, and the semiconductor device can be mounted with a high degree of integration.
【０００３】図８および図９を参照しながら、従来式の
実装方法を用いて形成された半導体装置について説明す
る。図８は、従来式の半導体装置１０１の断面図であ
る。図８で示すように、この半導体装置１０１は、概
略、半導体ＩＣチップ部１０２、実装回路部１０３、お
よびこれらを接合する複数の接合部１０４（１０４ａな
いし１０４ｇを示す）から構成される。図９は、図８に
おいて最も左側（周縁）部に配置された接合部１０４ａ
の一部を拡大した図である。A semiconductor device formed by using a conventional mounting method will be described with reference to FIGS. FIG. 8 is a sectional view of a conventional semiconductor device 101. As shown in FIG. 8, the semiconductor device 101 generally includes a semiconductor IC chip section 102, a mounting circuit section 103, and a plurality of joining sections 104 (showing 104a to 104g) for joining them. FIG. 9 shows the joining portion 104a arranged at the leftmost (peripheral) portion in FIG.
It is the figure which expanded a part of.
【０００４】半導体ＩＣチップ部１０２は、ＩＣチップ
１１０、ダイボンド樹脂１１１、およびＩＣチップ１１
０を保護するためのモールド樹脂１１２を有している。
ＩＣチップ１１０は、ダイボンド樹脂１１１の上に搭載
されており、外部回路に接続すべき複数のＩＣチップ端
子（図示せず）を有する。このＩＣチップ端子は、各
々、金線１１３およびダイボンド樹脂１１１上のパター
ン配線（図示せず）を介して、ダイボンド樹脂１１１の
下側表面に形成されたＩＣパッド１１４と接続してい
る。半導体ＩＣチップ部１０２は、さらに、ＩＣパッド
１１４を包囲するように、ガラスエポキシ樹脂で形成さ
れたインタポーザ１１５を有する。The semiconductor IC chip section 102 includes an IC chip 110, a die bond resin 111, and an IC chip 11.
0 has a mold resin 112 for protection.
The IC chip 110 is mounted on the die bond resin 111 and has a plurality of IC chip terminals (not shown) to be connected to an external circuit. Each of the IC chip terminals is connected to an IC pad 114 formed on the lower surface of the die bond resin 111 via a gold wire 113 and a pattern wiring (not shown) on the die bond resin 111. The semiconductor IC chip unit 102 further has an interposer 115 formed of glass epoxy resin so as to surround the IC pad 114.
【０００５】各接合部１０４は、例えば、スクリーン印
刷法などにより、各ＩＣパッド１１４上に半田などで形
成される。[0005] Each joint portion 104 is formed on each IC pad 114 by soldering or the like by, for example, a screen printing method.
【０００６】実装回路部１０３は、ガラスエポキシ樹脂
などにより形成された実装基板１２０と、複数の基板パ
ッド１２１から構成される。半導体ＩＣチップ部１０２
と実装回路部１０３は、図９で示すように、基板パッド
１２１と接合部１０４の各々が互いに対向するように配
置された状態でリフロー処理される。こうして、半導体
ＩＣチップ部１０２が実装回路部１０３に接合された半
導体装置１０１を形成する。The mounting circuit section 103 includes a mounting substrate 120 formed of a glass epoxy resin or the like, and a plurality of substrate pads 121. Semiconductor IC chip section 102
As shown in FIG. 9, the mounting circuit section 103 and the mounting circuit section 103 are subjected to reflow processing in a state where the substrate pad 121 and the bonding section 104 are arranged so as to face each other. Thus, the semiconductor device 101 in which the semiconductor IC chip unit 102 is joined to the mounting circuit unit 103 is formed.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、形成さ
れた従来式の半導体装置１０１について、温度サイクル
試験（例えば、−２５℃〜＋１２０℃）を実施すると、
半導体ＩＣチップ部１０２と接合部１０４の接合界面付
近、および実装回路部１０３と接合部１０２の接合界面
付近において、接合部１０４が破断（断線）するという
不具合が多発した。However, when a temperature cycle test (for example, −25 ° C. to + 120 ° C.) is performed on the formed conventional semiconductor device 101,
In the vicinity of the bonding interface between the semiconductor IC chip portion 102 and the bonding portion 104 and the vicinity of the bonding interface between the mounting circuit portion 103 and the bonding portion 102, there were many problems that the bonding portion 104 was broken (disconnected).
【０００８】この接合部１０４の破断（断線）のメカニ
ズムについて、図８ないし図１１を参照して説明する。
ＩＣチップ１１０は、通常、シリコンなどの半導体から
形成され、例えば、約３．５×１０-6／℃の熱膨張係数
を有する。一方、実装基板１２０は、上述のように、ガ
ラスエポキシ樹脂などにより形成され、例えば、約１４
×１０-6／℃の熱膨張係数を有する。つまり、実装基板
１２０は、ＩＣチップ１１０に比べて、一般に、大きい
熱膨張係数を有する。したがって、所定の温度変化によ
り膨張する度合いは、実装基板１２０の方がＩＣチップ
１１０よりも、はるかに大きい。図８および図９におい
て、ＩＣチップ１１０が膨張するときの変位ベクトルを
矢印Ａ（ベクトル）、および実装基板１２０が膨張する
ときの変位ベクトルを矢印Ｂ（ベクトル）で示す。これ
らの図で示すように、実装基板１２０の変位ベクトルＢ
は、ＩＣチップ１１０の変位ベクトルＡよりも、はるか
に大きい。とりわけ、半導体チップ部１０２と実装回路
部１０３の中央部よりも両端（周縁）部において、両者
の変位ベクトルＡ、Ｂの差異は大きくなる。The mechanism of breakage (breakage) of the joint 104 will be described with reference to FIGS.
The IC chip 110 is usually formed from a semiconductor such as silicon, and has a thermal expansion coefficient of, for example, about 3.5 × 10 −6 / ° C. On the other hand, the mounting substrate 120 is formed of glass epoxy resin or the like as described above,
It has a coefficient of thermal expansion of × 10 -6 / ° C. That is, the mounting substrate 120 generally has a larger thermal expansion coefficient than the IC chip 110. Therefore, the degree of expansion due to a predetermined temperature change is much greater in the mounting substrate 120 than in the IC chip 110. 8 and 9, a displacement vector when the IC chip 110 expands is indicated by an arrow A (vector), and a displacement vector when the mounting substrate 120 expands is indicated by an arrow B (vector). As shown in these figures, the displacement vector B
Is much larger than the displacement vector A of the IC chip 110. In particular, the difference between the displacement vectors A and B at both ends (peripheral edges) of the semiconductor chip portion 102 and the mounting circuit portion 103 is larger than the center portion.
【０００９】図９は、図８の最も左側にある接合部１０
４ａ付近を拡大した図である。このとき、ＩＣチップ１
１０と実装基板１２０の間に介在する接合部１０４ａ
は、変位ベクトルＡ、Ｂの差異に起因して、ＩＣチップ
１１０に対して水平方向左側に歪み応力Ｆ1を受け、実
装基板１２０に対しては反対方向である右側に同じ大き
さの歪み応力Ｆ2を受ける。なお、上述のように、変位
ベクトルＡ、Ｂの差異は、半導体チップ部１１０と実装
回路部１２０の中央部よりも両端（周縁）部において大
きくなるので、歪み応力Ｆ1、Ｆ2も同様に、半導体チッ
プ部１０２と実装回路部１０３の両端（周縁）部におい
て大きくなる。FIG. 9 shows the leftmost joint 10 in FIG.
It is the figure which expanded the vicinity of 4a. At this time, IC chip 1
Joint 104a Interposed Between 10 and Mounting Board 120
Receives the strain stress F 1 on the left side in the horizontal direction with respect to the IC chip 110 due to the difference between the displacement vectors A and B, and the same magnitude of the strain stress on the right side, which is the opposite direction to the mounting substrate 120. receive the F 2. As described above, the difference between the displacement vectors A and B is larger at both ends (periphery) than at the center of the semiconductor chip unit 110 and the mounting circuit unit 120, so that the strain stresses F 1 and F 2 are also the same. At both ends (periphery) of the semiconductor chip portion 102 and the mounting circuit portion 103.
【００１０】さらに、図示しないが、変位ベクトルＡ、
Ｂの差異に起因して、実装基板１２０は、下に凸（ＩＣ
チップ１１０とは反対側の方向に凸）となるように湾曲
してしまう。その結果、ＩＣチップ１１０と実装基板１
２０の間に介在する各接合部１０４は、ＩＣチップ１１
０に対して垂直方向下側に湾曲応力ｆ1を受け、実装基
板１２０に対しては反対方向である上側に同じ大きさの
湾曲応力ｆ2を受けることになる。湾曲応力ｆ1、ｆ2の
大きさは、歪み応力Ｆ1ほど大きくはないが、歪み応力
と同様、半導体チップ部１０２と実装回路部１０３の中
央部よりも両端（周縁）部において大きくなる。Further, although not shown, displacement vectors A,
B, the mounting substrate 120 is convex downward (IC
(The convex in the direction opposite to the tip 110). As a result, the IC chip 110 and the mounting substrate 1
20 are connected to the IC chip 11.
The bending stress f 1 is received on the lower side in the direction perpendicular to 0, and the same level of bending stress f 2 is received on the upper side, which is the opposite direction to the mounting substrate 120. The magnitudes of the bending stresses f 1 and f 2 are not as large as the strain stress F 1, but are larger at both ends (peripheral edges) than at the center of the semiconductor chip portion 102 and the mounting circuit portion 103, like the strain stress.
【００１１】ところで、接合部１０４は、ＩＣパッド１
１４および基板パッド１２１との間に、ＩＣ−接合界面
１１７および基板−接合界面１２３をそれぞれ有してお
り、両者接合界面１１７、１２３付近は、一般に、合金
層が形成されているので、水平方向の歪み応力Ｆ1、Ｆ2
や垂直方向の湾曲応力ｆ1、ｆ2に対して比較的に脆弱で
ある。したがって、温度サイクル試験や実使用における
温度変化に伴って、上述のような歪み応力Ｆ1、Ｆ2およ
び湾曲応力ｆ1、ｆ2が生じると、例えば、図１０で示す
ように、基板−接合界面１２３付近に亀裂１２４が生
じ、さらに、反復的な温度変化により、この亀裂１２３
が拡大し、図１１で示すように、ついには破断（断線）
に至る。図１１は、基板−接合界面１２３に亀裂が生じ
て断線した様子を示す図であるが、ＩＣ−接合界面１１
７付近にも同様に亀裂が生じて断線に至る。By the way, the bonding portion 104 is connected to the IC pad 1
14 and the substrate pad 121, an IC-bonding interface 117 and a substrate-bonding interface 123 are respectively provided. In the vicinity of the bonding interfaces 117 and 123, generally, an alloy layer is formed. Strain stresses F 1 and F 2
And are relatively vulnerable to bending stresses f 1 and f 2 in the vertical direction. Therefore, when the above-described strain stresses F 1 and F 2 and the bending stresses f 1 and f 2 are generated due to a temperature change in a temperature cycle test or actual use, for example, as shown in FIG. A crack 124 is formed near the interface 123, and further, due to a repetitive temperature change, this crack 123
Expands and finally breaks (disconnection) as shown in FIG.
Leads to. FIG. 11 is a diagram showing a state in which a crack is generated in the substrate-bonding interface 123 and the wire is disconnected.
Similarly, a crack is generated near 7 and the wire is broken.
【００１２】そこで、本発明は、温度変化に伴って生じ
る歪み応力および湾曲応力に耐える、信頼性の高い半導
体装置を提供することを目的とする。Accordingly, an object of the present invention is to provide a highly reliable semiconductor device that can withstand a strain stress and a bending stress generated by a temperature change.
【００１３】[0013]
【課題を解決するための手段】請求項１に記載の本発明
によれば、複数のＩＣ電極部が一方の表面に形成された
半導体ＩＣチップ部と、複数の基板電極部が一方の表面
に形成された実装基板部と、ＩＣ電極部と対応する基板
電極部を接合する複数の接合部とを備えた半導体装置に
おいて、ＩＣ電極部が、該ＩＣ電極部に固定され、接合
部内部に突出する第１の突出部を有し、基板電極部が、
該基板電極部に固定され、接合部内部に突出する第２の
突出部を有する。これにより、第１および第２の突出部
が、接合部およびＩＣ電極部と、接合部および基板電極
部の間の接合界面における両者の接合強度を補強し、こ
れらの接合界面で断線しにくい、信頼性の高い半導体装
置を提供することができる。According to the present invention, a semiconductor IC chip portion having a plurality of IC electrode portions formed on one surface and a plurality of substrate electrode portions are formed on one surface. In a semiconductor device having a formed mounting substrate portion and a plurality of bonding portions for bonding a substrate electrode portion corresponding to an IC electrode portion, the IC electrode portion is fixed to the IC electrode portion and protrudes into the bonding portion. A first protruding portion, and the substrate electrode portion has
A second protrusion fixed to the substrate electrode portion and protruding into the joint; As a result, the first and second protrusions reinforce the bonding strength between the bonding portion and the IC electrode portion and the bonding interface between the bonding portion and the substrate electrode portion, and are less likely to break at the bonding interface. A highly reliable semiconductor device can be provided.
【００１４】請求項２に記載の本発明によれば、第１お
よび第２の突出部が、接合部以上の弾性係数（剛性率）
を有する。これにより、第１および第２の突出部は、接
合部以上に硬いので、接合部およびＩＣ電極部と、接合
部および基板電極部の間の接合界面における両者の接合
強度をより十分に補強し、これらの接合界面でより断線
しにくい、より信頼性の高い半導体装置を提供すること
ができる。According to the second aspect of the present invention, the first and second projections have an elastic coefficient (rigidity) equal to or higher than the joint.
Having. Accordingly, the first and second protrusions are harder than the joints, and therefore, the joint strength between the joints and the IC electrode part and the joint interface between the joints and the substrate electrode part are more sufficiently reinforced. It is possible to provide a more reliable semiconductor device that is less likely to be disconnected at these bonding interfaces.
【００１５】請求項３に記載の本発明によれば、第１お
よび第２の突出部が、接合部以上の融点を有する。これ
により、第１および第２の突出部は、接合部以上に硬い
ので、接合部およびＩＣ電極部と、接合部および基板電
極部の間の接合界面における両者の接合強度をより十分
に補強し、これらの接合界面でより断線しにくい、より
信頼性の高い半導体装置を提供することができる。According to the third aspect of the present invention, the first and second protrusions have a melting point higher than that of the joint. Accordingly, the first and second protrusions are harder than the joints, and therefore, the joint strength between the joints and the IC electrode part and the joint interface between the joints and the substrate electrode part are more sufficiently reinforced. It is possible to provide a more reliable semiconductor device that is less likely to be disconnected at these bonding interfaces.
【００１６】請求項４に記載の本発明によれば、接合部
が半田材からなる。これにより、例えば、スクリーン印
刷法などを用いて、第１および第２の突出部を、安価に
大量生産するとともに、信頼性の高い半導体装置を提供
することができる。According to the present invention, the joint is made of a solder material. This makes it possible to mass-produce the first and second protrusions at low cost by using, for example, a screen printing method, and to provide a highly reliable semiconductor device.
【００１７】請求項５に記載の本発明によれば、半導体
ＩＣチップ部と実装基板部の表面と垂直な断面を有し、
半導体ＩＣチップ部と実装基板部の熱膨張係数が異な
り、第１および第２の突出部が、周囲温度変化に伴って
接合部に負荷される水平方向の歪み応力を緩和するよう
な垂直断面形状を有する。これにより、水平方向の歪み
応力に耐える、信頼性の高い半導体装置を提供すること
ができる。According to the fifth aspect of the present invention, the semiconductor device has a cross section perpendicular to the surfaces of the semiconductor IC chip portion and the mounting substrate portion,
The semiconductor IC chip portion and the mounting substrate portion have different thermal expansion coefficients, and the first and second protrusions have a vertical cross-sectional shape that relieves the horizontal strain stress applied to the joint due to a change in ambient temperature. Having. Thus, a highly reliable semiconductor device that can withstand horizontal strain stress can be provided.
【００１８】請求項６に記載の本発明によれば、第１お
よび第２の突出部の垂直断面形状が、矩形である。これ
により、水平方向の歪み応力に耐える、信頼性の高い半
導体装置を提供することができる。According to the present invention, the vertical cross-sectional shape of the first and second protrusions is rectangular. Thus, a highly reliable semiconductor device that can withstand horizontal strain stress can be provided.
【００１９】請求項７に記載の本発明によれば、第１お
よび第２の突出部の垂直断面形状が、周囲温度変化に伴
って接合部に負荷される水平方向の歪み応力を緩和する
ような実質的に垂直な辺を含む三角形である。これによ
り、水平方向の歪み応力に耐える、信頼性の高い半導体
装置を提供することができる。According to the present invention, the vertical cross-sectional shape of the first and second protrusions relieves the horizontal strain stress applied to the joint due to a change in ambient temperature. Is a triangle including substantially vertical sides. Thus, a highly reliable semiconductor device that can withstand horizontal strain stress can be provided.
【００２０】請求項８に記載の本発明によれば、半導体
ＩＣチップ部と実装基板部の表面と垂直な断面を有し、
半導体ＩＣチップ部と実装基板部の熱膨張係数が異な
り、第１および第２の突出部が、周囲温度変化に伴って
接合部に負荷される垂直方向の湾曲応力を緩和するよう
な垂直断面形状を有する。これにより、垂直方向の湾曲
歪み応力に耐える、信頼性の高い半導体装置を提供する
ことができる。According to the present invention, the semiconductor device has a cross section perpendicular to the surfaces of the semiconductor IC chip portion and the mounting substrate portion,
A vertical cross-sectional shape in which the semiconductor IC chip part and the mounting substrate part have different thermal expansion coefficients, and the first and second protrusions relieve a vertical bending stress applied to the joint due to a change in ambient temperature. Having. This makes it possible to provide a highly reliable semiconductor device that can withstand vertical bending strain stress.
【００２１】請求項９に記載の本発明によれば、第１の
突出部の垂直断面形状が、台形であり、第２の突出部の
垂直断面形状が、逆台形である。これにより、水平方向
の歪み応力および垂直方向の湾曲歪み応力に耐える、信
頼性の高い半導体装置を提供することができる。According to the ninth aspect of the present invention, the vertical cross section of the first protrusion is trapezoidal, and the vertical cross section of the second protrusion is inverted trapezoid. This makes it possible to provide a highly reliable semiconductor device that withstands horizontal distortion stress and vertical distortion stress.
【００２２】請求項１０に記載の本発明によれば、第１
および第２の突出部が、ＩＣ電極部および基板電極部と
一体成形される。これにより、ＩＣ突出部１６および基
板突出部２２を別途形成する必要がないので、工程を簡
略化することができる。さらに、第１の突出部およびＩ
Ｃ電極部と、第２の突出部および基板電極部の間の接合
界面は、突出部および電極部を各々別途形成する場合に
比較して、両者の接合強度を最大化することができるの
で、より信頼性の高い半導体装置を提供することができ
る。According to the tenth aspect of the present invention, the first
And the second protrusion is integrally formed with the IC electrode portion and the substrate electrode portion. This eliminates the need to separately form the IC protrusion 16 and the substrate protrusion 22, thereby simplifying the process. Further, the first protrusion and I
Since the bonding interface between the C electrode portion, the second protruding portion and the substrate electrode portion can maximize the bonding strength between them, as compared with the case where the protruding portion and the electrode portion are separately formed, A more reliable semiconductor device can be provided.
【００２３】請求項１１に記載の本発明によれば、複数
のＩＣ電極部が一方の表面に形成された半導体ＩＣチッ
プ部と、複数の基板電極部が一方の表面に形成された実
装基板部と、ＩＣ電極部と対応する基板電極部を接合す
る複数の接合部とを備えた半導体装置において、半導体
ＩＣチップ部と実装基板部の表面と垂直な断面を有し、
ＩＣ電極部と接合部の接合界面における垂直断面形状
が、複数の凹凸状または鋸状である。これにより、ＩＣ
電極部と接合部の接合強度を向上させ、信頼性の高い半
導体装置を提供することができる。According to the eleventh aspect of the present invention, a semiconductor IC chip portion having a plurality of IC electrode portions formed on one surface and a mounting substrate portion having a plurality of board electrode portions formed on one surface. And a semiconductor device having a plurality of bonding portions for bonding the IC electrode portion and the corresponding substrate electrode portion, the semiconductor device having a cross section perpendicular to the surfaces of the semiconductor IC chip portion and the mounting substrate portion,
The vertical cross-sectional shape at the bonding interface between the IC electrode portion and the bonding portion is a plurality of irregularities or saw-like shapes. Thereby, IC
The bonding strength between the electrode portion and the bonding portion can be improved, and a highly reliable semiconductor device can be provided.
【００２４】請求項１２に記載の本発明によれば、複数
のＩＣ電極部が一方の表面に形成された半導体ＩＣチッ
プ部と、複数の基板電極部が一方の表面に形成された実
装基板部と、ＩＣ電極部と対応する基板電極部を接合す
る複数の接合部とを備えた半導体装置において、半導体
ＩＣチップ部と実装基板部の表面と垂直な断面を有し、
基板電極部と接合部の接合界面における垂直断面形状
が、複数の凹凸状または鋸状である。これにより、基板
電極部と接合部の接合強度を向上させ、信頼性の高い半
導体装置を提供することができる。According to the present invention, a semiconductor IC chip portion having a plurality of IC electrode portions formed on one surface and a mounting substrate portion having a plurality of board electrode portions formed on one surface. And a semiconductor device having a plurality of bonding portions for bonding the IC electrode portion and the corresponding substrate electrode portion, the semiconductor device having a cross section perpendicular to the surfaces of the semiconductor IC chip portion and the mounting substrate portion,
The vertical cross-sectional shape at the bonding interface between the substrate electrode portion and the bonding portion is a plurality of irregularities or saw-like shapes. Thus, the bonding strength between the substrate electrode portion and the bonding portion can be improved, and a highly reliable semiconductor device can be provided.
【００２５】[0025]
【発明の実施の形態】図面を参照しながら、以下に、本
発明に係る半導体装置の実施利の形態について説明す
る。各実施の形態の説明において、理解を容易にするた
めに方向を表す用語（例えば、「上部」、「下部」、
「右側」、「左側」等）を適宜用いるが、これは説明の
ためのものであって、これらの用語は本発明を限定する
ものでない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. In the description of the embodiments, terms indicating directions (for example, “upper”, “lower”,
“Right”, “left”, etc.) are used as appropriate, but this is for explanation only, and these terms do not limit the invention.
【００２６】実施の形態１．図１および図２を参照しな
がら、本発明に係る半導体装置の実施の形態１について
説明する。図１は、実施の形態１による半導体装置１の
断面図である。図１で示すように、この半導体装置１
は、概略、半導体ＩＣチップ部２、実装回路部３、およ
びこれらを接合する複数の接合部４（４ａないし４ｇを
示す）から構成される。図２は、図１において最も左側
（周縁）部に配置された接合部４ａの一部を拡大した図
である。Embodiment 1 First Embodiment A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a semiconductor device 1 according to the first embodiment. As shown in FIG. 1, this semiconductor device 1
Generally comprises a semiconductor IC chip section 2, a mounting circuit section 3, and a plurality of joining sections 4 (showing 4a to 4g) for joining them. FIG. 2 is an enlarged view of a part of the joint 4a disposed at the leftmost (peripheral) portion in FIG.
【００２７】半導体ＩＣチップ部２は、ＩＣチップ１
０、ダイボンド樹脂１１、およびＩＣチップ１０を保護
するためのモールド樹脂１２を有している。ＩＣチップ
１０は、ダイボンド樹脂１１の上に搭載されており、外
部回路に接続すべき複数のＩＣチップ端子（図示せず）
を有する。このＩＣチップ端子は、各々、金線１３およ
びダイボンド樹脂１１上のパターン配線（図示せず）を
介して、ダイボンド樹脂１１の下側表面に形成されたＩ
Ｃパッド１４と接続している。さらに、半導体ＩＣチッ
プ部２は、ＩＣパッド１４を包囲するように、ガラスエ
ポキシ樹脂で形成されたインタポーザ１５を有する。ま
た、ＩＣパッド１４は、後述の接合される接合部４との
間にＩＣ−接合界面１７を有する。The semiconductor IC chip unit 2 includes an IC chip 1
0, a die bond resin 11, and a mold resin 12 for protecting the IC chip 10. The IC chip 10 is mounted on the die bond resin 11 and has a plurality of IC chip terminals (not shown) to be connected to an external circuit.
Having. The IC chip terminals are formed on the lower surface of the die bond resin 11 via the gold wire 13 and the pattern wiring (not shown) on the die bond resin 11, respectively.
Connected to C pad 14. Further, the semiconductor IC chip unit 2 has an interposer 15 formed of glass epoxy resin so as to surround the IC pad 14. Further, the IC pad 14 has an IC-bonding interface 17 between the IC pad 14 and a bonding portion 4 to be bonded later.
【００２８】さらに、本発明の半導体ＩＣチップ部２
は、ＩＣパッド１４にしっかりと固定され、下方向に突
出するＩＣ突出部１６を有する。この状態で、各接合部
４が、例えば、スクリーン印刷法などにより、各ＩＣパ
ッド１４上に半田などで形成される。Further, the semiconductor IC chip part 2 of the present invention
Has an IC protruding portion 16 which is firmly fixed to the IC pad 14 and protrudes downward. In this state, each joint 4 is formed on each IC pad 14 by solder or the like by, for example, a screen printing method.
【００２９】このＩＣ突出部１６は、任意の材料で構成
することができるが、高い弾性係数（剛性率）を有する
ことが望ましい。さらに、接合部４が、上述の温度変化
に伴い、ＩＣパッド１４に対して水平左側方向の歪み応
力（Ｆ1、図８参照）を受けた場合であっても、ＩＣ突
出部１６が、ＩＣパッド１４と接合部の間の接合強度を
補強して、接合部４のＩＣ−接合界面１７において亀裂
が生じることを防止できるように、ＩＣ突出部１６はＩ
Ｃパッド１４に強固に固定されなければならない。The IC protrusion 16 can be made of any material, but preferably has a high elastic coefficient (rigidity). Further, even when the joint 4 receives a horizontal leftward strain stress (F 1 , see FIG. 8) with respect to the IC pad 14 due to the above-described temperature change, the IC protrusion 16 is The IC protrusion 16 is provided with an I-shaped protrusion 16 so as to reinforce the bonding strength between the pad 14 and the bonding portion and prevent a crack from being generated at the IC-bonding interface 17 of the bonding portion 4.
It must be firmly fixed to the C pad 14.
【００３０】実装回路部３は、ガラスエポキシ樹脂など
により形成された実装基板２０と、複数の基板パッド２
１から構成される。また、基板パッド２１は、接合され
る接合部４との間に基板−接合界面２３を有する。さら
に、実装回路部３は、基板パッド２１にしっかりと固定
され、上方向に突出する基板突出部２２を有する。こう
して、半導体ＩＣチップ部２と実装回路部３は、図２で
示すように、基板パッド２１と接合部４の各々が互いに
対向するように配置された状態でリフロー処理される。
これにより、半導体ＩＣチップ部２が実装回路部３に接
合された半導体装置１を形成することができる。The mounting circuit section 3 includes a mounting board 20 formed of glass epoxy resin or the like and a plurality of board pads 2.
1 Further, the substrate pad 21 has a substrate-bonding interface 23 between the substrate pad 21 and the bonding portion 4 to be bonded. Further, the mounting circuit section 3 has a board protruding section 22 that is firmly fixed to the board pad 21 and protrudes upward. Thus, the semiconductor IC chip section 2 and the mounting circuit section 3 are subjected to reflow processing in a state where the substrate pad 21 and the bonding section 4 are arranged so as to face each other, as shown in FIG.
Thereby, the semiconductor device 1 in which the semiconductor IC chip unit 2 is joined to the mounting circuit unit 3 can be formed.
【００３１】同様に、この基板突出部２２は、任意の材
料で構成することができるが、高い弾性係数（剛性率）
を有することが望ましい。さらに、接合部４が、上述の
温度変化に伴い、基板パッド２０に対して水平右側方向
の歪み応力（Ｆ2、図８参照）温度変化に伴って水平方
向の歪み応力が生じた場合であっても、基板突出部２２
が、基板パッド２１と接合部４の間の接合強度を補強し
て、接合部４の基板−接合界面２３において亀裂が生じ
ることを防止できるように、基板突出部２２は基板パッ
ド２１に強固に固定されなければならない。Similarly, the substrate projection 22 can be made of any material, but has a high elastic modulus (rigidity).
It is desirable to have Further, the joint 4 causes a horizontal right-sided strain stress (F 2 , see FIG. 8) with respect to the substrate pad 20 due to the above-described temperature change. However, the substrate protrusion 22
However, the substrate protruding portion 22 is firmly attached to the substrate pad 21 so that the bonding strength between the substrate pad 21 and the bonding portion 4 is reinforced and a crack is prevented from being generated at the substrate-bonding interface 23 of the bonding portion 4. Must be fixed.
【００３２】このように構成されたＩＣ突出部１６と基
板突出部２２は、一般に、合金層で形成された接合部４
のＩＣ−接合界面１７および基板−接合界面２３におい
て、ＩＣパッド部１４および接合部４と、基板パッド部
２１および接合部４の間の接合強度を補強し、たとえ、
温度サイクル試験や半導体装置の動作オン・オフによる
温度変化に伴う水平方向の歪み応力Ｆ1、Ｆ2が生じて
も、接合部４の上記接合界面１７、２３に亀裂が生じる
ことを防止することができる。こうして、温度変化に伴
って生じる歪み応力に耐える、信頼性の高い半導体装置
を実現することができる。The IC protrusion 16 and the substrate protrusion 22 configured as described above are generally connected to the joint 4 formed of an alloy layer.
In the IC-bonding interface 17 and the substrate-bonding interface 23, the bonding strength between the IC pad portion 14 and the bonding portion 4 and the substrate pad portion 21 and the bonding portion 4 is reinforced.
Even if horizontal strain stresses F 1 and F 2 are generated due to a temperature change due to a temperature cycle test and a temperature change due to operation ON / OFF of the semiconductor device, cracks are prevented from being generated at the bonding interfaces 17 and 23 of the bonding portion 4. Can be. Thus, a highly reliable semiconductor device that can withstand the strain stress generated due to the temperature change can be realized.
【００３３】実施の形態２．図３を参照して、実施の形
態２による半導体装置１について説明する。実施の形態
２の半導体装置１は、ＩＣ突出部１６と基板突出部２２
の垂直断面形状が異なる点以外は、実施の形態１の半導
体装置１と同様に構成されているので、詳細な説明を省
略する。Embodiment 2 FIG. The semiconductor device 1 according to the second embodiment will be described with reference to FIG. The semiconductor device 1 according to the second embodiment includes an IC protrusion 16 and a substrate protrusion 22.
Since the configuration is the same as that of the semiconductor device 1 of the first embodiment except that the vertical cross-sectional shape is different, detailed description will be omitted.
【００３４】実施の形態１のＩＣ突出部１６と基板突出
部２２は、円柱または多角柱の形状を有する一方、実施
の形態２のそれらは、図３で示すように、接合部４に向
かって広がる（より広い底面積を有する）円錐台または
角錐台の垂直断面形状を有する。つまり、ＩＣ突出部１
６が台形断面形状を有し、基板突出部２２が逆台形断面
形状を有する。The IC projecting portion 16 and the substrate projecting portion 22 of the first embodiment have a columnar or polygonal column shape, while those of the second embodiment have a shape toward the joint 4 as shown in FIG. It has a frustoconical or truncated pyramid vertical cross-sectional shape that expands (has a wider base area). That is, the IC protrusion 1
6 has a trapezoidal cross section, and the substrate projection 22 has an inverted trapezoidal cross section.
【００３５】上述のように、接合部４は、ＩＣチップ１
０に対しては垂直方向下側に湾曲応力ｆ1を受け、実装
基板２０に対しては反対方向である上側に同じ大きさの
湾曲応力ｆ2を受ける。しかし、ＩＣ突出部１６と基板
突出部２２を図３で示すような形状で構成した場合、こ
れら突出部１６、２２が垂直方向の湾曲応力ｆ1、ｆ2を
吸収し、接合部４が受ける湾曲応力ｆ1、ｆ2を低減する
ことができる。その結果、たとえ、温度サイクル試験や
半導体装置の動作オン・オフによる温度変化に伴う垂直
方向の湾曲応力ｆ1、ｆ2が生じても、接合部４の上記接
合界面１７、２３で亀裂が生じることを防止することが
できる。こうして、温度変化に伴って生じる湾曲応力に
も同様に耐える、より信頼性の高い半導体装置を実現す
ることができる。As described above, the bonding portion 4 is connected to the IC chip 1
For 0, a bending stress f 1 is received on the lower side in the vertical direction, and on the mounting board 20, a bending stress f 2 of the same magnitude is received on the upper side in the opposite direction. However, when the IC protruding portion 16 and the substrate protruding portion 22 are configured as shown in FIG. 3, these protruding portions 16 and 22 absorb the vertical bending stresses f 1 and f 2, and are received by the joint portion 4. The bending stresses f 1 and f 2 can be reduced. As a result, even if vertical bending stresses f 1 and f 2 are generated due to a temperature change due to a temperature cycle test or a temperature change due to operation on / off of the semiconductor device, cracks are generated at the bonding interfaces 17 and 23 of the bonding portion 4. Can be prevented. In this manner, a more reliable semiconductor device that can withstand a bending stress caused by a temperature change similarly can be realized.
【００３６】実施の形態３．図４を参照して、実施の形
態３による半導体装置１について説明する。実施の形態
３の半導体装置１は、ＩＣ突出部１６と基板突出部２２
の垂直断面形状が異なる点以外は、実施の形態１の半導
体装置１と同様に構成されているので、詳細な説明を省
略する。Embodiment 3 FIG. The semiconductor device 1 according to the third embodiment will be described with reference to FIG. The semiconductor device 1 according to the third embodiment includes an IC protrusion 16 and a substrate protrusion 22.
Since the configuration is the same as that of the semiconductor device 1 of the first embodiment except that the vertical cross-sectional shape is different, detailed description will be omitted.
【００３７】図８を用いて説明したように、温度変化に
伴う水平方向の歪み応力Ｆ1、Ｆ2は、接合部４の半導体
装置１における位置に依存する。つまり、図１で示す接
合部４ａないし４ｃがＩＣ基板１０に対して受ける歪み
応力Ｆ1は、水平左側方向であり、逆に、実装基板２０
に対して受ける歪み応力Ｆ2は、水平右側方向である。As described with reference to FIG. 8, the horizontal strain stresses F 1 and F 2 due to the temperature change depend on the position of the junction 4 in the semiconductor device 1. In other words, strain stress F 1 to no junction 4a shown in FIG. 1, 4c receives the IC substrate 10 is a horizontal left direction, conversely, the mounting board 20
Strain stress F 2 for receiving respect is a horizontal right direction.
【００３８】このように、不具合をもたらす歪み応力Ｆ
1、Ｆ2の水平方向が、その接合部４の位置から推定され
る場合、ＩＣ突出部１６と基板突出部２２の断面形状を
接合部４の位置に依存して変えることにより、水平方向
の歪み応力Ｆ1、Ｆ2を効率よく緩和することができる。
図４で示すように、例えば、接合部４ａの内部に突出す
る基板突出部２２は、左側だけにほぼ垂直な壁を含む三
角断面形状を有するように形成される。また、接合部４
ａの内部に突出するＩＣ突出部１６は、これとは反対
に、右側だけにほぼ垂直な壁を含む三角断面形状を有す
るように形成される。こうして、より少量のＩＣ突出部
１６および基板突出部２２を用いて、水平方向の歪み応
力Ｆ1、Ｆ2を効率よく緩和することができる。付言する
と、図１で示す接合部４ｅないし４ｇがＩＣ基板１０に
対して受ける歪み応力Ｆ1は、水平右側方向となる。As described above, the strain stress F which causes a defect is obtained.
When the horizontal direction of 1 and F 2 is estimated from the position of the joint 4, the cross-sectional shape of the IC protrusion 16 and the substrate protrusion 22 is changed depending on the position of the joint 4, whereby The strain stresses F 1 and F 2 can be efficiently reduced.
As shown in FIG. 4, for example, the substrate protruding portion 22 protruding into the joint portion 4a is formed to have a triangular cross-sectional shape including a substantially vertical wall only on the left side. Also, the joint 4
On the contrary, the IC protruding portion 16 protruding into the inside a is formed so as to have a triangular cross-sectional shape including a substantially vertical wall only on the right side. In this manner, the horizontal strain stresses F 1 and F 2 can be efficiently reduced by using a smaller amount of the IC protrusion 16 and the substrate protrusion 22. When an additional note, the strain stress F 1 to no junction 4e shown in Figure 1, 4g receives the IC substrate 10 is a horizontal right direction.
【００３９】実施の形態４．図５を参照して、実施の形
態４による半導体装置１について説明する。実施の形態
４の半導体装置１は、実施の形態１の半導体装置１のＩ
Ｃ突出部１６と基板突出部２２を、特に、接合部４の弾
性係数（剛性率）またはそれより高い弾性係数（剛性
率）を有する半田材を用いて形成したものであるので、
詳細な説明を省略する。接合部４以上の弾性係数（剛性
率）を有する材料の一例として、接合部４を構成する半
田材よりも融点の高い半田材が挙げられる。Embodiment 4 Fourth Embodiment A semiconductor device 1 according to a fourth embodiment will be described with reference to FIG. The semiconductor device 1 of the fourth embodiment is the same as the semiconductor device 1 of the first embodiment.
Since the C protruding portion 16 and the substrate protruding portion 22 are formed by using a solder material having an elastic modulus (rigidity) of the joint 4 or a higher elastic modulus (rigidity) than that,
Detailed description is omitted. An example of a material having an elastic coefficient (rigidity) equal to or higher than that of the joint 4 is a solder material having a higher melting point than the solder material forming the joint 4.
【００４０】図５で示すＩＣ突出部１６と基板突出部２
２は、例えば、スクリーン印刷法などを用いて、弾性係
数（剛性率または融点）の高い半田材を、ＩＣパッド１
７および基板パッド２１上に貼付することにより、形成
される。こうして、実施の形態１と同様に信頼性の高い
半導体装置１を、安価に大量生産できる。The IC protrusion 16 and the substrate protrusion 2 shown in FIG.
2, a solder material having a high modulus of elasticity (rigidity or melting point) is applied to the IC pad 1 using a screen printing method or the like.
7 and the substrate pad 21. Thus, the semiconductor device 1 having high reliability as in the first embodiment can be mass-produced at low cost.
【００４１】さらに、その他の適当な方法を用いて、こ
の高い弾性係数（剛性率）または高い融点を有する半田
材を、実施の形態１ないし３で説明した半導体装置のＩ
Ｃ突出部１６と基板突出部２２のような形状に成型する
ことにより、実施の形態４による半導体装置１よりも信
頼性の高い半導体装置１を実現することができる。Further, by using another appropriate method, the solder material having the high elastic modulus (rigidity) or the high melting point is applied to the semiconductor device described in the first to third embodiments.
By molding into a shape like the C protruding portion 16 and the substrate protruding portion 22, a semiconductor device 1 having higher reliability than the semiconductor device 1 according to the fourth embodiment can be realized.
【００４２】実施の形態５．図６を参照して、実施の形
態５による半導体装置１について説明する。実施の形態
５の半導体装置１は、ＩＣパッド１７および基板パッド
２１自身が接合部４に突出した形状を有し、ＩＣ突出部
１６および基板突出部２２を省略する点以外は、実施の
形態１の半導体装置１と同様に構成されているので、詳
細な説明を省略する。つまり、ＩＣパッド１７およびＩ
Ｃ突出部１６と、基板パッド２１および基板突出部２２
を一体成形して、両者の接合強度を最大化する。Embodiment 5 FIG. The semiconductor device 1 according to the fifth embodiment will be described with reference to FIG. The semiconductor device 1 according to the fifth embodiment has the same configuration as that of the first embodiment except that the IC pad 17 and the substrate pad 21 have a shape protruding from the bonding portion 4 and the IC projection 16 and the substrate projection 22 are omitted. Since the configuration is the same as that of the semiconductor device 1, the detailed description is omitted. That is, the IC pads 17 and I
C projection 16, substrate pad 21 and substrate projection 22
To maximize the joint strength between the two.
【００４３】このように、ＩＣ突出部１６および基板突
出部２２を別途形成する必要がないので、工程を簡略化
することができる。さらに、ＩＣパッド１７および基板
パッド２１が、ＩＣ突出部１６および基板突出部２２の
機能を果たし、しかも一体成型されているので、より信
頼性の高い半導体装置１を実現することができる。As described above, since it is not necessary to separately form the IC protruding portion 16 and the substrate protruding portion 22, the process can be simplified. Further, since the IC pad 17 and the substrate pad 21 function as the IC protrusion 16 and the substrate protrusion 22 and are integrally formed, the semiconductor device 1 with higher reliability can be realized.
【００４４】このときのＩＣパッド１７および基板パッ
ド２１の形状は、実施の形態１ないし３で説明したよう
な任意の形状に成形することができる。At this time, the shapes of the IC pad 17 and the substrate pad 21 can be formed into any shapes as described in the first to third embodiments.
【００４５】実施の形態６．図７を参照して、実施の形
態６による半導体装置１について説明する。実施の形態
６の半導体装置１は、ＩＣパッド１７および基板パッド
２１によりＩＣ突出部１６および基板突出部２２を一体
成形する代わりに、ＩＣパッドおよび基板パッド２１の
接合部４と対向する表面が、凹凸または鋸状段差を有す
るように形成した点以外は、従来式の半導体装置１０１
と同様に構成されているので、詳細な説明を省略する。
このような凹凸は、めっき法、およびエッチング法など
広く知られた方法を用いて形成することができる。Embodiment 6 FIG. Sixth Embodiment A semiconductor device 1 according to a sixth embodiment will be described with reference to FIG. In the semiconductor device 1 according to the sixth embodiment, instead of forming the IC protruding portion 16 and the substrate protruding portion 22 integrally with the IC pad 17 and the substrate pad 21, A conventional semiconductor device 101 except that it is formed to have irregularities or sawtooth steps.
Since the configuration is the same as that described above, detailed description is omitted.
Such unevenness can be formed using a widely known method such as a plating method and an etching method.
【００４６】この実施の形態６のＩＣパッド１７および
基板パッド２１は、実施の形態１と同様に、接合部４に
負荷される水平方向の歪み応力Ｆ1、Ｆ2を低減すること
ができる。しかも、これらＩＣパッド１７および基板パ
ッド２１を少量の材料（例えば、金など）で形成するこ
とができるので、安価に信頼性の高い半導体装置を製造
することができる。The IC pad 17 and the substrate pad 21 according to the sixth embodiment can reduce horizontal strain stresses F 1 and F 2 applied to the joint 4, as in the first embodiment. Moreover, since the IC pad 17 and the substrate pad 21 can be formed of a small amount of material (for example, gold), a highly reliable semiconductor device can be manufactured at low cost.
【００４７】[0047]
【発明の効果】請求項１に記載の本発明によれば、第１
および第２の突出部が、接合部およびＩＣ電極部と、接
合部および基板電極部の間の接合界面における両者の接
合強度を補強し、これらの接合界面で断線しにくい、信
頼性の高い半導体装置を提供することができる。According to the first aspect of the present invention, the first
And the second protruding portion reinforces the bonding strength between the bonding portion and the IC electrode portion, and the bonding interface between the bonding portion and the substrate electrode portion, and makes it difficult for the semiconductor device to be disconnected at the bonding interface. An apparatus can be provided.
【００４８】請求項２および３に記載の本発明によれ
ば、第１および第２の突出部は、接合部以上に硬いの
で、接合部およびＩＣ電極部と、接合部および基板電極
部の間の接合界面における両者の接合強度をより十分に
補強し、これらの接合界面でより断線しにくい、より信
頼性の高い半導体装置を提供することができる。According to the second and third aspects of the present invention, since the first and second protrusions are harder than the joint, the gap between the joint and the IC electrode and between the joint and the substrate electrode is increased. It is possible to provide a more reliable semiconductor device in which the bonding strength between the two at the bonding interface is more sufficiently reinforced, and disconnection is more difficult at the bonding interface.
【００４９】請求項４に記載の本発明によれば、第１お
よび第２の突出部を、安価に大量生産するとともに、信
頼性の高い半導体装置を提供することができる。According to the present invention, the first and second projections can be mass-produced at low cost and provide a highly reliable semiconductor device.
【００５０】請求項５ないし７に記載の本発明によれ
ば、水平方向の歪み応力に耐える、信頼性の高い半導体
装置を提供することができる。According to the present invention, it is possible to provide a highly reliable semiconductor device which can withstand horizontal strain stress.
【００５１】請求項８および９に記載の本発明によれ
ば、垂直方向の湾曲歪み応力に耐える、信頼性の高い半
導体装置を提供することができる。According to the eighth and ninth aspects of the present invention, it is possible to provide a highly reliable semiconductor device that withstands a bending stress in a vertical direction.
【００５２】請求項１０に記載の本発明によれば、ＩＣ
突出部１６および基板突出部２２を別途形成する必要が
ないので、工程を簡略化することができ、さらに、第１
の突出部およびＩＣ電極部と、第２の突出部および基板
電極部の間の接合界面は、突出部および電極部を各々別
途形成する場合に比較して、両者の接合強度を最大化す
ることができるので、より信頼性の高い半導体装置を提
供することができる。According to the tenth aspect of the present invention, an IC
Since it is not necessary to separately form the protruding portion 16 and the substrate protruding portion 22, the process can be simplified, and the first
The bonding interface between the second protrusion and the substrate electrode portion, and the bonding interface between the second protrusion and the substrate electrode portion should maximize the bonding strength between the two in comparison with the case where the protrusion and the electrode portion are separately formed. Therefore, a more reliable semiconductor device can be provided.
【００５３】請求項１１に記載の本発明によれば、ＩＣ
電極部と接合部の接合強度を向上させ、信頼性の高い半
導体装置を提供することができる。According to the eleventh aspect of the present invention, an IC
The bonding strength between the electrode portion and the bonding portion can be improved, and a highly reliable semiconductor device can be provided.
【００５４】請求項１２に記載の本発明によれば、基板
電極部と接合部の接合強度を向上させ、信頼性の高い半
導体装置を提供することができる。According to the twelfth aspect of the present invention, the bonding strength between the substrate electrode portion and the bonding portion can be improved, and a highly reliable semiconductor device can be provided.
【図面の簡単な説明】[Brief description of the drawings]
【図１】 図１は、本発明に係る実施の形態１の半導体
装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device according to a first preferred embodiment of the present invention.
【図２】 図２は、図１で示した最も左側（周縁）部に
配置された接合部の一部を拡大した断面図である。FIG. 2 is an enlarged cross-sectional view of a part of a bonding portion arranged at a leftmost (peripheral) portion shown in FIG.
【図３】 図３は、本発明に係る実施の形態２の半導体
装置の図２と同様の一部拡大断面図である。FIG. 3 is a partially enlarged cross-sectional view similar to FIG. 2 of a semiconductor device according to a second embodiment of the present invention;
【図４】 図４は、本発明に係る実施の形態３の半導体
装置の図２と同様の一部拡大断面図である。FIG. 4 is a partially enlarged cross-sectional view similar to FIG. 2 of a semiconductor device according to a third embodiment of the present invention.
【図５】 図５は、本発明に係る実施の形態４の半導体
装置の図２と同様の一部拡大断面図である。FIG. 5 is a partially enlarged sectional view similar to FIG. 2 of a semiconductor device according to a fourth embodiment of the present invention.
【図６】 図６は、本発明に係る実施の形態５の半導体
装置の図２と同様の一部拡大断面図である。FIG. 6 is a partially enlarged sectional view similar to FIG. 2 of a semiconductor device according to a fifth embodiment of the present invention.
【図７】 図７は、本発明に係る実施の形態６の半導体
装置の図２と同様の一部拡大断面図である。FIG. 7 is a partially enlarged sectional view similar to FIG. 2 of a semiconductor device according to a sixth embodiment of the present invention.
【図８】 図８は、従来式の半導体装置の断面図であ
る。FIG. 8 is a sectional view of a conventional semiconductor device.
【図９】 図９は、図８で示した最も左側（周縁）部に
配置された接合部の一部を拡大した断面図であって、水
平方向の歪み応力と垂直方向の湾曲応力を示す。FIG. 9 is an enlarged cross-sectional view of a part of a bonding portion arranged at the leftmost (peripheral) portion shown in FIG. 8, and shows a horizontal strain stress and a vertical bending stress. .
【図１０】 図１０は、基板−接合界面付近に亀裂が生
じた様子を示す図９と同様の一部拡大断面図である。FIG. 10 is a partially enlarged cross-sectional view similar to FIG. 9, showing a state in which a crack has occurred near a substrate-bonding interface.
【図１１】 図１１は、反復的な温度変化により、基板
−接合界面に亀裂が生じて断線した様子を示す図９と同
様の一部拡大断面図である。FIG. 11 is a partially enlarged cross-sectional view similar to FIG. 9, showing a state in which a crack is generated at a substrate-bonding interface due to a repetitive temperature change and the wire is broken.
１ 半導体装置、２ 半導体ＩＣチップ部、３ 実装回
路部、４ 接合部、１０ＩＣチップ、１１ ダイボンド
樹脂、１３ 金線、１４ ＩＣパッド、１５インタポー
ザ、１６ ＩＣ突出部、１７ ＩＣ−接合界面、２０
実装基板、２１ 基板パッド、２２ 基板突出部、２３
基板−接合界面。REFERENCE SIGNS LIST 1 semiconductor device, 2 semiconductor IC chip section, 3 mounting circuit section, 4 bonding section, 10 IC chip, 11 die bond resin, 13 gold wire, 14 IC pad, 15 interposer, 16 IC protrusion, 17 IC-bonding interface, 20
Mounting board, 21 board pad, 22 board protrusion, 23
Substrate-joining interface.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 谷 周一 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 Ｆターム(参考） 5F044 KK17 LL01 LL04 QQ02 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Tani 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F044 KK17 LL01 LL04 QQ02
Claims (12)
れた半導体ＩＣチップ部と、複数の基板電極部が一方の
表面に形成された実装基板部と、ＩＣ電極部と対応する
基板電極部を接合する複数の接合部とを備えた半導体装
置において、 ＩＣ電極部が、該ＩＣ電極部に固定され、接合部内部に
突出する第１の突出部を有し、 基板電極部が、該基板電極部に固定され、接合部内部に
突出する第２の突出部を有することを特徴とする半導体
装置。1. A semiconductor IC chip portion having a plurality of IC electrode portions formed on one surface, a mounting board portion having a plurality of substrate electrode portions formed on one surface, and a substrate electrode corresponding to the IC electrode portion. A semiconductor device comprising a plurality of joints for joining the parts, wherein the IC electrode part has a first protrusion fixed to the IC electrode part and projecting inside the joint part; A semiconductor device having a second protrusion fixed to a substrate electrode portion and projecting into a joint portion.
の弾性係数を有することを特徴とすることを特徴とする
半導体装置。2. The semiconductor device according to claim 1, wherein the first and second protrusions have an elastic coefficient higher than that of the joint.
の融点を有することを特徴とする請求項１の半導体装
置。3. The semiconductor device according to claim 1, wherein the first and second protrusions have a melting point equal to or higher than the junction.
る請求項１の半導体装置。4. The semiconductor device according to claim 1, wherein the joint is made of a solder material.
と垂直な断面を有し、 半導体ＩＣチップ部と実装基板部の熱膨張係数が異な
り、 第１および第２の突出部が、周囲温度変化に伴って接合
部に負荷される水平方向の歪み応力を緩和するような垂
直断面形状を有することを特徴とする請求項１の半導体
装置。5. A semiconductor IC chip portion having a cross section perpendicular to a surface of a mounting substrate portion, wherein the semiconductor IC chip portion and the mounting substrate portion have different thermal expansion coefficients, and the first and second protrusions have an ambient temperature. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a vertical cross-sectional shape so as to relieve a horizontal strain stress applied to the joint portion with the change.
が、矩形であることを特徴とする請求項５の半導体装
置。6. The semiconductor device according to claim 5, wherein the vertical cross-sectional shape of the first and second protrusions is rectangular.
が、周囲温度変化に伴って接合部に負荷される水平方向
の歪み応力を緩和するような実質的に垂直な辺を含む三
角形であることを特徴とする請求項５の半導体装置。7. A triangle wherein the vertical cross-sectional shape of the first and second protrusions includes substantially vertical sides to relieve horizontal strain stresses applied to the joint due to changes in ambient temperature. 6. The semiconductor device according to claim 5, wherein
と垂直な断面を有し、 半導体ＩＣチップ部と実装基板部の熱膨張係数が異な
り、 第１および第２の突出部が、周囲温度変化に伴って接合
部に負荷される垂直方向の湾曲応力を緩和するような垂
直断面形状を有することを特徴とする請求項１の半導体
装置。8. A semiconductor IC chip and a mounting substrate having a cross section perpendicular to a surface of the mounting substrate, wherein the semiconductor IC chip and the mounting substrate have different coefficients of thermal expansion, and the first and second projections have an ambient temperature. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a vertical cross-sectional shape so as to relieve a vertical bending stress applied to the joint portion with the change.
あり、 第２の突出部の垂直断面形状が、逆台形であることを特
徴とする請求項８の半導体装置。9. The semiconductor device according to claim 8, wherein the vertical cross section of the first protrusion is a trapezoid, and the vertical cross section of the second protrusion is an inverted trapezoid.
部および基板電極部と一体成形されたことを特徴とする
請求項１ないし９のいずれかの半導体装置。10. The semiconductor device according to claim 1, wherein the first and second projecting portions are formed integrally with the IC electrode portion and the substrate electrode portion.
された半導体ＩＣチップ部と、複数の基板電極部が一方
の表面に形成された実装基板部と、ＩＣ電極部と対応す
る基板電極部を接合する複数の接合部とを備えた半導体
装置において、 半導体ＩＣチップ部と実装基板部の表面と垂直な断面を
有し、 ＩＣ電極部と接合部の接合界面における垂直断面形状
が、複数の凹凸状または鋸状であることを特徴とする半
導体装置。11. A semiconductor IC chip portion having a plurality of IC electrode portions formed on one surface, a mounting substrate portion having a plurality of board electrode portions formed on one surface, and a substrate electrode corresponding to the IC electrode portion. A semiconductor device having a plurality of joints for joining the parts, the semiconductor device having a cross section perpendicular to the surface of the semiconductor IC chip part and the surface of the mounting substrate part, and having a plurality of vertical cross-sectional shapes at the joint interface between the IC electrode part and the joint part A semiconductor device characterized by having an uneven shape or a saw-like shape.
された半導体ＩＣチップ部と、複数の基板電極部が一方
の表面に形成された実装基板部と、ＩＣ電極部と対応す
る基板電極部を接合する複数の接合部とを備えた半導体
装置において、 半導体ＩＣチップ部と実装基板部の表面と垂直な断面を
有し、 基板電極部と接合部の接合界面における垂直断面形状
が、複数の凹凸状または鋸状であることを特徴とする半
導体装置。12. A semiconductor IC chip portion having a plurality of IC electrode portions formed on one surface, a mounting board portion having a plurality of substrate electrode portions formed on one surface, and a substrate electrode corresponding to the IC electrode portion. A semiconductor device having a plurality of joints for joining the parts, the semiconductor device having a cross section perpendicular to the surface of the semiconductor IC chip part and the surface of the mounting substrate part, and having a plurality of vertical cross-sectional shapes at the joint interface between the substrate electrode part and the joint part. A semiconductor device characterized by having an uneven shape or a saw-like shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000167737A JP2001351946A (en) | 2000-06-05 | 2000-06-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000167737A JP2001351946A (en) | 2000-06-05 | 2000-06-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001351946A true JP2001351946A (en) | 2001-12-21 |
Family
ID=18670856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000167737A Pending JP2001351946A (en) | 2000-06-05 | 2000-06-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001351946A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
| WO2004051748A1 (en) * | 2002-11-27 | 2004-06-17 | Freescale Semiconductor, Inc. | Solder bond pad with a convex shape |
| JP2005101614A (en) * | 2003-09-23 | 2005-04-14 | Samsung Electronics Co Ltd | Reinforced solder bump and method of forming reinforced solder bump structure |
| US7446399B1 (en) | 2004-08-04 | 2008-11-04 | Altera Corporation | Pad structures to improve board-level reliability of solder-on-pad BGA structures |
| JP2009099637A (en) * | 2007-10-15 | 2009-05-07 | Fujitsu Ltd | Circuit board, semiconductor device, and manufacturing method of semiconductor device |
| JP2011181953A (en) * | 2011-05-16 | 2011-09-15 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| WO2014155455A1 (en) * | 2013-03-26 | 2014-10-02 | 日本特殊陶業株式会社 | Wiring board |
| JP2015115363A (en) * | 2013-12-09 | 2015-06-22 | 富士通株式会社 | Electronic device and method of manufacturing electronic device |
| JP2018107302A (en) * | 2016-12-27 | 2018-07-05 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
-
2000
- 2000-06-05 JP JP2000167737A patent/JP2001351946A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
| US6929978B2 (en) | 1999-03-05 | 2005-08-16 | Altera Corporation | Method of fabricating an integrated circuit package utilizing a conductive structure for improving the bond strength between an IC package and a printed circuit board |
| WO2004051748A1 (en) * | 2002-11-27 | 2004-06-17 | Freescale Semiconductor, Inc. | Solder bond pad with a convex shape |
| JP2005101614A (en) * | 2003-09-23 | 2005-04-14 | Samsung Electronics Co Ltd | Reinforced solder bump and method of forming reinforced solder bump structure |
| US7446399B1 (en) | 2004-08-04 | 2008-11-04 | Altera Corporation | Pad structures to improve board-level reliability of solder-on-pad BGA structures |
| JP2009099637A (en) * | 2007-10-15 | 2009-05-07 | Fujitsu Ltd | Circuit board, semiconductor device, and manufacturing method of semiconductor device |
| JP2011181953A (en) * | 2011-05-16 | 2011-09-15 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| WO2014155455A1 (en) * | 2013-03-26 | 2014-10-02 | 日本特殊陶業株式会社 | Wiring board |
| JP2015115363A (en) * | 2013-12-09 | 2015-06-22 | 富士通株式会社 | Electronic device and method of manufacturing electronic device |
| US9761552B2 (en) | 2013-12-09 | 2017-09-12 | Fujitsu Limited | Electronic apparatus and method for fabricating the same |
| US9812418B2 (en) | 2013-12-09 | 2017-11-07 | Fujitsu Limited | Electronic apparatus and method for fabricating the same |
| JP2018107302A (en) * | 2016-12-27 | 2018-07-05 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
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