JPH08236575A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH08236575A JPH08236575A JP7033343A JP3334395A JPH08236575A JP H08236575 A JPH08236575 A JP H08236575A JP 7033343 A JP7033343 A JP 7033343A JP 3334395 A JP3334395 A JP 3334395A JP H08236575 A JPH08236575 A JP H08236575A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- electrode
- solder
- pin
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.
【０００２】[0002]
【従来の技術】現在、２００ピンクラスの半導体素子の
搭載されるパッケージでは、生産コストの安価なＱＦＰ
(Quad Flat Package）が主流である。しかし、ＱＦＰで
２００ピン以上を考えた場合、リードピンが細くなり変
形しやすくなるため、配線基板への表面実装時に接続不
良が発生しやすくなる。そのため、ＱＦＰに変わって、
多ピン化に対応できる新パッケージ構造として、ＢＧＡ
（Ball Grid Array)パッケージが検討されている。図２
に、ＢＧＡパッケージの断面構造を示す。ＢＧＡパッケ
ージでは、リードピンに変えてハンダボールを用い、ま
た、ハンダボールは基板下面に取り付けられるため、ボ
ールピッチが広くなり、表面実装時の不良発生率が低減
できる。このような、ＱＦＰとＢＧＡパッケージの比較
については、例えば、日経ＢＰ社，１９９４年２月１４
日発行，日経エレクトロニクスＰ60〜６７に記載されて
いる。2. Description of the Related Art At present, in a package in which a semiconductor element of 200-pin class is mounted, a QFP which has a low production cost is produced.
(Quad Flat Package) is the mainstream. However, when the number of pins of the QFP is 200 or more, the lead pins become thin and easily deformed, so that a connection failure is likely to occur during surface mounting on the wiring board. Therefore, instead of QFP,
BGA as a new package structure that can support multiple pins
(Ball Grid Array) package is under consideration. Figure 2
The cross-sectional structure of the BGA package is shown in FIG. In the BGA package, solder balls are used instead of the lead pins, and the solder balls are attached to the lower surface of the substrate, so that the ball pitch is widened and the defect occurrence rate during surface mounting can be reduced. For such a comparison between the QFP and BGA packages, see, for example, Nikkei BP, February 14, 1994.
Nikkei Electronics P60-67, published by Nikkei Electronics.
【０００３】[0003]
【発明が解決しようとする課題】ＢＧＡパッケージで
は、図７（ａ),（ｂ）のように、半導体チップの電極と
絶縁基板の電極間との接続にワイヤボンディングを用い
る方式（ＷＢ）と、はんだバンプを用いるフェイスダウ
ン接続方式（ＦＤ）が知られている。（ａ）のＷＢ方式
は、量産性に優れている。しかし、ワイヤボンディング
の領域が広く、パッケージサイズが大きくなってしまう
欠点を持つ。一方、（ｂ）のＦＤ方式では、同一サイズ
のチップを搭載したときに、ＷＢ方式のＢＧＡパッケー
ジ構造に比べてパッケージサイズを小さくできる。しか
しながら、ＦＤ方式では、はんだバンプと半導体チップ
との熱膨張差が大きい。そのため、半導体装置を繰り返
し動作させた時、発生する熱によりバンプもしくバンプ
と半導体チップの電極界面にクラックが発生し易くなり
信頼性が低下するといった問題が生じる。In the BGA package, as shown in FIGS. 7A and 7B, a method (WB) using wire bonding for connection between electrodes of a semiconductor chip and electrodes of an insulating substrate, A face-down connection method (FD) using solder bumps is known. The WB method of (a) is excellent in mass productivity. However, it has a drawback that the wire bonding area is wide and the package size is large. On the other hand, in the FD method of (b), when the chips of the same size are mounted, the package size can be made smaller than that of the WB method BGA package structure. However, in the FD method, the difference in thermal expansion between the solder bump and the semiconductor chip is large. Therefore, when the semiconductor device is repeatedly operated, the heat generated causes cracks to easily occur at the bumps or at the electrode interfaces between the bumps and the semiconductor chip, resulting in a decrease in reliability.
【０００４】このような熱膨張差に起因する問題に対し
熱応力を緩和する方法には、接続部品としてはんだ材も
しくはろう材とピンを用いる方法が知られており、例え
ば、特開昭61−125062号や特開平6−188289 号が上げら
れる。但し、樹脂を用いて接続部品を封止する場合、封
止材がピンの変形を抑え、ピンの熱応力緩和効果が少な
くなるため、特定の接合界面での熱応力の集中を防ぐ必
要がある。また、基板上や半導体素子の隣接電極間が微
細ピッチになると、スクリーン印刷法を用いて電極上に
はんだを搭載する方法では、隣接電極間でブリッジが発
生しやすくなるため不適当である。従って、はんだを搭
載する方法としてめっき法やボールによるバンプ形成法
が考えられる。しかし、この場合に搭載されたはんだは
硬いため、球状ではピンとの接続の位置合わせがしにく
くなる。そのため、はんだを搭載する形状として、ピン
との位置合わせのしやすい形状を考える必要がある。As a method for relieving thermal stress against the problem caused by such a difference in thermal expansion, there is known a method of using a solder material or a brazing material and a pin as a connecting component, for example, Japanese Patent Laid-Open No. 61- 125062 and JP-A-6-188289 are listed. However, when the connection parts are sealed with resin, the sealing material suppresses the deformation of the pins and the effect of relaxing the thermal stress of the pins is reduced, so it is necessary to prevent the concentration of thermal stress at a specific bonding interface. . Further, when a fine pitch is formed on the substrate or between the adjacent electrodes of the semiconductor element, a method of mounting solder on the electrodes using a screen printing method is not suitable because a bridge is likely to occur between the adjacent electrodes. Therefore, as a method for mounting the solder, a plating method or a bump forming method using balls can be considered. However, since the solder mounted in this case is hard, it is difficult to align the connection with the pin if the solder is spherical. Therefore, it is necessary to consider a shape that facilitates alignment with the pin as a shape for mounting the solder.
【０００５】本発明では、ＢＧＡタイプのパッケージに
おいて、電極間接合部の熱的信頼性を上げるために特定
の界面への熱応力の集中を防ぎつつ、そのような半導体
装置を製造する際のピンとはんだの位置合わせをしやす
くすることを目的とする。According to the present invention, in a BGA type package, the concentration of thermal stress at a specific interface is prevented in order to improve the thermal reliability of the inter-electrode junction, and pins for manufacturing such a semiconductor device are used. The purpose is to facilitate solder alignment.
【０００６】[0006]
【課題を解決するための手段】本発明の目的は、半導体
チップの下面に形成された電極にピンを取り付け、ピン
の他端と絶縁基板の主面の電極をめっき法で形成された
リング状のはんだを用いて接続することにより達成され
る。SUMMARY OF THE INVENTION An object of the present invention is to attach a pin to an electrode formed on the lower surface of a semiconductor chip and to form a ring shape in which the other end of the pin and an electrode on the main surface of an insulating substrate are formed by plating. It is achieved by connecting with the solder of.
【０００７】[0007]
【作用】半導体チップの電極と絶縁基板の電極との電気
的な接続部品としてピンとはんだを用い、半導体チップ
の電極とピンを直接接続し、絶縁基板の電極とピンの接
続部にのみはんだで補強させる半導体装置の構造とする
ことにより、半導体チップと基板のあいだ発生する左右
方向の熱応力をピンが解消するため、バンプと基板側電
極の接合部にクラックが発生しにくくなる。特に、絶縁
基板より熱膨張率の低い半導体チップ側にはんだより熱
膨張率の低いピンを接続し、熱膨張率の高い絶縁基板側
にはんだを接続したことで、熱膨張率の近い材料が接合
界面で接することになる。従って、封止材によってピン
が変形しにくい状態であっても、特定の接合界面での熱
応力の集中を防ぐため、各層に対し熱応力の分散を図れ
る。また、封止材としてピン材の熱膨張率と実質的に等
しい熱膨張率を持つ材料を用いることで、ピンと封止材
が上下方向にほぼ同程度膨張するため、ピンとはんだ層
の接合部の亀裂を防止できる。[Function] Pins and solder are used as electrical connecting parts between the electrodes of the semiconductor chip and the electrodes of the insulating substrate, the electrodes of the semiconductor chip are directly connected to each other, and only the connecting portions of the electrodes and pins of the insulating substrate are reinforced with solder. With the structure of the semiconductor device, the pin eliminates the lateral thermal stress generated between the semiconductor chip and the substrate, and thus cracks are less likely to occur at the joint between the bump and the substrate-side electrode. In particular, by connecting pins with a lower coefficient of thermal expansion than solder to the semiconductor chip that has a lower coefficient of thermal expansion than the insulating substrate and connecting solder to the side of the insulating substrate that has a higher coefficient of thermal expansion, materials with a similar coefficient of thermal expansion are joined. They will come into contact at the interface. Therefore, even if the pins are not easily deformed by the sealing material, thermal stress is prevented from concentrating at a specific bonding interface, and thermal stress can be dispersed to each layer. Further, by using a material having a coefficient of thermal expansion substantially equal to that of the pin material as the encapsulating material, the pin and the encapsulating material expand in substantially the same amount in the vertical direction, so that the joint portion of the pin and the solder layer Can prevent cracks.
【０００８】また、上記の構造を持つ半導体装置で、ピ
ンと絶縁基板の電極を接続するはんだの固相の溶融温度
Ｔｍ，絶縁基板のガラス転移温度Ｔｇの間にＴｇ＞Ｔｍ
を充たすはんだをピンと絶縁基板の電極を接続するはん
だとして選択することにより、はんだでピンと絶縁基板
の電極を接続する際に、そのリフロー温度をＴｇ以下と
することが可能になるため、絶縁基板を軟化させずに接
続が行える。更に、絶縁基板の下面に取り付けられたは
んだボールの固相の溶融温度をＴｍ′としたとき、Ｔｍ
＞Ｔｍ′の条件を充たすはんだをはんだボールに選択す
ることにより、配線基板への表面実装時温度をＴｍ以下
で設定できるため、表面実装時にピンと絶縁基板の電極
を接続するはんだの再溶融を防ぎ、電極間の短絡を防止
できる。また、半導体チップの電極と絶縁基板の主面の
電極を接続するピンの成分として、主成分をＰｔまたは
Ｎｉとすることより、ピンと絶縁基板の電極を接続する
際にはんだにピンが溶解することを防止できる。In the semiconductor device having the above structure, Tg> Tm between the melting temperature Tm of the solid phase of the solder connecting the pin and the electrode of the insulating substrate and the glass transition temperature Tg of the insulating substrate.
By selecting the solder that fills the pin as the solder that connects the pin and the electrode of the insulating substrate, when the pin and the electrode of the insulating substrate are connected by solder, the reflow temperature can be set to Tg or less. Can be connected without softening. Furthermore, when the melting temperature of the solid phase of the solder balls attached to the lower surface of the insulating substrate is Tm ', Tm
By selecting a solder ball satisfying the condition of> Tm 'as the solder ball, the temperature at the time of surface mounting on the wiring board can be set at Tm or less, preventing remelting of the solder that connects the pin to the electrode of the insulating board during surface mounting. A short circuit between the electrodes can be prevented. Further, by using Pt or Ni as a main component as a component of the pin that connects the electrode of the semiconductor chip and the electrode of the main surface of the insulating substrate, the pin can be dissolved in solder when connecting the pin and the electrode of the insulating substrate. Can be prevented.
【０００９】通常、半導体チップに形成される電極のピ
ッチは１３０μｍ以下であり、電極サイズは１００μｍ
角以下である。そのため、半導体チップの電極と絶縁基
板の主面の電極を接続するピンとして１５μｍ以下の太
さのワイヤを用いることで、ピン先端にボールを作り熱
・超音波を併用してボールを電極と直接接合するボール
ボンディング方法を、半導体チップの電極とピンとの接
続方法として用いることができる。従って、本発明で示
された半導体装置を作製するために用いる装置として、
通常の超音波ボールボンディング装置を利用できる。Usually, the pitch of electrodes formed on a semiconductor chip is 130 μm or less, and the electrode size is 100 μm.
Below the corner. Therefore, by using a wire with a thickness of 15 μm or less as a pin for connecting the electrode of the semiconductor chip and the electrode on the main surface of the insulating substrate, a ball is made at the tip of the pin and the ball is directly contacted with the electrode by using heat and ultrasonic waves. A ball bonding method of joining can be used as a method of connecting electrodes and pins of a semiconductor chip. Therefore, as a device used for manufacturing the semiconductor device shown in the present invention,
Conventional ultrasonic ball bonding equipment can be used.
【００１０】更に、ピン径１５μｍ以下、ピンの長さを
０.２mm 以上の範囲内とすることにより、半導体チップ
とピンに発生した熱応力をピンの変形により緩和でき
る。但し、直径１５μｍ程度の金属細線を１mm（１００
０μｍ）以上もの長さで取り扱うと、曲がりなどの問題
が生じて取扱性が悪くなり、組立て時の短絡による不良
発生も多くなる。Further, by setting the pin diameter to 15 μm or less and the pin length to 0.2 mm or more, the thermal stress generated in the semiconductor chip and the pin can be relaxed by the deformation of the pin. However, a thin metal wire with a diameter of about 15 μm is 1 mm (100 mm
When handled with a length of 0 μm) or more, problems such as bending occur, the handleability deteriorates, and defects often occur due to a short circuit during assembly.
【００１１】また、めっき法やボールボンディングによ
るはんだバンプ形成法を用いて電極上にはんだ層を形成
することにより、１３０μｍ以下の狭ピッチ化された電
極ピッチに対応できる。この場合、印刷法により形成さ
れたはんだペースト層と異なり、めっき法で形成された
はんだ層は粘性が無いため、はんだ層が塊状であるとピ
ンの挿入が不可能となる。そこで、絶縁基板の電極上に
形成するはんだ層の形状を、ピンの直径より大きな円を
空孔に持つリング状とすることにより、はんだ層中心部
へのピンの挿入が可能となる。Further, by forming a solder layer on the electrodes by using a plating method or a solder bump forming method by ball bonding, it is possible to cope with a narrow electrode pitch of 130 μm or less. In this case, unlike the solder paste layer formed by the printing method, the solder layer formed by the plating method has no viscosity, so that if the solder layer is lumpy, it becomes impossible to insert the pins. Therefore, by making the shape of the solder layer formed on the electrode of the insulating substrate into a ring shape having a circle with a hole larger than the diameter of the pin in the hole, the pin can be inserted into the center of the solder layer.
【００１２】また、接合部の強度を確保するために、リ
ング状に形成したはんだの厚さをリングの直径の１／３
以上とすることで、ピンとはんだ層との間に接触面積を
確保できる。また、２／３以下の範囲内とすることで、
はんだを溶融させる際に隣接はんだ層とのブリッジを防
止できる。In order to secure the strength of the joint, the thickness of the ring-shaped solder is 1/3 of the diameter of the ring.
With the above, a contact area can be secured between the pin and the solder layer. Also, by setting it within the range of 2/3 or less,
A bridge with an adjacent solder layer can be prevented when melting the solder.
【００１３】[0013]
【実施例】図１に、本発明の一実施例である半導体装置
の断面構造を示す。この半導体装置は、半導体チップ１
と絶縁基板２と封止材３とはんだボール４、及びピン５
とはんだ層６から構成される。半導体チップ１には電極
７が、絶縁基板２には電極７′が形成されている。半導
体チップ１側の電極７は、ピン５の一方の端に形成され
ているボール８と接続され、ボールを形成していないピ
ン５の他端９がはんだ層６を介して絶縁基板上の電極
７′と接続されることにより、半導体チップ１と絶縁基
板の電極７′と電気的に接続される。FIG. 1 shows a sectional structure of a semiconductor device according to an embodiment of the present invention. This semiconductor device includes a semiconductor chip 1
, Insulating substrate 2, encapsulant 3, solder balls 4, and pins 5
And the solder layer 6. Electrodes 7 are formed on the semiconductor chip 1 and electrodes 7'are formed on the insulating substrate 2. The electrode 7 on the semiconductor chip 1 side is connected to the ball 8 formed at one end of the pin 5, and the other end 9 of the pin 5 not forming the ball is an electrode on the insulating substrate via the solder layer 6. By connecting with 7 ', the semiconductor chip 1 and the electrode 7'of the insulating substrate are electrically connected.
【００１４】以上のような半導体装置の構造であれば、
Ｗ／Ｂ方式のパッケージより、パッケージサイズを小さ
くできる。With the structure of the semiconductor device as described above,
The package size can be made smaller than that of the W / B type package.
【００１５】図２は図１で示された半導体装置における
ピン接続部の拡大図を示す。今、半導体装置を稼動させ
たときの半導体チップ１と絶縁基板２の間に生じる熱歪
について検討してみる。その熱歪をδとしたとき、δ＝
ΔＴ・Δα・Ｗ／２、半導体チップ１の温度と室温との
差ΔＴ＝１５０℃，半導体チップ１と絶縁基板２との熱
膨張差Δα＝１×１０-5／℃，半導体チップ１の長辺の
長さＷ＝３０mmとすれば、δ＝２２.５×１０-3mm、す
なわちδ＝２２.５μｍである。このとき、封止材が無
く、ピンが弾性範囲内で自由に変形できるとした場合、
半導体チップ１と絶縁基板２とを接続するピン５に発生
する剪断力Ｆは、次の式で表される。FIG. 2 is an enlarged view of the pin connection portion in the semiconductor device shown in FIG. Now, the thermal strain generated between the semiconductor chip 1 and the insulating substrate 2 when the semiconductor device is operated will be examined. When the thermal strain is δ, δ =
ΔT · Δα · W / 2, difference between temperature of semiconductor chip 1 and room temperature ΔT = 150 ° C., difference in thermal expansion between semiconductor chip 1 and insulating substrate 2 Δα = 1 × 10 −5 / ° C., length of semiconductor chip 1 If the side length W = 30 mm, then δ = 22.5 × 10 −3 mm, that is, δ = 22.5 μm. At this time, if there is no sealing material and the pin can freely deform within the elastic range,
The shearing force F generated on the pin 5 connecting the semiconductor chip 1 and the insulating substrate 2 is expressed by the following equation.
【００１６】 Ｆ＝１２・Ｅ・Ｉ・δ／ｌ3 但し、Ｉ＝πｄ4／６４ ここで、Ｅ：金属細線（ピン）の弾性係数 ｌ：金属細線（ピン）層の長さ Ｉ：断面２次モーメント ｄ：金属細線（ピン）の直径 ピンとしてＮｉを用いると、Ｅ＝２.０×１０12dyn／cm
2である。また、ピンの直径ｄ＝１５μｍ，長さｌ＝２
００μｍとした場合、Ｆ＝１.７ｇｆとなる。一方、は
んだ層の破断強度Ｆ′は以下の式で表される。[0016] F = 12 · E · I · δ / l 3 where, I = πd 4/64, where, E: elastic modulus of the thin metal wires (pins) l: length of the thin metal wires (pins) layer I: sectional Second moment d: Diameter of thin metal wire (pin) When Ni is used as the pin, E = 2.0 × 10 12 dyn / cm
2 Also, the diameter d of the pin is 15 μm and the length l is 2
When it is set to 00 μm, F = 1.7 gf. On the other hand, the breaking strength F'of the solder layer is expressed by the following formula.
【００１７】Ｆ′＝ｆ・Ｓ ここでＦ：単位面積当たりの引張強度 Ｓ：破断面積 はんだ層６がＰｂーＳｎ合金であるとき、Ｆ′＝１kg／
mm2 以上である。また、電極７′が１００μｍ角であれ
ば、外径ｄ′＝１００μｍ、はんだ層の厚さＨが４０μ
ｍであれば、Ｓ＝π・ｄ′・ｈから求められ、破断強度
Ｆ′＝３.７ｇｆとなり、はんだ層の破断強度がピンの
剪断力より大きくなるため、はんだ層の破断を防げる。
一方、ピンの直径ｄ＝２０μｍとした場合には、Ｆ＝
５.４ｇｆ となり、はんだ層が破断する。F ′ = f · S where F: tensile strength per unit area S: fracture area When the solder layer 6 is a Pb-Sn alloy, F ′ = 1 kg /
mm 2 or more. If the electrode 7'is 100 μm square, the outer diameter d '= 100 μm and the solder layer thickness H is 40 μm.
If m, it is determined from S = π · d ′ · h, and the breaking strength F ′ = 3.7 gf, and the breaking strength of the solder layer is larger than the shearing force of the pin, so that the breaking of the solder layer can be prevented.
On the other hand, when the pin diameter d = 20 μm, F =
It becomes 5.4 gf and the solder layer breaks.
【００１８】実際には、封止材によってピンの変形が多
少抑えられるが、絶縁基板より熱膨張率の低い半導体チ
ップ１側にはんだより熱膨張率の低いピン５を接続し、
熱膨張率の高い絶縁基板側にはんだを接続したことで、
特定の接合界面での熱応力の集中を防ぐことができるた
め、各層に熱応力の分散を図れ、はんだ層へのクラック
発生防止に効果がある。In practice, the pin deformation is somewhat suppressed by the sealing material, but the pin 5 having a lower thermal expansion coefficient than solder is connected to the semiconductor chip 1 side having a lower thermal expansion coefficient than the insulating substrate.
By connecting the solder to the side of the insulating substrate with a high coefficient of thermal expansion,
Since it is possible to prevent the concentration of thermal stress at a specific bonding interface, it is possible to disperse the thermal stress in each layer, and it is effective in preventing the occurrence of cracks in the solder layer.
【００１９】また、封止材３として、ピン５とほぼ同じ
熱膨張率を持つ材料を用いることで、封止材３の上下方
向に対する膨張は、ピン５の膨張と同等以下にできるの
で、ピン５とはんだ層６の亀裂を防止できる。Further, by using a material having substantially the same coefficient of thermal expansion as that of the pin 5 as the sealing material 3, the vertical expansion of the sealing material 3 can be made equal to or less than the expansion of the pin 5, 5 and the solder layer 6 can be prevented from cracking.
【００２０】図３は、本発明の一実施例である半導体装
置の製造方法を示す図である。まず、（ａ）〜（ｂ）
は、超音波ボールボンディング方法を示す図である。
（ａ）ワイヤ１０の先端を放電等により溶融させボール
８をつくる。（ｂ）このボール８を半導体チップ１上の
電極７に対してキャピラリツール１１先端で加圧しなが
らツール１１に超音波振動を印加する。（ｃ）ボール８
と電極７を金属的に直接接合させた後、ツール１１を引
き上げる。すると、ボール１１からワイヤ１０が延びた
状態になるので、ワイヤ１０を一定の長さで切断し、ピ
ン５を形成する。このとき、ワイヤ１０の切断は機械的
に行わなくてもよく、例えば、レーザ光線等により溶融
切断でも構わない。（ｄ）において、（ａ）〜（ｃ）を
繰り返して全ての電極にピン５をつけた後、半導体チッ
プ１を反転させる。一方、主面側の電極７′に予めめっ
き法により作製したはんだ層６を持つ絶縁基板２を用意
し、このはんだ層６とピン５との位置を合わせる。
（ｅ）において、一定の温度に上げることにより、はん
だ層６を溶融させ、ピン５と電極７′を接続する。な
お、一定の温度に上げる方法として、リフローを行なわ
ず、レーザ光線によりはんだ層６をスポット溶融しても
よい。（ｆ）において、絶縁基板２の主面側を封止材３
で封止し、絶縁基板２の裏面側にはんだボール４を接続
する。FIG. 3 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. First, (a)-(b)
FIG. 6 is a diagram showing an ultrasonic ball bonding method.
(A) The tip of the wire 10 is melted by electric discharge or the like to form the ball 8. (B) While the ball 8 is pressed against the electrode 7 on the semiconductor chip 1 by the tip of the capillary tool 11, ultrasonic vibration is applied to the tool 11. (C) Ball 8
After directly bonding the electrode 7 and the electrode 7 metallically, the tool 11 is pulled up. Then, since the wire 10 is extended from the ball 11, the wire 10 is cut into a certain length to form the pin 5. At this time, the wire 10 may not be mechanically cut, and may be melt-cut by a laser beam or the like, for example. In (d), (a) to (c) are repeated to attach the pins 5 to all the electrodes, and then the semiconductor chip 1 is inverted. On the other hand, an insulating substrate 2 having a solder layer 6 prepared in advance on the electrode 7'on the main surface side by a plating method is prepared, and the solder layer 6 and the pin 5 are aligned with each other.
In (e), by raising the temperature to a constant temperature, the solder layer 6 is melted and the pin 5 and the electrode 7'are connected. As a method for raising the temperature to a constant temperature, the solder layer 6 may be spot-melted by a laser beam without performing reflow. In (f), the main surface side of the insulating substrate 2 is sealed with the sealing material 3
Then, the solder balls 4 are connected to the back surface side of the insulating substrate 2.
【００２１】以上の方法を用いると、（ａ）〜（ｂ）の
工程では超音波ボールボンディング装置を用いることが
可能となり、製造装置作製コストが低減できる。By using the above method, the ultrasonic ball bonding apparatus can be used in the steps (a) and (b), and the manufacturing cost of the manufacturing apparatus can be reduced.
【００２２】図４は、本発明の一実施例を示すはんだ層
へのピン挿入図を示す。（ａ）はその断面図、（ｂ）は
上面図を示す。はんだ層６は、絶縁基板２の電極７′上
に、外径ｄ，内径ｄ1 ，厚さＨのリング状のサイズにめ
っき法で形成されている。内径ｄ1 の穴は、マージンを
とってピン径Ｒより少し大きい。そのため、ピン５がは
んだ層６へ挿入しやすくなっている。また、はんだ層６
の厚さＨは、外径ｄの１／３以上としてあるので、切断
したピン長Ｌに対してマージンがとれる構造に成ってい
る。但し、はんだ層６の厚さＨを厚くしていくと、接続
するときに溶解するはんだの量が多くなるため、隣接電
極とはんだブリッジを形成しやすくなる。従って、厚さ
Ｈは外径ｄの２／３以下がよい。なお、ピンがＡｕ等に
めっきを施したほうが、ピンとはんだとのぬれ性を向上
させ、ピンとはんだ層との強度を得るのに有効である。FIG. 4 shows a pin insertion diagram into a solder layer showing an embodiment of the present invention. (A) shows the sectional drawing and (b) shows a top view. The solder layer 6 is formed on the electrode 7 ′ of the insulating substrate 2 by a plating method so as to have a ring-like size having an outer diameter d, an inner diameter d 1 and a thickness H. The hole having the inner diameter d 1 is slightly larger than the pin diameter R with a margin. Therefore, the pin 5 is easily inserted into the solder layer 6. Also, the solder layer 6
Since the thickness H is set to 1/3 or more of the outer diameter d, it has a structure that allows a margin for the cut pin length L. However, as the thickness H of the solder layer 6 is increased, the amount of solder that is melted when connecting is increased, and thus it becomes easier to form a solder bridge with the adjacent electrode. Therefore, the thickness H is preferably 2/3 or less of the outer diameter d. In addition, it is effective that the pins are plated with Au or the like to improve the wettability between the pins and the solder and to obtain the strength between the pins and the solder layer.
【００２３】図５は、ボールボンディングを用いたリン
グ状のはんだ層形成法を示す。FIG. 5 shows a ring-shaped solder layer forming method using ball bonding.
【００２４】（ａ）において、放電電極１２を用いて、
はんだワイヤ１５の先端にはんだボール１６を形成す
る。（ｂ）で、絶縁基板２上の電極７′にはんだボール
１６をボールボンディングする。（ｃ）そして、ワイヤ
をクランプすることにより、ワイヤはボールネック部１
６′で破断する。（ｄ）で、凹み作成用の、先端の細い
ツール１７を用い、先端をボール上部の中心に合わせて
荷重を加え、（ｅ）中心部に凹みをつくる。In (a), using the discharge electrode 12,
A solder ball 16 is formed at the tip of the solder wire 15. At (b), the solder balls 16 are ball-bonded to the electrodes 7'on the insulating substrate 2. (C) Then, by clamping the wire, the wire is attached to the ball neck portion 1
Break at 6 '. In (d), using a tool 17 with a thin tip for making a recess, a load is applied by aligning the tip with the center of the upper part of the ball, and (e) a recess is formed in the center.
【００２５】以上のように、はんだ層をリング状に形成
することにより、ピンがはんだ層へ挿入しやすくなるほ
かに、めっき法を用いずボールボンディング法に用いて
いるので、超音波ボールボンディング装置を併用できる
ため、半導体装置作製のコスト低減に効果が有る。As described above, by forming the solder layer in a ring shape, the pins can be easily inserted into the solder layer, and since it is used in the ball bonding method without using the plating method, the ultrasonic ball bonding apparatus is used. Can be used together, which is effective in reducing the cost of manufacturing a semiconductor device.
【００２６】[0026]
【発明の効果】半導体チップと絶縁基板との熱膨張差に
よって生じる剪断力をピンが解消し、更に、特定の界面
への熱応力の集中を防ぐことができるため、はんだ層と
基板側電極の接合部にクラックが発生しにくくなる。ま
た、そのような半導体装置を製造する際のピンとはんだ
の位置合わせがしやすくなる。The pin eliminates the shearing force generated by the difference in thermal expansion between the semiconductor chip and the insulating substrate, and the concentration of thermal stress on a specific interface can be prevented. Cracks are less likely to occur at the joint. Further, it becomes easy to align the pins and the solder when manufacturing such a semiconductor device.
【図１】半導体装置の断面図。FIG. 1 is a cross-sectional view of a semiconductor device.
【図２】ピン接続部の断面図。FIG. 2 is a sectional view of a pin connection portion.
【図３】半導体装置の製造方法を示す説明図。FIG. 3 is an explanatory diagram showing a method of manufacturing a semiconductor device.
【図４】はんだ層へのピンの挿入図。FIG. 4 is an insertion diagram of a pin in a solder layer.
【図５】ボールボンディングを用いたリング状のはんだ
層形成法を示す説明図。FIG. 5 is an explanatory view showing a ring-shaped solder layer forming method using ball bonding.
【図６】ＢＧＡパッケージの断面図。FIG. 6 is a sectional view of a BGA package.
１…半導体チップ、２…絶縁基板、３…封止材、４…は
んだボール、５…ピン、６…はんだ層、７，７′…電
極。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Insulating substrate, 3 ... Sealing material, 4 ... Solder ball, 5 ... Pin, 6 ... Solder layer, 7, 7 '... Electrode.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 高橋 和弥 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuya Takahashi 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory
Claims (5)
下面の両方に電極を持ち内部に配線構造を持つ絶縁基板
と，前記半導体チップと前記絶縁基板の電極同士を電気
的に接続する接続部品と，前記半導体チップと前記絶縁
基板の上面と接続部品を封止する封止材と，前記絶縁基
板の下面の電極に接続されたはんだボールから構成され
るフェイスダウンタイプの半導体装置において、前記半
導体チップの前記電極と前記絶縁基板の前記電極との電
気的な接続部品としてピンとはんだを用い、前記半導体
チップの電極とピンを直接接続し、前記絶縁基板の電極
とピンの接続部にのみはんだで補強させ、ピン材の熱膨
張率と実質的に等しい熱膨張率を持つ封止材を用いたこ
とを特徴とする半導体装置。1. A semiconductor chip having electrodes on the lower surface, an insulating substrate having electrodes on both the upper surface and the lower surface and having a wiring structure inside, and a connection for electrically connecting the electrodes of the semiconductor chip and the insulating substrate. A face-down type semiconductor device comprising a component, a sealing material for sealing the semiconductor chip, the upper surface of the insulating substrate and a connection component, and a solder ball connected to an electrode on the lower surface of the insulating substrate, Pins and solder are used as electrical connection parts between the electrodes of the semiconductor chip and the electrodes of the insulating substrate, the electrodes and pins of the semiconductor chip are directly connected, and only the connecting portions of the electrodes and pins of the insulating substrate are soldered. A semiconductor device characterized by using a sealing material having a coefficient of thermal expansion substantially the same as that of a pin material.
記電極と前記絶縁基板の主面の電極の接続に用いられる
ピンの材質が、ＰｔまたはＮｉ、もしくは、Ｐｔまたは
Ｎｉを主成分としppm オーダーで微量金属が混入された
合金である半導体装置。2. The material of the pin used for connection between the electrode of the semiconductor chip and the electrode on the main surface of the insulating substrate according to claim 1, wherein Pt or Ni is the main component and Pt or Ni is the main component in ppm order. A semiconductor device that is an alloy containing a trace amount of metal.
記電極と前記絶縁基板の主面の電極の接続に用いられる
ピンの太さが１５μｍ以下であり、長さが０.２〜１mm
の範囲内にある半導体装置。3. The pin according to claim 1, which is used for connecting the electrode of the semiconductor chip and the electrode on the main surface of the insulating substrate, has a thickness of 15 μm or less and a length of 0.2 to 1 mm.
Device within the range of.
板の前記電極を接続するはんだの固相の溶融温度Ｔｍ，
絶縁基板のガラス転移温度Ｔｇ，絶縁基板の下面に取り
付けられたはんだボールの固相の溶融温度Ｔｍ′とした
とき、これらの間にＴｇ＞Ｔｍ＞Ｔｍ′の関係が成立す
る半導体装置。4. The melting temperature Tm of the solid phase of the solder connecting the pin and the electrode of the insulating substrate according to claim 1,
A semiconductor device in which the glass transition temperature Tg of the insulating substrate and the melting temperature Tm 'of the solid phase of the solder balls attached to the lower surface of the insulating substrate are Tg>Tm>Tm'.
ップの電極に加圧し、加熱または超音波振動もしくはそ
の両方を与えて前記ボールと前記電極を接続した後、前
記ワイヤを前記ボールから一定の長さを残して切断する
とともに、絶縁基板上の電極にはんだを搭載し、前記電
極に切断したワイヤを位置合わせしてチップを搭載し、
はんだを溶解してワイヤと電極を接続した後、チップと
基板上面を封止材でモールドし、配線基板下面にはんだ
ボールを搭載する半導体装置の製造方法において、前記
絶縁基板の前記電極上に形成するはんだの形状をリング
状とし、更にリング穴の直径が半導体チップの電極と絶
縁基板の主面の電極を接続するワイヤの直径以上であ
り、更にリング状に形成したはんだの厚さが、リングの
直径の１／３以上２／３以下の範囲内にあることを特徴
とする半導体装置の製造方法。5. A ball formed at the tip of a wire is pressed against an electrode of a semiconductor chip, and after heating and / or ultrasonic vibration is applied to connect the ball and the electrode, the wire is fixed from the ball to a certain extent. While cutting leaving the length, solder is mounted on the electrode on the insulating substrate, the cut wire is aligned with the electrode and the chip is mounted,
Formed on the electrodes of the insulating substrate in a method of manufacturing a semiconductor device in which after melting solder to connect wires and electrodes, the chip and the upper surface of the substrate are molded with a sealing material and solder balls are mounted on the lower surface of the wiring substrate. The shape of the solder is ring-shaped, and the diameter of the ring hole is equal to or larger than the diameter of the wire that connects the electrode of the semiconductor chip and the electrode of the main surface of the insulating substrate. The method for manufacturing a semiconductor device is characterized in being in the range of 1/3 or more and 2/3 or less of the diameter of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7033343A JPH08236575A (en) | 1995-02-22 | 1995-02-22 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7033343A JPH08236575A (en) | 1995-02-22 | 1995-02-22 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08236575A true JPH08236575A (en) | 1996-09-13 |
Family
ID=12383928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7033343A Pending JPH08236575A (en) | 1995-02-22 | 1995-02-22 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08236575A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690090B2 (en) | 2001-01-26 | 2004-02-10 | Nec Electronics Corporation | Semiconductor device having reliable coupling with mounting substrate |
| KR100499336B1 (en) * | 1998-07-13 | 2005-09-02 | 삼성전자주식회사 | Flip-chip package device and method of manufacturing the same |
| CN104217969A (en) * | 2014-08-28 | 2014-12-17 | 南通富士通微电子股份有限公司 | Semiconductor device packaging method |
| CN109003909A (en) * | 2017-06-07 | 2018-12-14 | 三菱电机株式会社 | The manufacturing method of semiconductor device |
-
1995
- 1995-02-22 JP JP7033343A patent/JPH08236575A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100499336B1 (en) * | 1998-07-13 | 2005-09-02 | 삼성전자주식회사 | Flip-chip package device and method of manufacturing the same |
| US6690090B2 (en) | 2001-01-26 | 2004-02-10 | Nec Electronics Corporation | Semiconductor device having reliable coupling with mounting substrate |
| CN104217969A (en) * | 2014-08-28 | 2014-12-17 | 南通富士通微电子股份有限公司 | Semiconductor device packaging method |
| CN109003909A (en) * | 2017-06-07 | 2018-12-14 | 三菱电机株式会社 | The manufacturing method of semiconductor device |
| CN109003909B (en) * | 2017-06-07 | 2023-01-06 | 三菱电机株式会社 | Method for manufacturing semiconductor device |
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