JPH10294337A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve the strain due to stress of bumps due to the difference between the thermal expansion coefficients of a semiconductor chip and a circuit wiring board by a method wherein high-melting point solder alloy layers, which are firm to the strain due to stress, are selectively arranged only on the side of the board and the compositions of the alloy layers are changed in a stepwise manner to the side of the chip. SOLUTION: Bump electrodes 3 are respectively constituted of a first solder alloy layer 4 having a first melting point, a third solder alloy layer 5 having a third melting point, which is lower than the first melting point and is higher than a second melting point, and a second solder alloy layer 6 having the second melting point, which are arranged in order from the side of a circuit wiring board 2. Accordingly, as the solder composition alloy layers, which are firm to the strain due to stress, are arranged on the side part, in which the strain due to stress is generated most greatly, of the board 2, the strain due to stress of bumps is relaxed. Moreover, as the melting temperature of the layer 5 is within the ranges of the melting temperatures of the layers 4 and 6, a semiconductor chip 1 can be reliably bonded to the board 2 without needing a flux by heating simultaneously the chip 1 and the board 2 within the ranges of these temperatures to pressure-weld the alloy layers to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a flip-chip mounting structure. The present invention also relates to a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor devices has increased, there has been a demand for higher density semiconductor packaging technology. Typical examples of the high-density mounting technology of this semiconductor device include a wire bonding technology and a TAB technology. As the highest-density mounting technology, flip-chip mounting technology is used. It is often used as a technology for mounting on a computer.

[0003] Flip chip mounting technology is disclosed in US Pat.
Since the disclosure of Japanese Patent No. 401126 and US Pat. No. 3,429,040, the technique has been widely known. FIG. 15 shows an example of the basic structure of a flip-chip mounted semiconductor device. As shown in FIG. 15, in a semiconductor device having a general flip-chip mounting structure, a semiconductor chip 1, a bonding pad 11 provided on the semiconductor chip 1, and a passivation film covering the surface of the semiconductor chip 1 excluding the bonding pad 11. 13, a barrier metal layer 12 provided on the bonding pad 11, and a solder bump electrode 3 protrudingly formed on the barrier metal layer 12.
And a wiring board 2, and a terminal electrode 1 provided on the wiring board 2.
4. A configuration in which a solder resist film 15 formed on the wiring board 2 excluding the terminal electrodes 14 is joined with the solder bump electrodes 3 and the terminal electrodes 14.

In flip-chip mounting technology, when the constituent material of a semiconductor chip is different from the constituent material of a circuit wiring board on which the semiconductor chip is mounted, a displacement caused by a difference in thermal expansion coefficient often occurs in the semiconductor device and the circuit wiring board. Occur. The generated displacement causes stress distortion in a solder bump electrode connecting the semiconductor device and the circuit wiring board. This stress strain destroys the solder bump electrode to be flip-chip mounted, and reduces the reliability life.

For this reason, conventionally, for example, the arrangement of the solder bump electrodes has been changed to reduce the distance from the center point of the semiconductor device to the center point of the solder bump electrodes. Making the coefficient of thermal expansion similar or equal to that of the device;
Japanese Patent Application Laid-Open No. 61-194732 discloses a method of reducing the temperature change of a flip-chip mounted semiconductor device, and filling a gap between a semiconductor device and a circuit wiring board with a resin as disclosed in Japanese Patent Application Laid-Open No. 61-194732. Has been done.

Also, for example, Microelectronics Packagi
As described in the ng Handbook, many proposals have been made to increase the bump height. Further, proposals have also been made to make the material composition of the solder bump electrode suitable for a uniform composition so as to be robust against stress strain. For example, Proceeding of 26th Elec
Tronic Components Conference
, p67, 1976, reports that a Pb-Sn alloy containing 5% Pb is effective for improving reliability. On the other hand, as described in JP-A-61-65442 and JP-A-61-80828, the Sn content in the Sn alloy is 65% to 80%,
Or, it has been reported that it is desirable to reduce the stress to 50%. At present, stress is relaxed by a method according to the actual situation.

[0007] Further, the reliability has been improved by making the structure of the solder bump electrode into a drum shape. As a method of forming a drum-shaped bump, a method of providing a spacer or peeling a semiconductor chip from a circuit wiring board after connection of a solder bump has been proposed.

As a special method, Japanese Patent Application Laid-Open No. 62-11 / 1987
As described in US Pat. No. 7,346, a method has been proposed in which a solder bump composition has a drum shape when a two-layer combination of a high melting point metal layer and a low melting point metal layer is used.

[0009] Further, a high melting point metal layer and a low melting point metal layer
The layer combination is also disclosed, for example, in JP-A-59-218744. FIG. 16 is a schematic diagram showing a semiconductor device having a bump electrode having a two-layer structure of a high melting point metal layer and a low melting point metal layer as another example of a semiconductor device having a flip chip structure. In this semiconductor device, as shown in the figure, a high-melting-point solder 41 is adhered to a barrier metal 12 provided on an electrode pad 11 of an LSI chip 1 by a dipping method, and a terminal electrode 14 provided on a wiring board 2 is provided.
It has the same structure as that of FIG. 15 except that a low-melting metal layer 42 is provided thereon, and these are cured to form solder bumps. Proposals have been made to improve the reliability by maintaining the gap between the substrate and the semiconductor chip at a certain level or more with such a structure.

As described above, there are many proposals for improving the reliability by interposing a high melting point core metal in a solder bump electrode to form a stand-off, for example, Nikkei Electronics, NO. 663, pp81-96, 1
As in June 996, a Pb-Sn alloy containing 5% of Pb or a high melting point metal made of gold or copper is formed on the semiconductor chip side, and 63% of low melting point Pb is contained on the circuit wiring board side. A method of forming a Pb-Sn alloy or a conductive adhesive has been used.

According to these methods, the size of a semiconductor chip mounted and mounted on a circuit wiring board is 10 mm as in the past.
It has relatively small dimensions not exceeding × 10 mm, and
The effect has been exhibited when the wiring board to be mounted has a thermal expansion coefficient, such as a ceramic substrate, which is not much different from that of the semiconductor chip. However, in the case where the dimensions of the semiconductor chip are large and the thermal expansion coefficient of the wiring substrate is significantly different from that of the semiconductor chip, such as a glass epoxy substrate, the reliability is improved even if the above-described flip chip connection structure is used. I was unable to do it.

This is because stress strain in the solder bump electrode, which becomes conspicuous when the semiconductor chip size is large, is concentrated on the resin substrate side having a large thermal expansion coefficient, and the stress strain is sufficiently reduced by the sealing resin. This is because a limit has occurred.

On the other hand, since the solder constituting the solder bump electrode has a high oxidation rate, its surface is usually covered with an oxide film. Generally, the melting point of the solder oxide film is 1000 ° C.
That's it. Therefore, when the solder is melted, an oxide film remains in a solid state on the surface of the solder, hinders the flow of the solder, and makes it difficult to uniformly remelt the solder. For this reason, when reflowing the solder, it has been necessary to remove the oxide film on the surface.

As a method of reflowing the solder bump electrode, for example, a method of applying a liquid flux onto the solder bump electrode and heating the solder bump electrode to reduce and remove the oxide film on the solder surface is generally used. I was

However, in the method using the flux, it is necessary to wash and remove the flux after the reflow of the solder bump electrode, so that the maintenance of the cleaning apparatus and the processing cost of the cleaning liquid have caused an increase in cost. Also,
Not only that, it is technically difficult to completely clean minute gaps with the miniaturization of solder bump electrodes.
This was a problem in reliability.

For this reason, many methods for reflowing solder bump electrodes without using flux have been devised. For example, Japanese Patent Application Laid-Open No. 63-66949 discloses a method of destroying an oxide film on a solder surface by applying ultrasonic waves to an electronic component, Proceeding of
2nd Symposium Microjoinin
g and Assembly Technology
in Electronics pp45-48,1
No. 996 proposes a method of irradiating a laser beam to destroy an oxide film on the surface of a solder bump electrode.

In the method of applying an ultrasonic wave, an ultrasonic vibrator having a large output is required because the ultrasonic wave is applied to the entire part. As a result, there is a problem that the cost is increased and the parts are damaged by the ultrasonic waves. In addition, it is difficult to irradiate only the solder bump electrode with the laser beam in the method of irradiating the laser beam, and the peripheral portion of the solder bump electrode is also heated by the laser. However, there is a problem that a component material having high heat resistance is required. Furthermore, in this case, there is a problem that it is difficult to control the processing conditions because the range of conditions that can be processed is narrow.

Japanese Patent Application Laid-Open No. 57-143838 discloses a method of performing reflow by pressing a metal formed on an electrode pad on a circuit wiring board side without melting a solder bump on a semiconductor chip. ing. FIG.
FIG. 2 is a schematic cross-sectional view showing a semiconductor device described in JP-A-57-143838 as yet another example of a semiconductor device having a flip-chip structure. In this semiconductor device, a metal layer 52 made of copper, nickel, and chromium having sharp edges formed on the electrode pads 14 on the circuit wiring board 2 is pressed without melting the solder bumps 51 on the semiconductor chip 1. Except for this, it has the same structure as that of FIG. However, in this semiconductor device, although connection is achieved by a reflow process after pressure welding, hard metal remains in the solder and bump stress strain concentrates on copper, nickel, chromium, etc., which have a small amount of plastic deformation. The problem that the reliability later is not always sufficient has newly arisen.

[0019]

As described above, in flip-chip mounting in which a bump electrode formed on a semiconductor chip is interconnected with an electrode pad of a circuit wiring board, stress distortion caused by a difference in thermal expansion coefficient is caused. However, there is a problem that the bump electrode is broken. This problem has been remarkably recognized particularly when a circuit wiring board having a small semiconductor chip size and a significantly different coefficient of thermal expansion from the semiconductor chip is used. On the other hand, various improvements have been made, but none of them has been satisfactory.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a first object of the present invention is to provide a semiconductor device in which a semiconductor chip is bonded on a circuit wiring board by flip-chip mounting. An object of the present invention is to provide a semiconductor device having a bump electrode structure with high connection reliability by sufficiently reducing bump stress distortion caused by a difference in thermal expansion coefficient of a substrate.

A second object of the present invention is to provide a semiconductor device having a bump electrode structure with high connection reliability, in which the bump stress distortion caused by the difference in the thermal expansion coefficient between the semiconductor chip and the circuit wiring board is sufficiently reduced. An object of the present invention is to provide a method for manufacturing an apparatus without using a flux containing impurities causing corrosion.

[0022]

The present invention firstly provides a circuit board, a semiconductor chip connecting terminal electrode provided on the circuit board, and a first semiconductor chip connecting terminal electrode provided on the semiconductor chip connecting terminal electrode.
A first solder metal layer having a melting point of
Semiconductor chips spaced apart on the solder metal layer side of the
A bonding pad provided on the semiconductor chip so as to face the first solder metal layer; a second solder metal layer formed on the bonding pad and having a second melting point lower than the first melting point And a third solder metal layer provided to join the first solder metal layer and the second solder metal layer, and having a third melting point lower than the first melting point and higher than the second melting point. And a semiconductor device comprising:

The present invention secondly comprises a step of forming a first solder metal layer having a first melting point on a semiconductor chip connection terminal electrode provided on a circuit board, and a bonding pad provided on the semiconductor chip. Forming a second solder metal layer having a second melting point lower than the first melting point thereon, aligning the first solder metal layer with the second solder metal layer, A method for manufacturing a semiconductor device, characterized in that the bonding is performed at a temperature lower than the melting point and higher than the second melting point.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention comprises a circuit board, a semiconductor chip connecting terminal electrode provided on the circuit board, a high melting point solder metal layer provided on the semiconductor chip connecting terminal electrode, and a circuit. A semiconductor chip provided separately on the first solder metal layer side of the substrate, a bonding pad provided on the semiconductor chip so as to face the first solder metal layer, and a low melting point formed on the bonding pad; The second solder metal layer is joined via a third solder metal layer having an intermediate melting point lower than the melting point of the first solder metal layer and higher than the melting point of the second solder metal layer. .

According to the present invention, the first solder alloy layer having the highest melting point is formed on the circuit wiring board side, and the second solder alloy layer having the lowest melting point is formed on the semiconductor chip side.
In the middle between the solder alloy layer and the second solder alloy layer, the first
And a third solder alloy layer having a third melting point between the melting point of the second solder alloy layer and the melting point of the second solder alloy layer.

According to the present invention, when an organic resin substrate whose coefficient of thermal expansion is larger than that of a semiconductor chip is used for a circuit wiring board for consumer appliances as in recent years, The bump stress strain that increases on the side can be effectively reduced, and the connection reliability can be significantly improved.

This is achieved by selectively disposing a first solder alloy layer having a high melting point, which is strong against stress and strain, only on the circuit wiring board side, and gradually changes the composition on the semiconductor chip side. This is because the bump stress strain is effectively reduced in the bump electrode.

The solder metal material used in the present invention is preferably a lead-containing alloy such as lead tin (Pb-
An Sn) alloy, a lead-indium (Pb-In) alloy, a lead-antimony (Pb-Sb) alloy, or the like can be used.

A particularly preferred solder metal material is Pb-S
n alloy. For example, as the first solder alloy layer, P
It is preferable to use a Pb-Sn alloy containing 50% to 80% by weight of b, and it is preferable to use a Pb-Sn alloy containing 1% to 20% by weight of Pb as the second solder alloy layer. At this time, the melting temperature of the first solder alloy layer is about 327C to 290C, and the melting temperature of the second solder alloy layer is about 240C to 183C.

[0030] The third solder alloy layer is formed by joining the first solder alloy layer and the second solder alloy layer. The first solder alloy layer and the second solder alloy layer are mixed in the third solder alloy layer, and the tin content is preferably larger in the order from the first solder alloy layer to the second solder alloy layer. It has the following solder alloy composition. Therefore, the portion on the circuit wiring board side where the largest stress strain is generated has a configuration in which a solder composition alloy that is strong against the stress strain is arranged, so that the effect of stress relaxation is significantly improved. The temperature of the third solder alloy layer is about 240 ° C. to 290 ° C., which is within the melting temperature range of the first solder alloy layer and the second solder alloy layer. By simultaneously heating the semiconductor chip and the circuit wiring board within this temperature range and pressing the alloys together, reliable bonding can be realized without the need for flux. FIG. 1 shows that Pb-S
The n alloy phase diagram is shown. The above-mentioned temperature range can be easily obtained from the state diagram shown in FIG.

In the semiconductor device of the present invention, the first
It is preferable that the solder alloy layer has an arc shape with respect to the semiconductor chip connection electrode of the circuit wiring board. In addition, since the height of the first alloy layer has a value of less than 50% of the total height of the bumps, the solder of the specific composition is effectively disposed only on the portion where the stress strain is concentrated. Thereby, connection reliability is extremely improved.

Further, according to the method of the present invention, there is provided a method for manufacturing the above-mentioned semiconductor device, wherein a first high melting point solder metal layer is formed on a semiconductor chip connecting terminal electrode provided on a circuit board. Forming a second solder metal layer having a low melting point on a bonding pad provided on the semiconductor chip; aligning the first solder metal layer with the second solder metal layer; Below the melting point of the metal layer, second
And bonding at a temperature equal to or higher than the melting point of the solder metal layer. By this joining, a third solder layer having a melting point lower than the melting point of the first solder metal layer and higher than the melting point of the second solder metal layer is formed between the first and second solder layers.

According to the method of the present invention, the bonding is performed at a temperature lower than the first melting point and higher than the second melting point.
Only the solder alloy layer is in a molten state. By pressing the melted first solder alloy layer against the melted second solder alloy layer, the solder alloy oxide film formed on the surface of the second solder alloy layer can be easily broken. Therefore, by using the method of the present invention, it is possible to connect a semiconductor chip having solder bumps onto a circuit wiring board without requiring flux. Furthermore, unlike the conventional case, there is no need to wash and remove the flux residue remaining in the minute gap, and a reliable connection can be realized.
Highly reliable flip-chip mounting with less environmental load can be performed.

In the method of the present invention, the first solder alloy layer provided on the semiconductor chip connection electrode of the circuit wiring board is preferably formed in a pointed shape, for example, a cone or a quadrangular pyramid. . In the method of the present invention, as described above, since the bonding is performed at a temperature lower than the first melting point and higher than the second melting point, only the second solder alloy layer is in a molten state. When the unmelted first solder alloy layer has a pointed shape, the solder alloy oxide film formed on the surface of the second solder alloy layer by pressing against the melted second solder alloy layer Can be more easily and reliably destroyed.

In the method of the present invention, a reflow process is usually performed after joining. The strength of the bump electrode is improved by the reflow treatment. Thus, the obtained first and second solder metal layers become apparently integrated bump electrodes. The temperature of the reflow treatment is preferably about 10 ° C. higher than that of the first solder metal layer.

As described above, according to the present invention, in particular, it is possible to effectively reduce stress distortion of bump electrodes, which is a problem by flip-chip mounting a semiconductor chip having a large chip size on an organic resin substrate. And connection reliability is improved.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. FIG. 2 is a schematic sectional view illustrating an example of the semiconductor device of the present invention. FIG. 3 is an enlarged view around the bump electrode of FIG. As shown in the figure, the semiconductor device basically includes a circuit wiring board 2 having a connection terminal electrode 14 provided on one surface thereof and a solder resist 15 covering the periphery thereof. A bonding pad 11 provided on the circuit wiring board side surface facing the connection terminal electrode 14, a passivation film covering the periphery thereof, and a barrier metal layer provided on the bonding pad 11 12 have a structure in which they are joined via the bump electrode 3. In the semiconductor device of the present invention, as shown in FIG. 3, the bump electrodes 3 are formed, in order from the circuit wiring board 2 side, with a first solder metal layer 4 having a first melting point, And a second solder metal layer 6 having a second melting point lower than the third melting point.

An example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. First, as shown in FIG. 4, first, a circuit wiring board 2 having a connection terminal electrode 14 and a solder resist 15 covering the periphery thereof is prepared.
The first solder metal layer 32 made of a Pb-Sn alloy containing 80% by weight of Pb and having a pointed shape is formed.

In the first solder metal layer, first, for example, a resist film is formed in a region excluding the connection terminal electrode 14, and the first solder metal is deposited on the connection terminal electrode 13 by an electroplating method. Dissolve and remove the resist used in the above. In particular, when the plating resist film is sufficiently thick, solder pillars can be formed on the substrate electrode. Next, if necessary, a heat treatment is performed on the plated portion to anneal or reflow, and then, in a solution such as phosphoric acid, strong electrolysis is applied to the metal column and the parallel flat plate to perform electrolytic etching. A metal cone 32 having a sharp tip is formed depending on the conditions of electrolytic etching and the height and diameter of the metal column. Further, it is also possible to thinly plate a metal such as gold which is not easily oxidized on the surface of the solder metal. The selection of the conical or quadrangular pyramid shape is determined by the interface at which the solder projection to be formed contacts the circuit wiring board, and there is no particular problem with the shape as long as the uppermost portion has a sharp shape.

The first solder metal layer 32 having a pointed shape is also formed by heating the Pb-Sn alloy to about 370 ° C., melting the solder, and pressing a copper plate thereon. Can be formed in a lump by pulling them upward.

As the circuit wiring board 2, for example, US Pat. No. 4,811,082 or a printed circuit board SLC (Surface) of a system in which an insulating layer and a conductor layer such as copper are built up on a normal laminated glass epoxy board.
(Laminar Circuit) substrate can be used. An opening of, for example, 110 μmφ is provided in the connection terminal electrode, and Cu is exposed.

Next, the bonding pad 11, the passivation film 13 formed of, for example, PSG (phosphorus silica glass) and SiN (silicon nitride) formed therearound, and the Cu / A semiconductor chip 1 having a barrier metal layer 12 made of Ti is prepared, and a second solder metal layer 31 made of a Pb—Sn alloy containing, for example, 1 to 20% by weight of Pb is formed on the semiconductor chip 1.

The solder metal layer is formed, for example, in US Pat.
It can be formed by a known technique such as a vapor deposition method or an electroplating method as disclosed in Japanese Unexamined Patent Publication No. 925, No. 47-24765, or Unexamined Japanese Patent Publication No. H2-222928.

The size of the solder metal layer is, for example, 100 μm
φ diameter, for example, 256
The number of bump electrodes is arranged. The dimensions of the semiconductor chip were, for example, 10 mm × 10 mm. The height of the solder metal layer is, for example, 75 μm ± 5 μm.

Thereafter, the first solder metal layer 32 and the second
The solder metal layer 31 is aligned using, for example, a flip chip bonder that performs alignment using a half mirror. Here, the semiconductor chip 1 is held by a collet 33 having a heating mechanism, and is preheated in a nitrogen atmosphere at 200 ° C. higher than the melting point of the second solder metal layer.

Here, since the composition of the first bump electrode was a eutectic composition, heating was performed at 200 ° C., but if it is less than the melting point of% Pb-Sn containing 50% by weight to 80% by weight of Pb, The heating temperature is not particularly limited. Although the formation of the solder surface coating can be somewhat suppressed by setting the heating atmosphere to nitrogen, it is difficult to completely prevent the formation of an oxide film unless the oxygen concentration in the reflow atmosphere is reduced to zero. Therefore, a known oxide film is formed on the solder surface at this time.

Next, as shown in FIG. 5, the collet 33 holding the semiconductor chip is lowered until the first solder metal layer 32 of the circuit wiring board slightly enters the second solder metal layer 31. FIG. 6 and FIG. 7 are diagrams illustrating a state in which the second solder metal layer enters the first solder metal layer. As shown in FIG. 6, the first solder metal layer 31 and the second solder metal layer 32 are brought into contact with each other, and as shown in FIG. 7, the first solder metal layer 31 is further lowered until it slightly enters. Then, the oxide film formed on the surface of the second solder metal layer 32 is destroyed.

Stage 33 on which circuit wiring board 2 is mounted
Although it is not always necessary to heat when the second solder metal layer is brought into contact with the first solder metal layer, heating to a predetermined temperature or more of the circuit wiring board performed in a later step can be performed in a short time. If it is necessary to carry out, it is also possible to heat in a temperature range equal to or lower than the melting point of the first solder metal layer formed on the circuit wiring board.

Next, as shown in FIG. 8, the collet 33 holding the semiconductor chip 1 is lowered until the second solder metal layer 32 on the circuit wiring board completely enters the first solder metal layer 31 and the Contact.

Thereafter, as shown in FIG. 9, the stage 34 on which the circuit wiring board is mounted is raised to a temperature higher than the melting point of the first solder metal layer 31, for example, 370 ° C. to 390 ° C.
The first solder metal layer 31 is melted.

Until the alloy layer constituting the first bump electrode and the alloy layer constituting the second bump electrode are sufficiently interdiffused to obtain a third metal layer which achieves mechanically sufficient strength.
This holding temperature state is maintained, for example, for about 10 seconds.

By joining as described above, the first solder alloy layer can be formed in an arc shape with respect to the connection electrode 14 on the circuit wiring board 2 as shown in FIG. The reason why the first solder alloy layer is formed into an arc shape is to gradually reduce the stress distortion inside the bump electrode at the joint between the bump electrode and the circuit wiring board where the stress is most concentrated on the bump electrode. With such an arrangement structure, connection reliability is remarkably improved.

In the semiconductor device shown in FIG.
By disposing a third solder alloy layer 5 in which a second solder alloy layer 4 and a second solder alloy layer 6 are mixed in an intermediate portion between the first solder alloy layer 4 and the second solder alloy layer 3, bump stress strain is reduced. And the connection reliability can be remarkably improved.

Further, when the solder metal layer connecting the semiconductor chip and the circuit wiring board is in a molten state, by removing the collet holding the semiconductor chip, a self-alignment effect due to the surface tension of the solder is generated, which is generated during mounting. Some misalignment is corrected, and bonding can be performed at an accurate position.

By performing the steps described above, FIG.
It is possible to realize a semiconductor device in which a semiconductor chip as shown in (1) is mounted on a circuit wiring board. Further, if necessary, a sealing resin 36, which is a known technique, can be sealed in a gap formed between the flip-chip mounted semiconductor device and the circuit wiring board, as shown in FIG. 11, for example.

As the resin to be sealed, for example, an epoxy resin containing a bisphenol-based epoxy, an imidazole effect catalyst, an acid anhydride curing agent and a spherical quartz filler in a weight ratio of 45% by weight can be used.

Also, for example, 100 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.), 54 parts by weight of a phenol resin as a curing agent, 100 parts by weight of fused silica as a filler, and 0.1 parts of benzyldiamine as a catalyst. 5 parts by weight, 3 parts by weight of carbon black as other additives, silane coupling agent 3
It is also possible to use an epoxy resin melt obtained by grinding, mixing and melting parts by weight, and the material is not particularly limited.

Further, this resin can be extended so as to cover the connection metal to the periphery of the gap formed by the semiconductor chip and the circuit wiring board. By extending in this way, the connection reliability of the semiconductor chip is significantly improved.

Connection Reliability Test A connection reliability test was performed on the obtained semiconductor device. This semiconductor device has a size of 10 mm × 10 mm, as described above.
A bump connection electrode is formed on the main surface of a semiconductor chip
It is formed with a diameter of 100 μmφ and mounted on a circuit wiring board. A case where even one connection portion among the 256 pins is open is regarded as a failure, and the relationship between the cumulative failure rate and the temperature cycle is shown in a graph as shown in FIG.
In this test, the number of samples was 1000, and the temperature cycle conditions were (-55 ° C (30 minutes) to 25 ° C (5 minutes)
125 ° C. (30 minutes) to 25 ° C. (5 minutes). In the figure, a graph 121 indicates that 1 to 20% by weight of Pb
In the case of a conventional semiconductor device having a Pb-Sn alloy high-melting point solder layer including the following, a graph 122 is a graph 123 when a sealing resin is provided in a conventional semiconductor device having a high-melting point solder layer formed on a semiconductor chip side. In the case of the semiconductor device according to the present invention, the graph 124 shows the case where the sealing resin is provided in the semiconductor device according to the present invention.

As shown in the graph 121, a Pb-Sn alloy high melting point solder layer containing 1 to 20% by weight of Pb is formed on the semiconductor chip side, and connection is performed in 1500 cycles in the conventional structure using a flux for assembly. A defect occurred, and the defect became 100% in 2000 cycles. Further, as shown in the graph 122, when the sealing resin is arranged in this structure, the connection reliability is improved up to 2500 cycles, but the failure is 50% in 3000 cycles. All of these failures result in connection failure due to breakage of the solder on the circuit wiring board side.

On the other hand, the semiconductor device according to the present invention has the same connection reliability as the conventional resin-sealed structure even when the resin is not sealed, as shown in a graph 123, for example. As shown by 124, when the sealing resin was further disposed, no failure occurred up to 3500 cycles, and it was found that the connection reliability was extremely improved.

The defect in the case of using the present invention is a fatigue failure of the solder itself without resin sealing, and a defect of the sealing resin itself with resin sealing. The failure was not caused by the difference in the thermal expansion coefficient between the substrate and the semiconductor chip. As described above, it was confirmed from the failure analysis that the connection reliability of the semiconductor device of the present invention was extremely improved.

Further, the semiconductor device according to the present invention
The relationship between the cumulative failure rate and the temperature cycle when stored at ℃, 85% RH, and V _DD = 5 V was examined. FIG. 13 shows a graph showing the result. As shown in the graph 131, when connection using a conventional flux was performed, corrosion failure occurred in 1500 cycles, and the failure became 100% in 3000 hours. All of these defects were electrical corrosion of the solder metal layer itself. However, it was found that the structure according to the present invention did not cause any failure until 3000 hours, and the reliability was extremely high.

FIG. 14 is a graph showing the relationship between the height H of the first alloy layer and the connection reliability Nf ₅₀ with respect to the height H of the bump electrode. Here, the reliability was evaluated for the case where the first alloy layer was arc-shaped and the case where the first alloy layer was rectangular, and the results are shown in graphs 141 and 142, respectively. As is evident from the graph, the Nf ₅₀ starts at h / H of 0.05.
It can be seen that is changing rapidly. When h / H <0.05, Nf ₅₀ shows high reliability, but when h / H ≧ 0.05, Nf ₅₀ shows low reliability. This indicates that when the area of the first solder alloy layer in the bump electrode is less than 5%, the bump stress strain can be effectively reduced.

Further, it was also confirmed that when the first alloy layer had an arc shape, the reliability Nf ₅₀ exhibited an extremely high value. From the above evaluation results, it is understood that the semiconductor device according to the present invention is a highly reliable mounting structure having excellent resistance to a heat cycle and a high temperature and high humidity environment. Also, it was confirmed that the method of the present invention is a highly effective method capable of performing a connection equivalent to the conventional method without using a flux.

The present invention is not limited to the above embodiment, but can be variously modified without departing from the gist thereof. For example, the circuit defeat board is not limited to the glass epoxy board, but may be an alumina ceramic board, and the chip size and bump electrode size of the semiconductor chip to be mounted are not limited.

[0067]

According to the semiconductor device of the present invention, a semiconductor device having a bump electrode structure with high connection reliability, which sufficiently reduces bump stress distortion caused by a difference in thermal expansion coefficient between a semiconductor chip and a circuit wiring board. A device is obtained.

Further, when the method of the present invention is used, the bump stress distortion caused by the difference in the thermal expansion coefficient between the semiconductor chip and the circuit wiring board is sufficiently relaxed, and the semiconductor device having the bump electrode structure with high connection reliability is obtained. Can be produced without using a flux containing impurities causing corrosion.

[Brief description of the drawings]

FIG. 1 is a phase diagram of a Pb—Sn alloy

FIG. 2 is a schematic cross-sectional view illustrating an example of a semiconductor device of the present invention.

FIG. 3 is an enlarged view around a bump electrode of FIG. 2;

FIG. 4 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a graph showing a connection reliability test result of the semiconductor device of the present invention.

FIG. 13 is a graph showing a connection reliability test result of the semiconductor device of the present invention after storage at high temperature and high humidity.

FIG. 14 is a graph showing the relationship between the height H of the first alloy layer and the connection reliability Nf ₅₀ with respect to the height H of the bump electrode.

FIG. 15 is a diagram illustrating an example of a basic structure of a conventional flip-chip mounted semiconductor device.

FIG. 16 illustrates another example of a semiconductor device having a flip-chip structure.

FIG. 17 is a diagram illustrating yet another example of a semiconductor device having a flip-chip structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Circuit wiring board 3 ... Bump electrode 4 ... First solder alloy layer 5 ... Third solder alloy layer 6 ... Second solder alloy layer 11 ... Bonding pad 12 ... Barrier metal 13 ... Passivation film 14 ... Connection electrode terminal 15 ... Solder resist 31,41,51 ... Second solder alloy layer 32,42,52 ... First solder alloy layer 33 ... Collet 34 ... Heater 35 ... Solder surface oxide film 36 ... Seal resin 37 ... Solder Surface oxide film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Miyagi 33, Shinisogocho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Production Technology Research Institute (72) Inventor Miki Mori 33, Shinisogocho, Isogo-ku, Yokohama-shi, Kanagawa Address Co., Ltd., Toshiba Production Technology Laboratory

Claims (2)

[Claims] 1. A circuit board, a semiconductor chip connecting terminal electrode provided on the circuit board, a first solder metal layer having a first melting point provided on the semiconductor chip connecting terminal electrode, A semiconductor chip provided separately on the first solder metal layer side, a bonding pad provided on the semiconductor chip so as to face the first solder metal layer,
A second solder metal layer formed on the bonding pad and having a second melting point lower than the first melting point, and provided so as to join the first solder metal layer and the second solder metal layer; Lower than the first melting point and the second melting point;
A third solder metal layer having a third melting point higher than the melting point of the semiconductor device. A step of forming a first solder metal layer having a first melting point on a semiconductor chip connecting terminal electrode provided on the circuit board; and forming the first solder metal layer on a bonding pad provided on the semiconductor chip. Forming a second solder metal layer having a second melting point lower than the melting point, aligning the first solder metal layer with the second solder metal layer, wherein the second solder metal layer is less than the first melting point; A method for manufacturing a semiconductor device, comprising joining at a temperature equal to or higher than a melting point.