JP2000133668A - Semiconductor device and packaging structure - Google Patents

Semiconductor device and packaging structure

Info

Publication number
JP2000133668A
JP2000133668A JP10301301A JP30130198A JP2000133668A JP 2000133668 A JP2000133668 A JP 2000133668A JP 10301301 A JP10301301 A JP 10301301A JP 30130198 A JP30130198 A JP 30130198A JP 2000133668 A JP2000133668 A JP 2000133668A
Authority
JP
Japan
Prior art keywords
semiconductor chip
reinforcing member
terminal body
semiconductor device
reinforcing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10301301A
Other languages
Japanese (ja)
Inventor
Takashi Saito
隆 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10301301A priority Critical patent/JP2000133668A/en
Publication of JP2000133668A publication Critical patent/JP2000133668A/en
Pending legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To effectively prevent junction break of a terminal such as of a bump even when no underfilling agent is provided of repair (part replacement). SOLUTION: The semiconductor device comprises a semiconductor chip 1, terminals 4 which are electrically connected to pads on the semiconductor chip 1, and reinforcements 6 which are formed on the surface where the terminals 4 are provided and whose size in a radial direction from the center of the surface is larger than that in a direction perpendicular to the radial direction (and diameter of the terminal 4). The terminals 4 and the reinforcements 6 can be directly formed on the semiconductor chip 1, or formed on one side (opposite to the side where the semiconductor chip 1 is mounted) of a package substrate 2 like a chip size package.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、端子体を介して実
装基板に接続される半導体装置および半導体チップの実
装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor chip mounting structure connected to a mounting substrate via a terminal body.

【０００２】[0002]

【従来の技術】半導体チップをインターポーザー等の介
在なしに、直接、基板（マザーボード等の実装基板）に
実装する方法は、既に工業的に実施されている。図７
は、この半導体チップの直接的な実装（ベアチップ実
装）構造を示す断面図である。2. Description of the Related Art A method of directly mounting a semiconductor chip on a substrate (mounting substrate such as a motherboard) without an interposer or the like has already been industrially implemented. FIG.
FIG. 4 is a cross-sectional view showing a direct mounting (bare chip mounting) structure of the semiconductor chip.

【０００３】図７に示す実装構造１００では、マザーボ
ード等の実装基板１０２上に、半田バンプ等の端子体１
０４を介して半導体チップ１０６の電極パッド（不図
示）が、実装基板１０２上の配線パターン（不図示）と
電気的に接続されている。半導体チップ１０６と実装基
板１０２との対向間隔に、樹脂等のアンダーフィル剤１
０８が充填されている。アンダーフィル剤１０８は、半
導体チップ１０６と実装基板１０２の熱膨張係数が異な
り、そのため加熱時に半田バンプ１０４を介した半導体
チップ１０６と実装基板１０２との電気的接合が破壊さ
れてしまうという問題を回避するために、熱膨張差によ
る応力が半田バンプ１０４に集中しないように緩衝材の
役割を果たす。In a mounting structure 100 shown in FIG. 7, a terminal 1 such as a solder bump is mounted on a mounting substrate 102 such as a motherboard.
An electrode pad (not shown) of the semiconductor chip 106 is electrically connected to a wiring pattern (not shown) on the mounting substrate 102 via the wiring 04. An underfill agent 1 such as a resin is provided between the opposed space between the semiconductor chip 106 and the mounting substrate 102.
08 are filled. The underfill agent 108 avoids the problem that the thermal expansion coefficients of the semiconductor chip 106 and the mounting substrate 102 are different from each other, so that the electrical connection between the semiconductor chip 106 and the mounting substrate 102 via the solder bumps 104 is broken at the time of heating. In order to prevent the stress due to the difference in thermal expansion from being concentrated on the solder bumps 104, it plays a role of a cushioning material.

【０００４】図８（Ａ）は、従来における半導体チップ
のバンプ形成面を示す平面図である。図８（Ａ）に示す
半導体チップ１０６では、半導体チップ１０６のバンプ
形成面の四隅に、機械的強度確保のためだけにバンプ１
０４より大きな補強バンプ１１２を形成し、これによ
り、熱膨張差による応力によって半導体チップ１０６が
実装基板から剥がれにくくしている。FIG. 8A is a plan view showing a bump forming surface of a conventional semiconductor chip. In the semiconductor chip 106 shown in FIG. 8A, bumps 1 are provided at the four corners of the bump formation surface of the semiconductor chip 106 only for securing mechanical strength.
A reinforcing bump 112 larger than 04 is formed, thereby making it difficult for the semiconductor chip 106 to be peeled off from the mounting substrate due to stress due to a difference in thermal expansion.

【０００５】さらに、例えば特開平７−８６３３０号公
報には、半田バンプ等の接合部の配置パターンを工夫す
ることによって、上記熱膨張差による歪み（応力）を抑
制する技術が開示されている。図９（Ａ），（Ｂ）は、
この公報に開示された電極および接合部の配置パターン
を示す図である。図９（Ａ）では、電極１２２及び接合
部１２４がＩＣ１２０の対角線上に配置され、図９
（Ｂ）では、電極１２２及び接合部１２４がＩＣ１２０
の四隅のほか、各辺に直交する線上に配置されている。Further, for example, Japanese Patent Application Laid-Open No. 7-86330 discloses a technique for suppressing the distortion (stress) due to the difference in thermal expansion by devising an arrangement pattern of bonding portions such as solder bumps. FIGS. 9 (A) and 9 (B)
FIG. 3 is a diagram showing an arrangement pattern of electrodes and joints disclosed in this publication. In FIG. 9A, the electrodes 122 and the joints 124 are arranged on a diagonal line of the IC 120.
In (B), the electrode 122 and the joint 124 are IC 120
In addition to the four corners, they are arranged on a line perpendicular to each side.

【０００６】[0006]

【発明が解決しようとする課題】これら従来の半導体装
置および実装構造では、それぞれ、以下に示す課題が存
在する。The conventional semiconductor device and the mounting structure have the following problems.

【０００７】図７に示すベアチップ実装では、応力緩和
のためのアンダーフィル剤１０８が必要なことから、半
導体チップ１０６を一旦、基板１０２に実装した後は、
リペア（部品交換）ができないという課題がある。この
ため、半導体チップ１０６の交換が必要な場合は、基板
１０２ごとの交換となってしまい、修理コストが高くな
るという不利益がある。[0007] In the bare chip mounting shown in FIG. 7, an underfill agent 108 for relaxing stress is required.
There is a problem that repair (part replacement) cannot be performed. For this reason, when the semiconductor chip 106 needs to be replaced, the replacement is performed for each substrate 102, which has a disadvantage of increasing repair cost.

【０００８】図８（Ａ）に示すベアチップ実装では、半
導体チップ１０６の四隅に補強バンプ１１２を形成する
ことによって周辺部の強度を高めてあるが、図８（Ｂ）
の断面図に示すように、ヒートサイクル時等の基板１０
２の延びにより、中央部でバンプ１０４の接合が破壊さ
れてしまうという課題がある。In the bare chip mounting shown in FIG. 8A, the strength of the peripheral portion is increased by forming reinforcing bumps 112 at the four corners of the semiconductor chip 106, but FIG. 8B
As shown in the cross-sectional view of FIG.
Due to the extension of 2, there is a problem that the joint of the bump 104 is broken at the center.

【０００９】図９（Ａ），（Ｂ）に示す公報記載の接合
部の配置パターンでは、接合部（バンプ）の破壊に対す
る効果が不十分である。つまり、全面にバンプを形成し
ても、例えばヒートサイクル等を繰り返すとバンプ接合
が破壊されるのが実情である。The arrangement pattern of the joints described in the publications shown in FIGS. 9A and 9B has an insufficient effect on the destruction of the joints (bumps). That is, even if bumps are formed on the entire surface, bump bonding is destroyed when, for example, a heat cycle is repeated.

【００１０】本発明の目的は、アンダーフィル剤がなく
てもバンプ等の端子体の接合破壊が有効に防止でき、リ
ペア（部品交換）可能な半導体装置および実装構造を提
供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a mounting structure which can effectively prevent the breakage of terminals such as bumps even without an underfill agent, and which can be repaired (component replacement).

【００１１】[0011]

【課題を解決するための手段】本発明に係る半導体装置
は、半導体チップと、当該半導体チップのパッド部に電
気的に接続して形成された端子体と、当該端子体の形成
面に形成され、その形成面中央を通る放射線上の寸法が
当該放射線と直交する方向の寸法（および端子体の径）
より大きな補強体とを有する。この端子体および補強体
は、半導体チップ面に形成されたものでもよく、また、
いわゆるチップサイズパッケージのパッケージ基板面に
形成されたものでもよい。後者の場合、前記半導体チッ
プと前記端子体および補強体との間に、パッケージ基板
が介在し、前記パッケージ基板の半導体チップ側の面
に、前記端子体と電気的に接続された配線層が形成さ
れ、当該配線層と前記半導体チップのパッド部とが、内
部端子体を介して電気的に接続されている。A semiconductor device according to the present invention comprises a semiconductor chip, a terminal body electrically connected to a pad portion of the semiconductor chip, and a surface formed with the terminal body. , The dimension on the radiation passing through the center of the formation surface in the direction orthogonal to the radiation (and the diameter of the terminal body)
With a larger reinforcement. The terminal body and the reinforcing body may be formed on a semiconductor chip surface,
It may be formed on the package substrate surface of a so-called chip size package. In the latter case, a package substrate is interposed between the semiconductor chip and the terminal body and the reinforcing body, and a wiring layer electrically connected to the terminal body is formed on a surface of the package substrate on the semiconductor chip side. The wiring layer and the pad portion of the semiconductor chip are electrically connected via an internal terminal.

【００１２】本発明では、好適には、前記端子体の形成
面中央に、当該端子体より専有面積が大きな中央補強体
が形成されている。他の好適な構成としては、前記中央
補強体と前記補強体とが一体に形成されている。さらに
他の好適な構成として、前記補強体は、前記形成面中央
を通る対角線上に配置された対角補強体を含む。この場
合、好適に、前記対角補強体は、前記形成面の角部付近
で前記対角線と直交する方向の幅が拡大されている。ま
た、好適に、前記補強体は、その周囲に等間隔で配置さ
れた接続体との距離が接続体同士の距離とほぼ同じとな
る位置に突部を有する。In the present invention, preferably, a central reinforcing member having a larger occupation area than the terminal body is formed at the center of the forming surface of the terminal body. In another preferred configuration, the central reinforcing member and the reinforcing member are integrally formed. As still another preferred configuration, the reinforcing member includes a diagonal reinforcing member disposed on a diagonal line passing through the center of the forming surface. In this case, preferably, the diagonal reinforcing body has a width in the direction orthogonal to the diagonal line increased near a corner of the formation surface. Preferably, the reinforcing member has a protrusion at a position where a distance between the reinforcing members and the connecting members arranged at regular intervals around the reinforcing member is substantially equal to a distance between the connecting members.

【００１３】以上のような構成の補強体（中央補強体を
含む）は、補強用のためだけに設けてもよく、また、端
子体の一種として前記半導体チップの所定のパッド部に
電気的に接続させてもよい。The reinforcing member (including the central reinforcing member) having the above structure may be provided only for reinforcement, and may be electrically connected to a predetermined pad portion of the semiconductor chip as a kind of terminal. It may be connected.

【００１４】本発明に係る第１の実装構造は、半導体チ
ップの実装基板への実装構造であって、当該半導体チッ
プのパッド部に電気的に接続する端子体と、前記パッド
部が形成されているチップ面に、チップ面中央を通る放
射線上の寸法が当該放射線と直交する方向の寸法より大
きな補強体とを介して、前記半導体チップが前記実装基
板上に固定されている。A first mounting structure according to the present invention is a mounting structure for mounting a semiconductor chip on a mounting substrate, wherein a terminal body electrically connected to a pad portion of the semiconductor chip and the pad portion are formed. The semiconductor chip is fixed to the mounting substrate via a reinforcing member having a dimension on a radiation passing through the center of the chip surface larger than a dimension in a direction orthogonal to the radiation.

【００１５】本発明に係る第２の実装構造は、半導体チ
ップを一方の主面に搭載したパッケージ基板の実装基板
への実装構造であって、前記パッケージ基板の他方の主
面に、前記半導体チップのパッド部と電気的に接続され
た端子体が形成され、当該端子体の形成面に、その形成
面中央を通る放射線上の寸法が当該放射線と直交する方
向の寸法より大きな補強体が形成されている。A second mounting structure according to the present invention is a mounting structure of a package substrate having a semiconductor chip mounted on one main surface thereof on a mounting substrate, wherein the semiconductor chip is mounted on the other main surface of the package substrate. A terminal body electrically connected to the pad portion is formed, and a reinforcing member whose dimension on a radiation passing through the center of the forming surface is larger than a dimension in a direction orthogonal to the radiation is formed on a formation surface of the terminal body. ing.

【００１６】以上のような半導体装置および実装構造で
は、補強体の放射線方向の寸法が、放射線と直交する方
向の寸法（および端子体の径）より大きい。通常、熱膨
張差に応じた応力のかかりかたは面中心からの距離に応
じて異なる。ところが、本発明で補強体の放射線方向の
寸法が大きいため、このような応力が有効に補強体にか
かり、端子体の接合部にかからない。したがって、端子
体が半導体チップ（またはパッケージ基板）との界面、
或いは実装基板との界面で剥がれることがない。とくに
中央補強体により、実装基板等が延びて中央部で半導体
チップ（またはパッケージ基板）との距離が大きくな
る、中央部の浮きを有効に防止できる。また、角部によ
り、半導体チップ（またはパッケージ基板）の周辺部の
接合強度を高めることができる。In the semiconductor device and the mounting structure as described above, the dimension in the radiation direction of the reinforcing member is larger than the dimension in the direction perpendicular to the radiation (and the diameter of the terminal body). Normally, the manner of applying stress according to the difference in thermal expansion differs depending on the distance from the center of the plane. However, in the present invention, since the reinforcing member has a large dimension in the radiation direction, such stress is effectively applied to the reinforcing member and does not apply to the joint portion of the terminal body. Therefore, the terminal body is the interface with the semiconductor chip (or package substrate),
Alternatively, it does not peel off at the interface with the mounting substrate. In particular, the central reinforcing member can effectively prevent the central portion from floating, in which the mounting substrate or the like extends to increase the distance between the central portion and the semiconductor chip (or the package substrate). Further, the bonding strength of the peripheral portion of the semiconductor chip (or the package substrate) can be increased by the corner portion.

【００１７】[0017]

【発明の実施の形態】第１実施形態 図１は、第１実施形態に係る実装構造を示す断面図であ
る。図１において、実装基板３上に端子体４および補強
体６を介して、半導体チップ１が電気的接続を確保しな
がら載置されている。より詳しくは、特に図示しないが
実装基板３上に配線層パターンが形成され、また、半導
体チップの表面に電極パッド部が形成され、その電極パ
ッド部と実装基板３上の配線層パターンとが、端子体４
（または補強体６）を介して電気的に接続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a sectional view showing a mounting structure according to a first embodiment. In FIG. 1, a semiconductor chip 1 is placed on a mounting board 3 via a terminal body 4 and a reinforcing body 6 while ensuring electrical connection. More specifically, although not particularly shown, a wiring layer pattern is formed on the mounting substrate 3, and an electrode pad portion is formed on the surface of the semiconductor chip, and the electrode pad portion and the wiring layer pattern on the mounting substrate 3 are Terminal 4
(Or the reinforcing member 6).

【００１８】実装基板３は、例えば、プリント基板等の
有機基板、アルミナまたはムライト等のセラミック基
板、片面にポリイミドテープを施したＳｉ基板等から構
成される。端子体４は、例えば、ハンダ、Ａｕ，Ｃｕ等
からなる半球状または凸状のバンプ、球状体（ボール）
などからなる。ボールの場合、表面が導電層でコートさ
れたプラスチック等であってもよい。補強体６は、電気
的接続用として端子体４と同様に、配線層パターンと電
極パッド部を電気的に接続するものでもよく、また、電
極パッド部との電気的な接続を行わない補強用として用
いてもよい。補強体６は、例えば、ハンダ、Ａｕ，Ｃｕ
等からなる幅方向の断面が半球状のバンプからなる。The mounting substrate 3 is composed of, for example, an organic substrate such as a printed circuit board, a ceramic substrate such as alumina or mullite, a Si substrate having a polyimide tape on one surface. The terminal body 4 is, for example, a hemispherical or convex bump, a spherical body (ball) made of solder, Au, Cu, or the like.
Etc. In the case of a ball, a plastic or the like whose surface is coated with a conductive layer may be used. The reinforcing member 6 may be a member for electrically connecting the wiring layer pattern and the electrode pad portion similarly to the terminal member 4 for electrical connection, or a reinforcing member for not electrically connecting to the electrode pad portion. May be used. The reinforcing member 6 is made of, for example, solder, Au, Cu
The cross section in the width direction made of a hemispherical bump is formed.

【００１９】図２は、第１実施形態に係る半導体装置の
構造を示す断面図である。ここでは、チップサイズパッ
ケージ（ＣＳＰ）と称する半導体装置の構造を示す。こ
のＣＳＰ２０において、パッケージ基板２の一方の面
に、配線２ａが形成され、この配線２ａと電極パッド部
との電気的接続が内部端子体８を介して達成された状態
で、半導体チップ１が固定されている。パッケージ基板
２は、図１の実装基板３と同様な材質を有する。内部端
子体８は、図１の端子体４と同様にバンプまたはボール
等からなる。樹脂等からなるアンダーフィル剤９が、半
導体チップ１とパッケージ基板２との対向間隔に充填さ
れている。FIG. 2 is a sectional view showing the structure of the semiconductor device according to the first embodiment. Here, a structure of a semiconductor device called a chip size package (CSP) is shown. In this CSP 20, the wiring 2a is formed on one surface of the package substrate 2, and the semiconductor chip 1 is fixed in a state where the electrical connection between the wiring 2a and the electrode pad portion is achieved via the internal terminal body 8. Have been. The package substrate 2 has the same material as the mounting substrate 3 of FIG. The internal terminal body 8 is formed of a bump, a ball, or the like, like the terminal body 4 of FIG. An underfill agent 9 made of resin or the like is filled in a space between the semiconductor chip 1 and the package substrate 2 facing each other.

【００２０】パッケージ基板２の他方の面には、端子体
４と補強体６が設けられている。端子体４は、パッケー
ジ基板２の一方面に設けられた前記配線２ａと電気的に
接続されている。図１の場合と同様、補強体６は、機械
的補強を兼ねた電気的接続用として、或いは単に機械的
補強を行うために設けられている。ここでも補強体６
は、例えば、ハンダ、Ａｕ，Ｃｕ等からなる幅方向の断
面が半球状のバンプからなる。On the other surface of the package substrate 2, a terminal body 4 and a reinforcing body 6 are provided. The terminal body 4 is electrically connected to the wiring 2 a provided on one surface of the package substrate 2. As in the case of FIG. 1, the reinforcing member 6 is provided for electrical connection which also serves as mechanical reinforcement, or merely for mechanical reinforcement. Again, reinforcement 6
Is formed of, for example, a bump having a hemispherical cross section in the width direction made of solder, Au, Cu, or the like.

【００２１】図３は、図１または図２における端子体お
よび補強体の形成面から見た平面図である。図３に示す
ように、補強体６が形成面（半導体チップ１の面、また
はパッケージ基板２の面）に、その面中心を通る放射線
上に配置されている。そして、その放射線方向の寸法
が、放射線と直交する方向の寸法より大きい形状を有す
る。本実施形態では、４つの補強体６が、対角線（放射
線の一種）上に配置されている。補強体６の周囲に、端
子体４が、本例では２列に等間隔で配置されている。FIG. 3 is a plan view of the terminal body and the reinforcing body in FIG. 1 or FIG. As shown in FIG. 3, the reinforcing member 6 is arranged on the formation surface (the surface of the semiconductor chip 1 or the surface of the package substrate 2) on the radiation passing through the center of the surface. And the shape in the radiation direction is larger than the dimension in the direction orthogonal to the radiation. In the present embodiment, the four reinforcing members 6 are arranged on a diagonal line (a type of radiation). The terminals 4 are arranged at equal intervals in two rows in this example around the reinforcement 6.

【００２２】本実施形態の実装構造または半導体装置で
は、このように補強体６が、放射線上に配置されて、し
かも放射線方向に長い形状を有することから、半導体チ
ップ１またはパッケージ基板２と実装基板との間の強度
を強くすることができ、両者間に加わる、材料の熱膨張
に起因したストレスが大きくなっても、半導体チップ１
またはパッケージ基板２の端子体４が実装基板から剥が
れにくくなる。また、補強体６が線状であるため、実装
基板側の配線の引回しが容易である。In the mounting structure or the semiconductor device of the present embodiment, since the reinforcing member 6 is arranged on the radiation and has a long shape in the radiation direction, the semiconductor chip 1 or the package substrate 2 and the mounting substrate Can be increased, and even if the stress applied between them due to the thermal expansion of the material increases, the semiconductor chip 1
Alternatively, the terminal body 4 of the package substrate 2 is hardly peeled off from the mounting substrate. Further, since the reinforcing member 6 is linear, it is easy to route the wiring on the mounting substrate side.

【００２３】第２実施形態 図４は、本実施形態に係る実装構造または半導体装置
の、端子体および補強体の形成面を示す平面図である。
本実施形態では、半導体チップ１またはパッケージ基板
２のほぼ中央に、端子体４よりも占有面積が大きな中央
補強体３０が形成されている。中央補強体３０は、補強
体６と同じ材質で構成でき、機械的補強を兼ねた電気的
接続用として、或いは単に機械的補強を行うために設け
られている。 Second Embodiment FIG. 4 is a plan view showing a surface of a mounting structure or a semiconductor device according to the present embodiment on which terminals and reinforcing members are formed.
In the present embodiment, a central reinforcing body 30 occupying a larger area than the terminal body 4 is formed substantially at the center of the semiconductor chip 1 or the package substrate 2. The central reinforcing member 30 can be made of the same material as the reinforcing member 6 and is provided for electrical connection also serving as mechanical reinforcement, or simply for mechanical reinforcement.

【００２４】本実施形態の実装構造または半導体装置で
は、第１実施形態より更に中央補強体３０が追加され、
それだけ半導体チップ１またはパッケージ基板２と実装
基板との間の強度が増して、更に端子剥がれが発生しに
くい。また、実装後にヒートサイクルをかけた場合で
も、中央部で端子剥がれが発生しないことから、高い信
頼性が達成されている。In the mounting structure or the semiconductor device of the present embodiment, a central reinforcing member 30 is further added as compared with the first embodiment.
As a result, the strength between the semiconductor chip 1 or the package substrate 2 and the mounting substrate is increased, and terminal peeling is less likely to occur. In addition, even when a heat cycle is applied after mounting, high reliability is achieved because terminal peeling does not occur at the center.

【００２５】第３実施形態 図５は、本実施形態に係る実装構造または半導体装置
の、端子体および補強体の形成面を示す平面図である。
本実施形態における補強部４０は、半導体チップ１また
はパッケージ基板２のほぼ中央に配置され端子体４より
も占有面積が大きな中央補強体部４０ａと、中央補強体
部４０ａから放射状に延びた放射補強部４０ｂとからな
る。中央補強体部４０ａと放射補強部４０ｂは同じ材料
で一体に形成され、機械的補強を兼ねた電気的接続用と
して、或いは単に機械的補強を行うために設けられてい
る。 Third Embodiment FIG. 5 is a plan view showing a surface of a mounting structure or a semiconductor device according to this embodiment on which a terminal body and a reinforcing body are formed.
The reinforcing portion 40 according to the present embodiment includes a central reinforcing portion 40a which is disposed substantially at the center of the semiconductor chip 1 or the package substrate 2 and occupies a larger area than the terminal body 4, and a radial reinforcing portion extending radially from the central reinforcing portion 40a. And a portion 40b. The central reinforcing member 40a and the radiation reinforcing portion 40b are integrally formed of the same material, and are provided for electrical connection also serving as mechanical reinforcement, or simply for mechanical reinforcement.

【００２６】本実施形態の実装構造または半導体装置で
は、第１，第２実施形態より更に、半導体チップ１また
はパッケージ基板２と実装基板との間の強度が増し、端
子剥がれが発生しにくい。また、実装後にヒートサイク
ルをかけた場合でも、中央部で端子剥がれが発生しない
ことから、高い信頼性が達成されている。In the mounting structure or the semiconductor device according to the present embodiment, the strength between the semiconductor chip 1 or the package substrate 2 and the mounting substrate is further increased as compared with the first and second embodiments, and terminal peeling is less likely to occur. In addition, even when a heat cycle is applied after mounting, high reliability is achieved because terminal peeling does not occur at the center.

【００２７】第４実施形態 図６は、本実施形態に係る実装構造または半導体装置
の、端子体および補強体の形成面を示す平面図である。
本実施形態では、第２実施形態と同様、半導体チップ１
またはパッケージ基板２のほぼ中央に、端子体４よりも
占有面積が大きな中央補強体３０が形成されている。本
実施形態が第２実施形態と異なるのは放射線上に配置さ
れた補強体の形状である。本実施形態における補強体５
０は、放射線上に長く延びた基部５０ａと、基部の一端
側で形成面のコーナーに配置された角部５０ｂと、周囲
の端子体４との距離が端子体同士の距離と等しくなる基
部５０ａの長辺位置に形成された突部部５０ｃとを有す
る。角部５０ｂは、放射線と直交する方向の寸法が、基
板５０ａより大きく形成され、本例ではコーナーに沿っ
た略方形に形成されている。 Fourth Embodiment FIG. 6 is a plan view showing a surface of a mounting structure or a semiconductor device according to this embodiment on which a terminal body and a reinforcing body are formed.
In the present embodiment, as in the second embodiment, the semiconductor chip 1
Alternatively, a central reinforcing body 30 occupying a larger area than the terminal body 4 is formed substantially at the center of the package substrate 2. This embodiment is different from the second embodiment in the shape of the reinforcing member arranged on the radiation. Reinforcing body 5 in the present embodiment
0 is a base 50a extending long on the radiation, a corner 50b arranged at a corner of the forming surface at one end of the base, and a base 50a in which the distance between the peripheral terminal bodies 4 is equal to the distance between the terminal bodies. And a projection 50c formed at a long side position. The corner 50b is formed to have a dimension in a direction orthogonal to the radiation larger than the substrate 50a, and in this example, is formed in a substantially rectangular shape along the corner.

【００２８】本実施形態の実装構造または半導体装置で
は、第２実施形態と同様な効果に加え、更にコーナーの
強度が増して、ここでの端子剥がれが発生しにくい。ま
た、補強体５０は、強度的に効果的な形状を保持したま
ま、周囲の端子体４との距離を一定に保った状態で最も
効果的な位置に配置されていることから、端子体４の径
を例えば１００μｍφ程度にまで小さくでき、多ピン化
に対応可能な配置パターンとなっている。In the mounting structure or the semiconductor device of the present embodiment, in addition to the same effects as those of the second embodiment, the strength of the corner is further increased, and the terminal peeling hardly occurs here. Further, since the reinforcing member 50 is arranged at the most effective position while maintaining a constant distance from the surrounding terminal members 4 while maintaining the shape effective in strength, the terminal members 4 Can be reduced to, for example, about 100 μmφ, and the arrangement pattern is compatible with the increase in the number of pins.

【００２９】[0029]

【発明の効果】本発明に係る半導体装置および実装構造
によれば、アンダーフィル剤がなくてもバンプ等の端子
体の接合破壊が有効に防止でき、リペア（部品交換）可
能な半導体装置および実装構造を提供することができ
る。According to the semiconductor device and the mounting structure according to the present invention, it is possible to effectively prevent junction breakdown of a terminal body such as a bump even without an underfill agent, and to provide a semiconductor device and a mounting capable of repair (component replacement). Structure can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１は、本発明の第１実施形態に係る実装構造
を示す断面図である。FIG. 1 is a sectional view showing a mounting structure according to a first embodiment of the present invention.

【図２】図２は、本発明の第１実施形態に係る半導体装
置の構造を示す断面図である。FIG. 2 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.

【図３】図３は、図１または図２における端子体および
補強体の形成面を示す平面図である。FIG. 3 is a plan view showing a formation surface of a terminal body and a reinforcing body in FIG. 1 or 2;

【図４】図４は、本発明の第２実施形態に係る実装構造
または半導体装置の、端子体および補強体の形成面を示
す平面図である。FIG. 4 is a plan view showing a formation surface of a terminal body and a reinforcing body of a mounting structure or a semiconductor device according to a second embodiment of the present invention.

【図５】図５は、本発明の第３実施形態に係る実装構造
または半導体装置の、端子体および補強体の形成面を示
す平面図である。FIG. 5 is a plan view illustrating a formation surface of a terminal body and a reinforcing body of a mounting structure or a semiconductor device according to a third embodiment of the present invention.

【図６】図６は、本発明の第４実施形態に係る実装構造
または半導体装置の、端子体および補強体の形成面を示
す平面図である。FIG. 6 is a plan view showing a formation surface of a terminal body and a reinforcing body of a mounting structure or a semiconductor device according to a fourth embodiment of the present invention.

【図７】図７は、従来の半導体ベアチップ実装構造を示
す断面図である。FIG. 7 is a sectional view showing a conventional semiconductor bare chip mounting structure.

【図８】図８（Ａ）は、従来における半導体チップのバ
ンプ形成面を示す平面図である。図８（Ｂ）は、従来に
おける半導体チップの実装構造を示す断面図である。FIG. 8A is a plan view showing a bump forming surface of a conventional semiconductor chip. FIG. 8B is a cross-sectional view showing a conventional semiconductor chip mounting structure.

【図９】図９（Ａ），（Ｂ）は、従来の半導体装置に関
し、特許公開公報に開示された電極および接合部の配置
パターンを示す図である。FIGS. 9A and 9B are diagrams showing an arrangement pattern of electrodes and junctions disclosed in a patent publication relating to a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１…半導体チップ、２…パッケージ基板、２ａ…配線、
３…実装基板、４…端子体、６…補強体、８…内部端子
体、９…アンダーフィル剤、１０…実装構造、２０…Ｃ
ＳＰ（半導体装置）、３０…中央補強体、４０…補強
体、４０ａ…中央補強部、４０ｂ…放射補強部、５０…
補強体、５０ａ…基部、５０ｂ…角部、５０ｃ…突部。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Package board, 2a ... Wiring,
3 mounting board, 4 terminal body, 6 reinforcing body, 8 internal terminal body, 9 underfill agent, 10 mounting structure, 20 C
SP (semiconductor device), 30 central reinforcement, 40 reinforcement, 40a central reinforcement, 40b radiation reinforcement, 50
Reinforcement, 50a: base, 50b: corner, 50c: protrusion.

Claims (13)

【特許請求の範囲】[Claims] 【請求項１】半導体チップと、 当該半導体チップのパッド部に電気的に接続して形成さ
れた端子体と、 当該端子体の形成面に形成され、その形成面中央を通る
放射線上の寸法が当該放射線と直交する方向の寸法より
大きな補強体とを有する半導体装置。1. A semiconductor chip, a terminal body electrically connected to a pad portion of the semiconductor chip, and a radiation dimension formed on a formation surface of the terminal body and passing through the center of the formation surface. A semiconductor device having a reinforcing member larger than a dimension in a direction orthogonal to the radiation. 【請求項２】前記補強体の放射線上の寸法は、前記端子
体の径より大きい請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the dimension of the reinforcing member on the radiation is larger than the diameter of the terminal body. 【請求項３】前記半導体チップと前記端子体および補強
体との間に、パッケージ基板が介在し、 前記パッケージ基板の半導体チップ側の面に、前記端子
体と電気的に接続された配線層が形成され、 当該配線層と前記半導体チップのパッド部とが、内部端
子体を介して電気的に接続されている請求項１に記載の
半導体装置。3. A package substrate is interposed between the semiconductor chip and the terminal body and the reinforcing member, and a wiring layer electrically connected to the terminal body is provided on a surface of the package substrate on the semiconductor chip side. 2. The semiconductor device according to claim 1, wherein the wiring layer is formed and the pad portion of the semiconductor chip is electrically connected through an internal terminal body. 3. 【請求項４】前記端子体の形成面中央に、当該端子体よ
り専有面積が大きな中央補強体が形成されている請求項
１に記載の半導体装置。4. The semiconductor device according to claim 1, wherein a central reinforcing member having a larger occupation area than the terminal body is formed at the center of the formation surface of the terminal body. 【請求項５】前記中央補強体と前記補強体とが一体に形
成されている請求項４に記載の半導体装置。5. The semiconductor device according to claim 4, wherein said central reinforcing member and said reinforcing member are integrally formed. 【請求項６】前記補強体は、前記形成面中央を通る対角
線上に配置された対角補強体を含む請求項１に記載の半
導体装置。6. The semiconductor device according to claim 1, wherein said reinforcing member includes a diagonal reinforcing member disposed on a diagonal line passing through the center of said forming surface. 【請求項７】前記対角補強体は、前記形成面の角部付近
で前記対角線と直交する方向の幅が拡大されている請求
項６に記載の半導体装置。7. The semiconductor device according to claim 6, wherein said diagonal reinforcing body has a width in a direction orthogonal to said diagonal line increased near a corner of said forming surface. 【請求項８】前記補強体は、その周囲に等間隔で配置さ
れた接続体との距離が接続体同士の距離とほぼ同じとな
る位置に突部を有する請求項１に記載の半導体装置。8. The semiconductor device according to claim 1, wherein the reinforcing member has a protrusion at a position where a distance between the reinforcing members and the connecting members arranged at equal intervals is substantially equal to a distance between the connecting members. 【請求項９】前記補強体は、端子体の一種として前記半
導体チップの所定のパッド部に電気的に接続されている
請求項１に記載の半導体装置。9. The semiconductor device according to claim 1, wherein said reinforcing member is electrically connected to a predetermined pad portion of said semiconductor chip as a kind of terminal member. 【請求項１０】半導体チップの実装基板への実装構造で
あって、 当該半導体チップのパッド部に電気的に接続する端子体
と、 前記パッド部が形成されているチップ面に、当該チップ
面中央を通る放射線上の寸法が当該放射線と直交する方
向の寸法より大きな補強体とを介して、前記半導体チッ
プが前記実装基板上に固定されている実装構造。10. A mounting structure for mounting a semiconductor chip on a mounting board, comprising: a terminal body electrically connected to a pad portion of the semiconductor chip; and a chip surface on which the pad portion is formed; A mounting structure in which the semiconductor chip is fixed on the mounting substrate via a reinforcing member having a dimension on a ray passing through the reinforcing member larger than a dimension in a direction orthogonal to the ray. 【請求項１１】前記補強体は、端子体の一種として前記
半導体チップの所定のパッド部に電気的に接続されてい
る請求項１０に記載の実装構造。11. The mounting structure according to claim 10, wherein said reinforcing body is electrically connected to a predetermined pad portion of said semiconductor chip as a kind of terminal body. 【請求項１２】半導体チップを一方の主面に搭載したパ
ッケージ基板の実装基板への実装構造であって、 前記パッケージ基板の他方の主面に、前記半導体チップ
のパッド部と電気的に接続された端子体が形成され、 当該端子体の形成面に、その形成面中央を通る放射線上
の寸法が当該放射線と直交する方向の寸法より大きな補
強体が形成されている実装構造。12. A mounting structure of a package substrate having a semiconductor chip mounted on one main surface thereof on a mounting substrate, wherein the package substrate is electrically connected to a pad portion of the semiconductor chip on the other main surface of the package substrate. A mounting structure in which a terminal body is formed, and a reinforcing body whose dimension on a radiation passing through the center of the forming surface is larger than a dimension in a direction orthogonal to the radiation is formed on a formation surface of the terminal body. 【請求項１３】前記補強体は、端子体の一種として前記
半導体チップの所定のパッド部に電気的に接続されてい
る請求項１２に記載の実装構造。13. The mounting structure according to claim 12, wherein said reinforcing member is electrically connected to a predetermined pad portion of said semiconductor chip as a kind of terminal.
JP10301301A 1998-10-22 1998-10-22 Semiconductor device and packaging structure Pending JP2000133668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
JP10301301A JP2000133668A (en) 1998-10-22 1998-10-22 Semiconductor device and packaging structure

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Publication Number Publication Date
JP2000133668A true JP2000133668A (en) 2000-05-12

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002080273A2 (en) * 2001-03-30 2002-10-10 Intel Corporation Alternate bump metallurgy bars for power and ground routing
JP2002359342A (en) * 2001-05-31 2002-12-13 Dainippon Printing Co Ltd Middle board for multichip module
JP2003008186A (en) * 2001-06-21 2003-01-10 Sony Corp Semiconductor device
US7126227B2 (en) 2003-01-16 2006-10-24 Seiko Epson Corporation Wiring substrate, semiconductor device, semiconductor module, electronic equipment, method for designing wiring substrate, method for manufacturing semiconductor device, and method for manufacturing semiconductor module
JP2007194305A (en) * 2006-01-18 2007-08-02 Renesas Technology Corp Semiconductor device
WO2009099145A1 (en) * 2008-02-08 2009-08-13 Hitachi Chemical Company, Ltd. Semiconductor chip and packaging method of semiconductor chip
FR2994304A1 (en) * 2012-08-02 2014-02-07 St Microelectronics Tours Sas SURFACE MOUNTING CHIP
JP2019518335A (en) * 2017-01-05 2019-06-27 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． Highly reliable electronic package structure, circuit board and device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002080273A2 (en) * 2001-03-30 2002-10-10 Intel Corporation Alternate bump metallurgy bars for power and ground routing
WO2002080273A3 (en) * 2001-03-30 2003-07-03 Intel Corp Alternate bump metallurgy bars for power and ground routing
CN100440504C (en) * 2001-03-30 2008-12-03 英特尔公司 Alternate bump metallurgy bars for power and ground routing
JP2002359342A (en) * 2001-05-31 2002-12-13 Dainippon Printing Co Ltd Middle board for multichip module
JP2003008186A (en) * 2001-06-21 2003-01-10 Sony Corp Semiconductor device
US7126227B2 (en) 2003-01-16 2006-10-24 Seiko Epson Corporation Wiring substrate, semiconductor device, semiconductor module, electronic equipment, method for designing wiring substrate, method for manufacturing semiconductor device, and method for manufacturing semiconductor module
JP2007194305A (en) * 2006-01-18 2007-08-02 Renesas Technology Corp Semiconductor device
WO2009099145A1 (en) * 2008-02-08 2009-08-13 Hitachi Chemical Company, Ltd. Semiconductor chip and packaging method of semiconductor chip
FR2994304A1 (en) * 2012-08-02 2014-02-07 St Microelectronics Tours Sas SURFACE MOUNTING CHIP
JP2019518335A (en) * 2017-01-05 2019-06-27 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． Highly reliable electronic package structure, circuit board and device
US11011477B2 (en) 2017-01-05 2021-05-18 Huawei Technologies Co., Ltd. High-reliability electronic packaging structure, circuit board, and device

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