JP2001044307A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability in airtightness and prevent breakage of wires in a chip support board. SOLUTION: A semiconductor device comprises a package board 2 for supporting a semiconductor chip 5, a measure-shaped cap member 6 for sealing the chip 5 while being jointed to the board 2, a sealing solder 7 for jointing the board 2 to the member 6, a cap-side metallized layer 6a provided on a joint surface 6b of the member 6 for jointing with the solder 7, and a board-side metallized layer 2a provided around the peripheral edge of the board 2 for jointing with the solder 7. The layer 6a has a width larger than that of the layer 2a, and a board-side joint surface 7b of the solder 7 for jointing with the layer 2a is arranged at a location, corresponding to the inner region of the surface 6b of the member 6 in the board 2, whereby the formation of cracks in the board 2 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique which is effective when applied to improvement of hermetic reliability in hermetically sealed semiconductor devices.

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

An LSI (Large Scale Integration) chip, that is, a semiconductor device in which a semiconductor chip is bump-connected to a chip supporting substrate is often hermetically sealed, and among them, an example of an hermetically sealed semiconductor device is shown. BGA for hermetically sealing semiconductor chips using cap members
(Ball Grid Array) is known.

In this BGA, a chip supporting substrate (also referred to as a package substrate or a BGA substrate) for supporting a semiconductor chip is formed of ceramic such as mullite, and a cap member is formed of ceramic or metal such as aluminum nitride (AlN). Is formed,
Both are fixed by solder.

A semiconductor device hermetically sealed by a cap member is described in, for example, Nikkei BP,
Published on May 31, 993, "Practical Course VLSI Packaging Technology (2)", Susumu Kayama and Kunihiko Naruse (supervised), 178
Page.

[0006]

However, in the hermetically sealed BGA using the cap member of the above-described technique, the shrinkage stress caused by the sealing solder during the solidification of the solder in the solder reflow step when the cap member is fixed. Occurs.

That is, when the solder is solidified, the sealing solder shrinks, whereby shrinkage stress is applied to the chip supporting substrate and the cap member.

In this case, cracks are formed in the chip supporting substrate made of ceramics having relatively low strength due to the shrinkage stress of the sealing solder, and as a result, the problem that the hermetic reliability is impaired occurs.

Further, if a shrinkage stress is applied to the chip supporting substrate, there is a problem that the chip supporting substrate may be disconnected if the chip supporting substrate has a wiring layer therein.

An object of the present invention is to provide a semiconductor device for improving the airtight reliability and preventing a disconnection failure of a chip supporting substrate and a method for manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor device according to the present invention includes a chip supporting substrate for supporting a semiconductor chip, a cap member joined to the chip supporting substrate to seal the semiconductor chip, the chip supporting substrate and the cap member. And a cap-side joining surface of the sealing solder is formed to have a width equal to or wider than the substrate-side joining surface, and the substrate-side joining surface is provided with the chip support. It is arranged at a position on the substrate corresponding to an inner region of the joining surface of the cap member.

Thus, when the cap member and the chip supporting substrate are solder-fixed by the solder for sealing, the shrinkage stress of the sealing solder can be applied to the cap member having higher strength than the chip supporting substrate. .

Accordingly, since the shrinkage stress of the sealing solder applied to the chip supporting substrate can be reduced, it is possible to prevent cracks from being formed in the chip supporting substrate. As a result, the hermetic reliability of the hermetically sealed semiconductor device is reduced. Can be improved.

Further, a method of manufacturing a semiconductor device according to the present invention
Mounting the semiconductor chip on the chip supporting substrate, and forming the cap-side bonding surface of the sealing solder as a bonding member to have a width equal to or wider than the substrate-side bonding surface, The substrate-side bonding surface of the semiconductor device is disposed at a position corresponding to an inner region of the bonding surface of the cap member on the chip supporting substrate, and the chip supporting substrate and the cap member are bonded by the sealing solder. The method includes a step of sealing the chip with the cap member and a step of providing a plurality of external terminals on the chip supporting substrate.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a sectional view showing an example of the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a partially enlarged sectional view showing a structure of a joint portion of a sealing solder in the semiconductor device shown in FIG. FIG. 3 is an external perspective view showing the structure of the semiconductor device of FIG.

The semiconductor device of the present embodiment is of a hermetically sealed type in which a semiconductor chip 5 on which a semiconductor integrated circuit is formed is sealed by a square cap member 6, and as an example, a ball-shaped external terminal is provided. BGA (Ball Grid Arra) using a plurality of bump electrodes 8 (protruding terminals) as terminals
y (ball grid array) 1 will be described.

The BGA 1 shown in FIG. 1 is a package called a chip carrier.

The structure of the BGA 1 according to the present embodiment will be described with reference to FIGS. 1, 2 and 3. A package substrate 2 which is a chip supporting substrate for supporting a semiconductor chip 5 will be described.
A box-shaped cap member 6 joining the package substrate 2 to seal the semiconductor chip 5, a sealing solder 7 joining the package substrate 2 and the cap member 6, and a back surface 5b of the semiconductor chip 5 (semiconductor integrated circuit). A heat transfer solder 9 for joining the cap member 6 with the surface opposite to the main surface on which the circuit is formed, and a solder 7 provided on the cap member 6 so as to face the package substrate 2 and for sealing; Cap-side metallized layer (cap-side metal layer) 6a and cap member 6
Board-side metallized layer (board-side metal layer) which is provided on the package board 2 and faces the solder 7 for sealing.
2a.

Further, in the BGA 1 of the present embodiment, the cap-side metallized layer 6a is formed to have a wider width than the substrate-side metallized layer 2a, and is bonded to the substrate-side metallized layer 2a of the solder 7 for sealing. The side joint surface 7b is arranged at a position corresponding to an inner region of the joint surface 6b of the cap member 6 on the package substrate 2.

That is, in the BGA 1, as shown in FIG. 2, the substrate side metallized layer 2 a on the package substrate 2 provided corresponding to the leg of the cap member 6 The end of the leg of the cap member 6 is provided inside the portion corresponding to the outer edge portion 6c, and is provided outside the portion corresponding to the inner edge portion 6d of the end portion of the leg portion of the cap member 6.

Thus, the cap-side joining surface 7a for joining the sealing solder 7 to the cap-side metallized layer 6a is
The board-side joint surface 7b of the sealing member 7 is formed to have a wider width than the board-side joint surface 7b joined to the board-side metallized layer 2a. Is arranged at a location corresponding to the inside area of

Incidentally, the cap-side metallized layer 6a and the substrate-side metallized layer 2a may be formed to have the same width.

In this case, however, the metallized layer 2a on the substrate side is located on the periphery of the package substrate 2 inside the portion corresponding to the outer edge 6c of the end of the leg of the cap member 6 and at the same time. 6 must be provided outside a portion corresponding to the inner edge portion 6d of the end portion of the leg portion, and in this case, the joining surface 6b of the cap member 6
And a substrate-side metallization layer 2a provided on the periphery of the package substrate 2.
Have exactly the same width, and both are arranged facing each other.

As shown in FIG. 1, the semiconductor chip 5 is face-down bonded to the package substrate 2 via a chip bump 4 which is bonded to a bump land 3 which is a terminal provided on the main surface of the package substrate 2. Then, the package substrate 2 is hermetically sealed by a cap member 6 joined via a sealing solder 7.

That is, in the semiconductor chip 5, the bumps 4 for the chip are attached to the pads 5a which are the surface electrodes, and the bumps 4 are reflowed.
The chip bumps 4 may be attached to the bump lands 3 on the package substrate 2 at the time of die bonding.

The package substrate 2 is a multilayer wiring substrate provided with an internal wiring 10 for electrically connecting the bump land 3 on the main surface side and the bump land 3 on the opposite side. The internal wiring 10 is formed of a ceramic material such as a flexural strength of 20 kg / mm ² ) or alumina, and the internal wiring 10 is formed of tungsten or the like.

The cap member 6 is connected to the semiconductor chip 5.
3 which has a high breaking strength and high heat transfer, such as aluminum nitride (deflecting strength of 35 kg / mm). ² ) and the like (if heat dissipation is not important, alumina may be used).

Further, the substrate-side metallized layer 2a provided on the periphery of the main surface of the package substrate 2 is made of, for example, W
(Tungsten) -Ni (nickel) -Au (gold) alloy, etc., while the cap side metallization layer 6a provided on the joint surface 6b of the leg of the cap member 6
Is formed of a Ti (titanium) -Ni (nickel) -Au (gold) alloy or the like.
Since u is contained, the wettability with the sealing solder 7 can be improved.

The back surface 5b of the semiconductor chip 5 is soldered to the inner top surface of the cap 6 by the heat transfer solder 9. This is because the heat generated from the semiconductor chip 5 is transmitted to the cap member 6 via the heat transfer solder 9.

The sealing solder 7 and the heat transfer solder 9 are, for example, Au / Sn solder and Pb / Sn solder.

The bump electrodes 8 which are external terminals of the BGA 1 are provided, for example, in a grid pattern.

Next, the semiconductor device (B
The method of manufacturing GA1) will be described.

First, of the cap-side metallized layer 6a and the substrate-side metallized layer 2a to be joined to the sealing solder 7 as a joining member, the joint surface 6b of the leg of the cap member 6
The cap member 6 is formed so that the cap-side metallized layer 6a provided on the substrate has a wider width than the substrate-side metallized layer 2a provided on the peripheral portion of the package substrate 2.

Thereafter, the chip bumps 4 are temporarily fixed to the pads 5a of the semiconductor chip 5 or the bump lands 3 on the main surface of the package substrate 2 by a printing or transfer method.

Subsequently, the semiconductor chip 5 is arranged on the package substrate 2 with the chip bumps 4 interposed therebetween.

Thereafter, the chip bumps 4 are melted by reflow, so that the semiconductor chip 5 is mounted on the package substrate 2 (chip mount).

Subsequently, a solder preform of the heat transfer solder 9 is arranged on the back surface 5b of the semiconductor chip 5,
A solder preform of the sealing solder 7 is disposed on the substrate-side metallized layer 2a of the package substrate 2, and a cap member 6 is further placed on the solder preform of the sealing solder 7.
Position the legs.

In this state, the solder preform of the solder for sealing 7 and the solder for heat transfer 9 is melted by being passed through a reflow furnace. Are bonded via the metallized layer 2a on the substrate side and the metallized layer 6a on the cap side, and the back surface 5b of the semiconductor chip 5 and the inner top surface of the cap member 6 are bonded by the solder 9 for heat transfer.

Thus, the board-side joining surface 7b of the sealing solder 7 is arranged at a position corresponding to the area inside the joining surface 6b of the cap member 6 on the package substrate 2, and the package solder 2 is connected to the package board 2 by the sealing solder 7. The semiconductor chip 5 can be sealed by joining with the cap member 6.

Thereafter, a plurality of ball-shaped terminals such as bump electrodes 8 are attached to the bump lands 3 on the surface opposite to the main surface of the package substrate 2 by transfer or the like, and further, reflow or the like is performed to use these as external terminals. Provided on bump land 3.

Thus, the assembly of the BGA 1 is completed.

According to the semiconductor device of this embodiment and the method of manufacturing the same, the following operation and effect can be obtained.

That is, the cap-side joining surface 7a of the sealing solder 7 as the joining member of the cap member 6 is formed to have a width equal to or wider than the substrate-side joining surface 7b. 7 is disposed at a position corresponding to the area inside the bonding surface 6b of the cap member 6 on the package substrate 2,
Solder 7 for sealing between cap member 6 and package substrate 2
As shown in FIG. 2, the shrinkage stress 11 of the sealing solder 7 can be applied to the cap member 6 having higher breaking strength than the package substrate 2 at the time of solidification of the solder when the solder is fixed.

Therefore, since the shrinkage stress 11 of the sealing solder 7 applied to the package substrate 2 can be reduced, it is possible to prevent cracks from being formed in the package substrate 2.

As a result, the hermetic reliability of the hermetically sealed BGA 1 (semiconductor device) using the cap member 6 can be improved.

It should be noted that even when a material having a high modulus of longitudinal elasticity, such as Au / Sn solder, is used for the sealing solder 7, the occurrence of cracks can be prevented.

Further, since cracks can be prevented from being formed in the package substrate 2, the occurrence of disconnection failure in the package substrate 2 can be prevented.

Thus, poor airtightness can be prevented, and as a result, the reliability of the BGA 1 can be improved.

When the package substrate 2 is a multi-layer wiring substrate as in this embodiment, the effect on disconnection failure is particularly effective.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the embodiments of the present invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the above embodiment, the case where the cap-side metallized layer 6a is provided on the joint surface 6b at the tip of the leg of the cap member 6 has been described. As shown in a partially enlarged cross-sectional view of another embodiment of FIG. 4, the cap member 6 may be provided at a position extending from the joint surface 6b to the side surface 6e at the tip of the leg of the cap member 6.

As a result, the cap-side joint surface 7a of the sealing solder 7 is disposed at a position extending from the joint surface 6b at the tip of the leg of the cap member 6 to the side surface 6e. The contraction stress 11 of the sealing solder 7 applied to the cap member 6 can be dispersed from the joint surface 6b to the side surface 6e.

Therefore, even if the strength of the cap member 6 is relatively small, it is possible to prevent the formation of cracks in the cap member 6, and as a result,
Even in a BGA1 (semiconductor device) having a relatively low strength, the hermetic reliability can be improved.

In the above embodiment, the case where the package substrate 2 as the chip supporting substrate is a substrate made of ceramic such as mullite has been described. However, the chip supporting substrate is made of a material having a relatively high breaking strength. For example, a printed wiring board may be used.

Further, in the above embodiment, the case where the semiconductor chip 5 is flip-chip connected to the package substrate 2 by the chip bumps 4 has been described. However, the semiconductor chip 5 is a wire using a metal wire for bonding. It may be electrically connected to the package substrate 2 by bonding.

In the above embodiment, the case where the semiconductor device is the BGA 1 has been described, but the semiconductor device has a structure in which the semiconductor chip 5 is hermetically sealed by the cap member 6 using the sealing solder 7. For example, a PGA (Pin Grid Array) may be used.

[0060]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). The cap-side joining surface of the sealing solder for joining the cap member is formed to have a width equal to or wider than the substrate-side joining surface, and the substrate-side joining surface of the sealing solder is formed of a cap on the chip supporting substrate. By being arranged at a position corresponding to the inner area of the joining surface of the members, the sealing solder is attached to the cap member having a higher strength than the chip supporting substrate when the solder solidifies when the cap member and the chip supporting substrate are fixed by soldering. Can be applied. This can prevent cracks from being formed in the chip supporting substrate. As a result, the hermetic reliability of the hermetically sealed semiconductor device can be improved.

(2). According to the above (1), the occurrence of disconnection failure in the chip supporting substrate can be prevented. This allows
Insufficient airtightness can be prevented, and as a result, the reliability of the semiconductor device can be improved.

(3). The shrinkage stress of the sealing solder applied to the cap member can be dispersed by disposing the cap-side bonding surface of the sealing solder over the bonding surface and the side surface of the cap member. As a result, the cap member Cracks can be prevented from being formed in the cap member even when the strength of the cap member is relatively small.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partially enlarged cross-sectional view showing a structure of a joint portion of a sealing solder in the semiconductor device shown in FIG.

FIG. 3 is an external perspective view showing the structure of the semiconductor device of FIG. 1;

FIG. 4 is a partially enlarged sectional view showing a structure of a joint portion of a sealing solder in a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 BGA (semiconductor device) 2 package substrate (chip supporting substrate) 2 a substrate-side metallized layer (substrate-side metal layer) 3 bump land 4 chip bump 5 semiconductor chip 5 a pad 5 b back surface 6 cap member 6 a cap-side metallized layer (cap side) Metal layer) 6b Joining surface 6c Outer edge 6d Inner edge 6e Side surface 7 Solder for sealing 7a Cap-side joining surface 7b Board-side joining surface 8 Bump electrode (protruding terminal) 9 Solder for heat transfer 10 Internal wiring 11 Shrinkage stress

Continued on the front page (72) Inventor Toshihiko Sato 6-16-16, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Tetsuya Hayashida 3--16, Shinmachi, Omachi, Tokyo Hitachi Device Development Center

Claims (7)

[Claims] 1. A chip supporting substrate that supports a semiconductor chip, a cap member that joins the chip supporting substrate to seal the semiconductor chip, and a sealing solder that joins the chip supporting substrate and the cap member The cap-side joint surface in the solder for sealing is formed to have a width equal to or wider than the substrate-side joint surface,
The semiconductor device, wherein the substrate-side bonding surface is disposed at a position corresponding to an inner region of the bonding surface of the cap member on the chip supporting substrate. 2. A chip supporting substrate that supports a semiconductor chip, a cap member that joins the chip supporting substrate to seal the semiconductor chip, and a sealing solder that joins the chip supporting substrate and the cap member. A cap-side metal layer provided on the cap member facing the chip supporting substrate, which is joined to the sealing solder; and the chip is joined to the sealing solder, facing the cap member. A substrate-side metal layer provided on a supporting substrate, wherein the cap-side metal layer is formed to have a width equal to or wider than the substrate-side metal layer, and wherein the substrate-side metal of the sealing solder is formed. A semiconductor device, wherein a substrate-side bonding surface to be bonded to a layer is arranged at a position corresponding to an inner region of a bonding surface of the cap member on the chip supporting substrate. 3. The semiconductor device according to claim 1, wherein a cap-side joint surface of the sealing solder is disposed over a joint surface and a side surface of the cap member. apparatus. 4. The semiconductor device according to claim 1, wherein said cap member is formed of aluminum nitride, and said chip supporting substrate is formed of ceramics. 5. The semiconductor device according to claim 1, wherein the chip support substrate is a ball grid array provided with a plurality of projecting terminals as external terminals. Semiconductor device. 6. A step of mounting a semiconductor chip on a chip supporting substrate, and forming a cap-side bonding surface of a sealing solder as a bonding member having a width equal to or wider than the substrate-side bonding surface; The substrate-side joining surface of the sealing solder is arranged at a position corresponding to an inner region of the joining surface of the cap member on the chip supporting substrate, and the chip supporting substrate and the cap member are separated by the sealing solder. A method of manufacturing a semiconductor device, comprising: a step of joining and sealing the semiconductor chip with the cap member; and a step of providing a plurality of external terminals on the chip supporting substrate. 7. The cap-side metal layer and the board-side metal layer to be joined to the sealing solder as a joining member, wherein the cap-side metal layer has a width equal to or wider than the board-side metal layer. A step of preparing the formed cap member; a step of mounting the semiconductor chip on the chip supporting substrate; and a substrate-side bonding surface of the sealing solder corresponding to an inner region of the bonding surface of the cap member on the chip supporting substrate. And bonding the chip support substrate and the cap member via the cap-side metal layer and the substrate-side metal layer by the sealing solder to seal the semiconductor chip with the cap member. A method for manufacturing a semiconductor device, comprising: a step of providing a plurality of external terminals on the chip supporting substrate.