JP3825196B2 - Electronic circuit equipment - Google Patents

Electronic circuit equipment Download PDF

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JP3825196B2
JP3825196B2 JP05123799A JP5123799A JP3825196B2 JP 3825196 B2 JP3825196 B2 JP 3825196B2 JP 05123799 A JP05123799 A JP 05123799A JP 5123799 A JP5123799 A JP 5123799A JP 3825196 B2 JP3825196 B2 JP 3825196B2
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bare chip
bonding wire
dummy
bare
silicone
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JP2000252406A (en
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堂 金塚
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
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    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、配線基板上にＩＣベアチップを搭載し、所定配線パターンとの間をボンディングワイヤで接続して成る電子回路装置に関するものである。
【０００２】
【従来の技術】
従来、ＩＣベアチップは、樹脂モールドにより、またセラミックパッケージなどの容器に収容して、配線基板上に実装されていた。しかし、電子機器・通信機器などの小型化に伴い、絶縁基板に所定配線パターンを形成した配線基板上に、直接ＩＣベアチップを搭載し、ＩＣベアチップと所定配線パターンとの間をワイヤボンディング技術によって接続した構造の電子回路装置が使用されている。
【０００３】
このようなＩＣベアチップ及びボンディングワイヤは、絶縁保護、外部からの機械的な衝撃、腐食などを防止するために、ゲル状シリコーン樹脂やゴム状シリコーン樹脂（以下、これらをシリコーン被覆部材という）によって被覆していた。
【０００４】
このシリコーン被覆部材でＩＣベアチップ及びボンディングワイヤを完全に被覆するために、配線基板上にＩＣベアチップ及びボンディングワイヤを囲う枠体部材を設け、この枠体内にシリコーン被覆部材を充填・硬化していた。また、配線基板の表面に凹部を設け、この凹部の底面にＩＣベアチップを搭載し、ボンディングワイヤで電気的な接続処理を施し、凹部内にシリコーン被覆部材を充填・硬化していた。
【０００５】
しかし、上述の枠体を用いたり、また、基板の表面に凹部を形成したりして、シリコーン被覆部材の被覆領域を規定する構造では、部品点数が増加したり、基板の構造が複雑になったりして、低コストが困難であった。
【０００６】
こに対して、シリコーン被覆部材の液粘性などを制御して、枠体部材や凹部を設けず、配線基板上に直接搭載したＩＣベアチップ及びボンディングワイヤにシリコーン被覆部材で被覆することも提案されている（特開平１０−５０８９６号、特開平１０−４１４３８号）。
【０００７】
しかし、配線基板上にＩＣベアチップを搭載し、ボンディングワイヤを形成して、その上部にシリコーン被覆部材で被覆するにあたり、シリコン被覆部材がＩＣベアチップ及び該ＩＣベアチップと接合するボンディングワイヤを完全被覆する必要があり、そのため枠体に代わる低背の半田レジスト膜を形成したり、ＩＣベアチップの形状の角部を削除したりしていた。
【０００８】
【発明が解決しようとする課題】
しかし、実際には、配線基板上にボンディングワイヤで接合した状態のＩＣベアチップを搭載し、シリコーン被覆部材で被覆した場合に、以下の２つの問題は完全に解決されるに至らなかった。
【０００９】
１つは、ＩＣベアチップ及びボンディングワイヤを被覆するシリコーン被覆部材となる前駆体液（シリコーン被覆部材を形成するための供給した樹脂液）は、その供給時において配線基板上に平面方向に拡がり、その結果、ＩＣベアチップ上のシリコーン被覆部材の厚みが薄くなってしまう。その結果、ＩＣベアチップに接合したボンディングワイヤの頂点部分が外部に露出し、ボンディングワイヤの腐食が発生してしまう。同時に、十分な厚みが得られず、耐衝撃性が低下してしまう。
【００１０】
今１は、逆にＩＣベアチップ上に供給したシリコーン被覆部材が厚くなりすぎると、外部の衝撃により、シリコーン被覆部材が樹脂振動してしまう。そして、この振動による応力は、ボンディングワイヤに加わり、ボンディングワイヤの断線、剥離、ボンディングワイヤ倒れなどを発生してしまう。
【００１１】
特に、同一平面上に配線基板上に、頂点高さが異なるボンディングワイヤによって接続された２つのＩＣベアチップ（一方が信号処理系のＩＣベアチップ、他方が電力処理系ＩＣベアチップ）を夫々隣接配置し、該２つのＩＣベアチップ上に連続したシリコーン被覆部材で被覆してなる電子回路装置では、夫々のシリコーン被覆部材の高さを制御しないと、上述の問題点がいずれかの問題が発生してしまう。
【００１２】
本発明は、上述の問題点に鑑みて案出されたものであり、その目的は、ＩＣベアチップ上に被覆するシリコーン被覆部材の厚みを制御して、ボンディングワイヤの腐食を防止するとともに、ボンディングワイヤの断線・剥離・倒れを防止することができる電子部品装置を提供することにある。
【００１３】
【課題を解決するための手段】
第１の発明は、配線基板上に、頂点部の高さが異なるボンディングワイヤによって接続された少なくとも２つのＩＣベアチップを隣接配置するとともに、前記２つのＩＣベアチップ及びボンディングワイヤを樹脂（シリコーン被覆部材）で被覆してなる電子回路装置において、前記２つのＩＣベアチップ間の配線基板領域に、第１のダミー用ボンディングワイヤを前記２つのＩＣベアチップの配列方向を横切る方向に配設するとともに、頂点部の高いボンディングワイヤが接続されたＩＣベアチップ外周の配線基板領域に、前記第１のダミー用ボンディングワイヤと直交する方向に一対の第２のダミー用ボンディングワイヤを配設して成り、かつ前記頂点部の高いボンディングワイヤの頂点部高さをＨ1、頂点部の低いボンディングワイヤの頂点部高さをＨ2、第１のダミー用ボンディングワイヤの頂点部高さをＨ3、第２のダミー用ボンディングワイヤの頂点部高さをＨ4とした時、各々の高さがＨ4＞Ｈ1であり、且つＨ4＞Ｈ3＞Ｈ2である電子回路装置である。
【００１４】
このような構成により、ＩＣベアチップ及びボンディングワイヤを被覆するシリコーン被覆部材となる前駆体液を供給した時、前駆体液はその表面張力により各ボンディングワイヤにまとわりついて保持される。その結果、シリコーン被覆部材の表面は、一方のＩＣベアチップ（電力処理系ＩＣベアチップでボンディングワイヤが太く、頂点部の高さが高い側のＩＣベアチップ）から他方のＩＣベアチップ（信号処理系ＩＣベアチップでボンディングワイヤが細く、頂点部の高さが低い側のＩＣベアチップ）にかけて傾斜することになる。そして、第１ダミー用ボンディングワイヤ及び第１ダミー用ボンディングワイヤを有する本発明の構造では、シリコーン被覆部材の表面は、第２のダミー用ボンディングワイヤから第１のダミー用ボンディングワイヤにかけて急勾配の傾斜面となり、第１のダミー用ボンディングワイヤから他方のＩＣベアチップのボンディングワイヤにかけて緩やかな傾斜面となる。
【００１５】
これにより、一方のＩＣベアチップにおいて、このＩＣベアチップに接合するボンディングワイヤは、第２のダミー用ボンディングワイヤの存在により、シリコーン被覆部材によって完全に被覆されることになる。他方のＩＣベアチップにおいては、厚みが薄いシリコーン被覆部材が存在することになる。
【００１６】
従って、一方のＩＣベアチップに接合するボンディングワイヤはシリコーン被覆部材に埋設されることになり、腐食などが一切発生しない。
【００１７】
また、他方のＩＣベアチップにおいては、シリコーン被覆部材に外部衝撃が加わり、樹脂振動が発生しても、厚みが薄いため、その樹脂振動による応力を小さくなる。その結果、ボンディングワイヤの断線、剥離、倒れなどを有効に抑えることができる。
【００１８】
しかも、基板平面方向に広がろうとするシリコーン被覆部材の前駆体液は、第２のダミー用ボンディングワイヤに保持されるように働くため、配線基板上に拡がりにくく、シリコーン被覆部材の形成に必要な面積を小さくすることができる。これにより配線基板の小型化が可能となる。
【００１９】
また、シリコーン被覆部材の前駆体液の拡がりを制御できるため、シリコーン被覆部材の厚みを同時に容易に管理することもできる。
【００２３】
第２の発明は、配線基板上に、ボンディングワイヤによって接続されたＩＣベアチップを配置するとともに、該ＩＣベアチップの対角線上に、該ＩＣベアチップに接続するボンディングワイヤの頂点部の高さよりも高い頂点部を有し、且つＩＣベアチップを跨ぐダミー用ボンディングワイヤを配設し、かつ前記ＩＣベアチップ及びダミー用ボンディングワイヤを樹脂で被覆したことを特徴とする電子回路装置である。
【００２４】
この発明は、上述の第１の発明の一方のＩＣベアチップや他方のＩＣベアチップに、さらに、単独に配線基板上に搭載されたＩＣベアチップに適用することができる。
【００２５】
この発明の構造のように、ＩＣベアチップ上部で、対角線上に延びるダミー用ボンディングワイヤがシリコーン被覆部材内に埋設されることになる。このため、ＩＣベアチップ上のシリコーン被覆部材の厚みを容易に制御でき、シリコーン被覆部材自身の機械的な強度を向上させることができる。従って、ボンディングワイヤの腐食を防止するとともに、外部衝撃による樹脂振動の応力が発生しても、その応力を減少させることができ、ボンディングワイヤの断線・剥離・倒れを有効に防止できる。さらに、基板平面上に広がるシリコーン被覆部材の前駆体液を抑制でき、その結果、ＩＣベアチップを被覆するシリコーン被覆部材の領域を小さくすることができる。
【００２６】
【発明の実施の形態】
以下、本発明の電子回路装置を図面に基づいて詳説する。
【００２７】
図１は、本発明の電子回路装置の部分平面図であり、図２はＸ−Ｘ線の断面図である。
【００２８】
本発明の電子回路装置１０は、絶縁基板１１上に所定配線パターンを形成した配線基板１と、電力処理系ＩＣベアチップ２と、信号処理系ＩＣベアチップ３と、第１〜第２のダミー用ボンディングワイヤ４、５、ゲル状シリコーン樹脂やゴム状シリコーン樹脂の被覆部材（以下、これらをシリコーン被覆部材７という）とから構成されている。
【００２９】
絶縁基板１１は、例えばアルミナ、チッ化アルミなどのセラミック材料、ガラスエポキシ基板などから成る。絶縁基板１１上には、所定配線パターンが形成されている。この配線パターンとは、ＩＣベアチップ２、３が搭載される部位の電極パッド２１、３１、ＩＣベアチップ２、３と電気的に接続される配線パターン２２、３２、第１のダミー用ボンディングワイヤ４が形成されるダミー用電極パッド４１、第１のダミー用ボンディングワイヤ５が結合されるダミー用電極パッド５１を含んでいる。
【００３０】
このような配線パターンは、例えば、ＡｇやＡｇ−Ｐｄ、銅などの導体膜上に、必要に応じてＮｉメッキ及びＡｕメッキが施されている。
【００３１】
ＩＣベアチップ２（一方のＩＣベアチップ）は、例えば、電力処理系ＩＣベアチップであり、電源端子やバイアス供給端子などの比較的大きな電力が供給される増幅用トランジスタやソレノイド、モータなどを駆動させるためのスイッチングトランジスタなどが例示でき、例えばＭＯＳＦＥＴである。例えばソレノイド、モータなどを駆動させるためのスイッチングトランジスタでは、約１Ａの大きな電流の処理が行なわれる。尚、図では省略しているが、ＩＣベアチップ２の上面には入出力パッドが形成されている。
【００３２】
ＩＣベアチップ３（他方のＩＣベアチップ）は、例えば、信号系処理系ＩＣベアチップであり、Ｃ−ＭＯＳＩＣなどが例示でき、例えば数μＡ〜数百ｍＡ程度の信号を処理するものである。尚、図では省略しているがＩＣベアチップ３の上面には入出力パッドが形成されている。
【００３３】
このＩＣベアチップ２は、絶縁基板１１の電極パッド２１上に搭載されている。そして、ＩＣベアチップ２の上面の入出力パッドと絶縁基板１１の所定配線パターン２２の一部との間には、アルミニウム、Ａｕなどのボンディングワイヤ２０がボンディング接合されて、互いの電気的な接続が達成される。尚、電力処理系ＩＣベアチップ２に接合されるボンディングワイヤ２０は、例えば直径１００〜５００μｍのアルミワイヤーなどが例示でき、ボンディングワイヤ２０の頂点部の高さＨ1 は絶縁基板１１の表面から例えば１．５〜２．０ｍｍとなっている。
【００３４】
また、ＩＣベアチップ３は、絶縁基板１１の電極パッド３１上に搭載されている。そして、ＩＣベアチップ３の上面の入出力パッドと絶縁基板１１の所定配線パターン３２の一部との間には、アルミニウム、Ａｕなどのボンディングワイヤ３０がボンディング接合されて、互いの電気的に接続が達成される。尚、信号処理系ＩＣベアチップ３に接合されるボンディングワイヤ３０は、例えば直径３０〜５０μｍのアルミワイヤーなどが例示でき、ボンディングワイヤ３０の頂点部の高さＨ2 は絶縁基板１１の表面から例えば０．７〜１．０ｍｍとなっている。
【００３５】
通常、電力処理系ＩＣベアチップ２に用いるボンディングワイヤ２０は、上述のように１Ａ程度の大きな電流が流れることから、その直径を太くしている。また、直径を太くした結果、ワイヤが撓みにくくなるため、ボンディングワイヤの頂点部の高さを高く、ボンディング距離を長くして、安定したワイヤボンディングができるようにしている。結果、上述のように、信号処理系ＩＣベアチップ３に用いるボンディングワイヤ３０に比較して、ボンディングワイヤ２０の頂点部の高さＨ1 が高くなってしまう。
【００３６】
第１のダミー用ボンディングワイヤ４は、ＩＣベアチップ２とＩＣベアチップ３との間に、ＩＣベアチップ２、３の配列方向を横切るように配置された電極パッド４１、４１間に形成されるボンディングワイヤである。この第１のダミー用ボンディングワイヤ４は、例えば直径１００〜５００μｍのアルミワイヤーであり、ボンディングワイヤ４の頂点部は、ＩＣベアチップ２とＩＣベアチップ３との幅方向の略中心部に位置している。そして、ボンディングワイヤ２０の頂点部の高さをＨ1 、ボンディングワイヤ３０の頂点部の高さをＨ2 、第１のダミー用ボンディングワイヤ４の頂点部の高さをＨ3 とした時、第１のダミー用ボンディングワイヤ４の高さＨ3 を、Ｈ2 ＜Ｈ3 ＜Ｈ1 となるように設定する。
【００３７】
第２のダミー用ボンディングワイヤ５は、例えば、ＩＣベアチップ２の一対の辺、図ではＩＣベアチップ２の上辺及び下辺の外周に、該辺に平行に配置された電極パッド５１、５１間に形成されるボンディングワイヤである。この第２のボンディングワイヤ５は、例えば直径１００〜５００μｍのアルミワイヤーであり、ボンディングワイヤ５の頂点部は、ＩＣベアチップ２に接続されたボンディングワイヤ２０の頂点を考慮し設計されており、例えば、図２に示す断面において、第２のダミー用ボンディングワイヤ５内に、ＩＣベアチップ２に接続されたボンディングワイヤ２０が位置するようにすることが望ましい。
【００３８】
第２のダミー用ボンディングワイヤ５の頂点部の高さＨ4 は、ＩＣベアチップ２に接続したボンディングワイヤ２０の頂点高さＨ1 とした時、Ｈ4 ＞Ｈ1 となるように設定する。
【００３９】
シリコーン被覆部材７は、配線基板１に搭載したＩＣベアチップ２、３及びそれに接合するボンディングワイヤ２０、３０を絶縁的に保護し、外部からの機械的な衝撃から保護し、腐食などを防止するためのものである。具体的には、ゲル状またはゴム状シリコーン樹脂である。そして、シリコーン被覆部材７は、ＩＣベアチップ２、３に連続して共通的に被覆されている。このシリコーン被覆部材７の前駆体液は、液粘度が３０００ポイズ以上であり、チクソ性（塑性変形の度合、即ち、前駆体液を塗布供給した時に原形を維持する度合を示す性質、例えば、塗布供給５回転／秒させた時に得られる粘度と塗布供給１５回転／秒させた時に得られる粘度との比率が１０以上）を有しており、この前駆体液を加熱硬化しすることにより、シリコーン被覆部材７が得られる。得られたシリコーン被覆部材７は、ゴム状またゲル状で所定弾性を有している。
【００４０】
第１の発明では、上述したように、配線基板１上に頂点部の高さＨ1 、Ｈ2 が異なるボンディングワイヤ２０、３０によって接続されたＩＣベアチップ２、３を夫々隣接配置し、このＩＣベアチップ２、３及びボンディングワイヤ２０、３０が連続してシリコーン被覆部材７によって被覆されている。そして、シリコーン被覆部材７の表面は、ＩＣベアチップ２、３の隣接しあう間隔の配線基板領域に形成された第１のダミー用ボンディングワイヤ４を境界Ａに、シリコーン被覆部材７の厚みが厚い一方のＩＣベアチップ２の領域と、シリコーン被覆部材７の厚みの薄い他方のＩＣベアチップ３の領域とに分けられる。
【００４１】
一方のＩＣベアチップ２の領域のシリコーン被覆部材７の厚みは、は、ボンディングワイヤ２０（頂点部高さＨ1 ）よりも高い頂点部（Ｈ4 ）の一対の第２のダミー用ボンディングワイヤ５に、前駆体液が表面張力によって保持されることにより規定される。即ち、シリコーン被覆部材７によりボンディングワイヤ２０を埋設されることになる。これにより、ボンディングワイヤ２０の腐食を有効に防止できる。尚、ボンディングワイヤ２０と第２のダミー用ボンディングワイヤ５との頂点部分の差ΔＨ（＝Ｈ4 −Ｈ1 ）を０．５ｍｍ〜０．２ｍｍに設定することが望ましい。即ち、ΔＨが０．５ｍｍ未満となると、一対の第２のダミー用ボンディングワイヤ５、５間のシリコーン被覆部材７からボンディングワイヤ２０が露出することがない。ΔＨが２．０ｍｍを越えると、相対的にシリコーン被覆部材７の量が多くなり過ぎて、絶縁基板１１の表面の拡がりが増し、また、他方のＩＣベアチップ３側に過剰にシリコーン被覆部材７が移行してしまうために好ましくない。
【００４２】
また、他方のＩＣベアチップ３の領域のシリコーン被覆部材７は、第１のダミー用ボンディングワイヤ４の表面張力によって、表面の傾斜度合いが変化して、第１のダミー用ボンディングワイヤ４から他方のＩＣベアチップ３にかけて、その表面の傾斜が非常に緩やかになり、他方のＩＣベアチップ３上のシリコーン被覆部材７の厚みが薄くなる。
【００４３】
このように、特に、ＩＣベアチップ３の上部の厚みを薄くできることにより、外部衝撃により樹脂振動が発生しても、その振動による応力を低減でき、ボンディングワイヤ３０の断線・剥離・ワイヤ倒れを未然に防止できる。
【００４４】
このため、２つのＩＣベアチップ２、３を近接配置させ、ＩＣベアチップ２、３と配線パターン２２、３２との接続が安定し、しかも、ボンディングワイヤ２０、３０の腐食がなく、小型な電子回路装置となる。
【００４６】
また、ＩＣベアチップ２の互いに対向する一対の辺（図１では上下辺）の外周に、該上下辺に平行で、且つ該ＩＣベアチップ２に接続するボンディングワイヤ２０の頂点部の高さＨ1 よりも高い頂点部の高さＨ4 を有するダミー用ボンディングワイヤ（第２のダミー用ボンディングワイヤ５）が形成されている。
【００４７】
このような構造により、上述したように、配線基板１上に供給したシリコーン被覆部材７の前駆体液が広がることを抑制でき、配線基板の小型化が達成される。
【００４８】
同時に、シリコーン被覆部材７内に、ＩＣベアチップ２に接続するボンディングワイヤ２０を完全に埋設させることができるため、腐食を防止できる。
【００４９】
図３、図４は、第２の発明を第１の発明に適用した状態の平面図及びその断面図である。
【００５０】
図３、図４において、図１、図２に比較して、配線基板１上に、一対の第３のダミーボンディングワイヤ６、６が設けられた構造である。
【００５１】
一対の第３のダミーボンディングワイヤ６、６は、平面が矩形状のＩＣベアチップ３の対角線の延長線上に形成された電極パッド６１、６１、６１、６１に接合され、ＩＣベアチップ３の上方で互いに交差するように形成されている。
【００５２】
尚、一対の第３のダミー用ボンディングワイヤ６のうち、低い側の頂点部の高さをＨ5 とした場合、Ｈ2 ＜Ｈ5 となっている。
【００５３】
このようにＩＣベアチップ３の上方に略対角線上に交差しあう一対の第３のダミー用ボンディングワイヤ６、６によって、ＩＣベアチップ３上をシリコーン被覆部材７の厚みが規制できる。そして、ＩＣベアチップ３に接続するボンディングワイヤ３０がシリコーン被覆部材７の表面から露出することを完全に防止できる。また、配線基板１の表面に広がるシリコーン被覆部材７を抑制することができる。これにより、ボンディングワイヤ３つの腐食を防止でき、小型の電子回路装置となる。
【００５４】
しかも、ＩＣベアチップ３上のシリコーン被覆部材７の厚み内に、第３のダミー用ボンディングワイヤ６が埋設されるため、シリコーン被覆部材７自身の剛性を高まり、これにより、外部の衝撃によりシリコーン被覆部材７が樹脂振動が発生しようとしても、有効に抑えることができる。また、その樹脂振動を一対のダミー用ボンディングワイヤ６、６によって、振動応力を細かく分散することができ、応力自身を小さくすることができる。その結果、ボンディングワイヤ３０の切断、剥がれ、ワイヤ倒れを未然に防止することができる。
【００５５】
尚、信号系ＩＣベアチップ３は、一般に入力出力パッドが多く、ボンディングワイヤ３０が各４辺から導出されることになる。しかし、一対の第３のダミー用ボンディングワイヤ６、６が、ＩＣベアチップ３の対角線上に跨がるように形成されるため、ＩＣベアチップ３の入出力パッドに接続されたボンディングワイヤ３０と直接接触したりすることが一切ない。
【００５６】
尚、上述の説明では、矩形状のＩＣベアチップ３の対角線を跨ぐように一対の第３のダミー用ボンディングワイヤ６、６を形成しているが、対角線上に電極パッド６１、６１を形成することができない場合には、一対の第３のダミー用ボンディングワイヤ６、６が対角線近傍になるように形成しても構わない。
【００５７】
図３、図４では、ＩＣベアチップ２、３を近接配置した電子回路装置に適用した例を示しているが、図３、４に示す一つのＩＣベアチップ３が単独に形成された電子回路装置にも適用できる。また、上述の例では、ＩＣベアチップ３の上方を、２本の第３のダミー用ボンディングワイヤ６，６で跨ぐように形成したが、一方の対角線上を跨ぐ１本の第３のダミー用ボンディングワイヤ６を形成しても構わない。
【００５８】
尚、第１〜第３のダミー用ボンディングワイヤ４、５、６の電気的な接続について言及していなが、例えば、そのインダクタンス成分を利用して、インダクタンス素子として利用してもよい。また、ＩＣベアチップ周囲の複雑な配線パターンを簡略化するためのジャンパー導体として用いても構わない。
【００５９】
【発明の効果】
以上のように、ＩＣベアチップと配線基板の所定配線パターンとを接続するボンディングワイヤ以外に、２つのＩＣベアチップ間に、また、ＩＣベアチップの一対の辺に各々平行に、さらに、ＩＣベアチップを対角線上で跨ぐように、夫々ダミー用ボンディングワイヤを形成している。従って、ＩＣベアチップを被覆するシリコーン被覆部材の厚みを簡単に制御することができ、ＩＣベアチップ及びＩＣベアチップと接合するボンディングワイヤをシリコーン被覆部材で完全に被覆でき、ボンディングワイヤの腐食を防止することができる。
【００６０】
また、ＩＣベアチップ上のシリコーン被覆部材の厚み部分に発生する外部衝撃による樹脂振動を有効に抑えることができ、ボンディングワイヤの断線、剥離、ワイヤ倒れを未然に防止することができる。
【図面の簡単な説明】
【図１】本発明の電子回路装置の概略平面図である。
【図２】本発明の図１中のＸ−Ｘ線の断面図である。
【図３】本発明の他の電子回路装置の概略平面図である。
【図４】本発明の図１中のＹ−Ｙ線の断面図である。
【符号の説明】
１０・・・電子回路装置
１・・・・配線基板
１１・・・絶縁基板
２１、３１・・電極パッド
２２、３２・・配線パターン
４１、５１、６１・・電極パッド
２・・・・ＩＣベアチップ（電力処理系ＩＣベアチップ）
３・・・・ＩＣベアチップ（信号処理系ＩＣベアチップ）
４・・・第１のダミー用ボンディングワイヤ
５・・・第２のダミー用ボンディングワイヤ
６・・・第３のダミー用ボンディングワイヤ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic circuit device in which an IC bare chip is mounted on a wiring board and connected to a predetermined wiring pattern with a bonding wire.
[0002]
[Prior art]
Conventionally, an IC bare chip has been mounted on a wiring substrate by resin molding or in a container such as a ceramic package. However, with the downsizing of electronic devices and communication devices, IC bare chips are directly mounted on a wiring board that has a predetermined wiring pattern formed on an insulating substrate, and the IC bare chip and the predetermined wiring pattern are connected by wire bonding technology. An electronic circuit device having the structure described above is used.
[0003]
Such IC bare chips and bonding wires are covered with a gel-like silicone resin or rubber-like silicone resin (hereinafter referred to as a silicone-coated member) in order to prevent insulation protection, mechanical shock from outside, corrosion, etc. Was.
[0004]
In order to completely cover the IC bare chip and the bonding wire with the silicone covering member, a frame member surrounding the IC bare chip and the bonding wire is provided on the wiring board, and the silicone covering member is filled and cured in the frame. Further, a concave portion is provided on the surface of the wiring substrate, an IC bare chip is mounted on the bottom surface of the concave portion, an electrical connection process is performed with a bonding wire, and the silicone coating member is filled and cured in the concave portion.
[0005]
However, in the structure in which the above-described frame body is used or the concave portion is formed on the surface of the substrate to define the covering region of the silicone covering member, the number of parts increases or the structure of the substrate becomes complicated. As a result, low cost was difficult.
[0006]
On the other hand, it has also been proposed to control the liquid viscosity of the silicone coating member to cover the IC bare chip and the bonding wire directly mounted on the wiring board with the silicone coating member without providing the frame member or the recess. (JP-A-10-50896, JP-A-10-41438).
[0007]
However, when an IC bare chip is mounted on a wiring board, a bonding wire is formed, and the upper part is covered with a silicone coating member, the silicon coating member must completely cover the IC bare chip and the bonding wire to be bonded to the IC bare chip. For this reason, a low-profile solder resist film instead of the frame is formed, or the corners of the IC bare chip shape are deleted.
[0008]
[Problems to be solved by the invention]
However, actually, when an IC bare chip bonded with a bonding wire is mounted on a wiring board and covered with a silicone coating member, the following two problems have not been completely solved.
[0009]
One is that the precursor liquid (the supplied resin liquid for forming the silicone coating member) that becomes a silicone coating member that covers the IC bare chip and the bonding wire spreads in the plane direction on the wiring board at the time of the supply, and as a result The thickness of the silicone-coated member on the IC bare chip is reduced. As a result, the apex portion of the bonding wire bonded to the IC bare chip is exposed to the outside, and the bonding wire is corroded. At the same time, a sufficient thickness cannot be obtained, and the impact resistance is lowered.
[0010]
In contrast, when the silicone coating member supplied on the IC bare chip is too thick, the silicone coating member vibrates due to an external impact. The stress due to the vibration is applied to the bonding wire, and the bonding wire is disconnected, peeled off, or the bonding wire falls.
[0011]
In particular, two IC bare chips (one signal processing IC bare chip and the other power processing IC bare chip) connected to each other on the same plane by bonding wires having different vertex heights are arranged adjacent to each other, In the electronic circuit device formed by coating the two IC bare chips with the continuous silicone coating member, the above-described problems will occur as long as the height of each silicone coating member is not controlled.
[0012]
The present invention has been devised in view of the above-mentioned problems, and its purpose is to control the thickness of a silicone-coated member coated on an IC bare chip to prevent the bonding wire from being corroded. It is an object of the present invention to provide an electronic component device that can prevent disconnection, peeling, and falling.
[0013]
[Means for Solving the Problems]
According to a first aspect of the present invention, at least two IC bare chips connected by bonding wires having different apex heights are arranged adjacent to each other on a wiring board, and the two IC bare chips and the bonding wires are made of resin (silicone-coated member). The first dummy bonding wire is disposed in a direction crossing the arrangement direction of the two IC bare chips in the wiring board region between the two IC bare chips. the wiring substrate area of the IC bare chip periphery a high bonding wires are connected, become by disposing a pair of second dummy bonding wire to said first dummy bonding wire and a straight direction orthogonal, and the apex portion high bonding wires apex height H 1, the lower the bonding wire of the apex portion H 2 point unit height, the first dummy bonding wire apex height of H 3 of, when the apex height of the second dummy bonding wire was H 4, each of the height H 4 An electronic circuit device in which> H 1 and H 4 > H 3 > H 2 .
[0014]
With such a configuration, when a precursor liquid serving as a silicone coating member that covers the IC bare chip and the bonding wire is supplied, the precursor liquid is held together by bonding with each bonding wire due to its surface tension. As a result, the surface of the silicone-coated member is changed from one IC bare chip (power processing IC bare chip with a thick bonding wire and a high apex height) to the other IC bare chip (signal processing IC bare chip). The bonding wire is slender and tilts toward the IC bare chip on the side where the height of the apex portion is low. In the structure of the present invention having the first dummy bonding wire and the first dummy bonding wire, the surface of the silicone covering member is steeply inclined from the second dummy bonding wire to the first dummy bonding wire. And a gentle inclined surface from the first dummy bonding wire to the bonding wire of the other IC bare chip.
[0015]
Thereby, in one IC bare chip, the bonding wire bonded to the IC bare chip is completely covered with the silicone covering member due to the presence of the second dummy bonding wire. In the other IC bare chip, there is a thin silicone-coated member.
[0016]
Therefore, the bonding wire bonded to one IC bare chip is embedded in the silicone-coated member, and no corrosion or the like occurs.
[0017]
Further, in the other IC bare chip, even if an external impact is applied to the silicone-coated member and resin vibration occurs, the thickness due to the resin vibration is small, so the stress due to the resin vibration is reduced. As a result, it is possible to effectively suppress disconnection, peeling, and falling of the bonding wire.
[0018]
In addition, since the precursor liquid of the silicone-coated member that tends to spread in the plane direction of the substrate works so as to be held by the second dummy bonding wire, it is difficult to spread on the wiring substrate, and the area necessary for forming the silicone-coated member Can be reduced. As a result, the wiring board can be miniaturized.
[0019]
In addition, since the spread of the precursor liquid of the silicone coating member can be controlled, the thickness of the silicone coating member can be easily managed simultaneously.
[0023]
According to a second aspect of the present invention, an IC bare chip connected by a bonding wire is disposed on a wiring board, and a vertex portion higher than the height of the vertex portion of the bonding wire connected to the IC bare chip is disposed on a diagonal line of the IC bare chip. The electronic circuit device is characterized in that a dummy bonding wire straddling the IC bare chip is disposed, and the IC bare chip and the dummy bonding wire are covered with a resin.
[0024]
The present invention can be applied to one IC bare chip or the other IC bare chip of the first invention described above, and further to an IC bare chip mounted on a wiring board independently.
[0025]
Like the structure of the present invention, dummy bonding wires extending diagonally above the IC bare chip are embedded in the silicone-coated member. For this reason, the thickness of the silicone coating member on the IC bare chip can be easily controlled, and the mechanical strength of the silicone coating member itself can be improved. Therefore, corrosion of the bonding wire can be prevented, and even if resin vibration stress is generated due to external impact, the stress can be reduced, and the bonding wire can be effectively prevented from being disconnected, peeled off or collapsed. Furthermore, the precursor liquid of the silicone-coated member spreading on the substrate plane can be suppressed, and as a result, the area of the silicone-coated member that covers the IC bare chip can be reduced.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an electronic circuit device of the present invention will be described in detail with reference to the drawings.
[0027]
FIG. 1 is a partial plan view of an electronic circuit device of the present invention, and FIG. 2 is a sectional view taken along line XX.
[0028]
The electronic circuit device 10 of the present invention includes a wiring board 1 having a predetermined wiring pattern formed on an insulating substrate 11, a power processing IC bare chip 2, a signal processing IC bare chip 3, and first and second dummy bondings. It is comprised from the wires 4 and 5 and the coating member (henceforth the silicone coating member 7) of gel-like silicone resin or rubber-like silicone resin.
[0029]
The insulating substrate 11 is made of, for example, a ceramic material such as alumina or aluminum nitride, a glass epoxy substrate, or the like. A predetermined wiring pattern is formed on the insulating substrate 11. This wiring pattern includes electrode pads 21 and 31 where IC bare chips 2 and 3 are mounted, wiring patterns 22 and 32 electrically connected to IC bare chips 2 and 3, and first dummy bonding wires 4. The dummy electrode pad 41 to be formed and the dummy electrode pad 51 to which the first dummy bonding wire 5 is coupled are included.
[0030]
Such a wiring pattern is subjected to Ni plating and Au plating, if necessary, on a conductor film such as Ag, Ag-Pd, or copper.
[0031]
The IC bare chip 2 (one IC bare chip) is, for example, a power processing IC bare chip for driving an amplifying transistor, a solenoid, a motor, or the like to which relatively large power is supplied such as a power supply terminal and a bias supply terminal. A switching transistor etc. can be illustrated, for example, it is MOSFET. For example, a switching transistor for driving a solenoid, a motor or the like processes a large current of about 1A. Although not shown in the drawing, an input / output pad is formed on the upper surface of the IC bare chip 2.
[0032]
The IC bare chip 3 (the other IC bare chip) is, for example, a signal processing IC bare chip, and can be exemplified by a C-MOSIC and the like, for example, for processing a signal of several μA to several hundred mA. Although not shown in the figure, input / output pads are formed on the upper surface of the IC bare chip 3.
[0033]
The IC bare chip 2 is mounted on the electrode pad 21 of the insulating substrate 11. A bonding wire 20 such as aluminum or Au is bonded between the input / output pads on the upper surface of the IC bare chip 2 and a part of the predetermined wiring pattern 22 of the insulating substrate 11 so that electrical connection between them is achieved. Achieved. The bonding wire 20 bonded to the power processing IC bare chip 2 can be exemplified by an aluminum wire having a diameter of 100 to 500 μm, for example. The height H 1 of the apex portion of the bonding wire 20 is, for example, 1 from the surface of the insulating substrate 11. .5 to 2.0 mm.
[0034]
The IC bare chip 3 is mounted on the electrode pad 31 of the insulating substrate 11. A bonding wire 30 such as aluminum or Au is bonded between the input / output pads on the upper surface of the IC bare chip 3 and a part of the predetermined wiring pattern 32 of the insulating substrate 11 to electrically connect each other. Achieved. The bonding wire 30 bonded to the signal processing IC bare chip 3 can be exemplified by an aluminum wire having a diameter of 30 to 50 μm, for example, and the height H 2 of the apex portion of the bonding wire 30 is, for example, 0 from the surface of the insulating substrate 11. .7 to 1.0 mm.
[0035]
Usually, the bonding wire 20 used for the power processing IC bare chip 2 has a large diameter because a large current of about 1 A flows as described above. Further, since the wire is difficult to bend as a result of increasing the diameter, the height of the apex portion of the bonding wire is increased and the bonding distance is increased so that stable wire bonding can be performed. As a result, as described above, the height H 1 of the apex portion of the bonding wire 20 becomes higher than the bonding wire 30 used in the signal processing IC bare chip 3.
[0036]
The first dummy bonding wire 4 is a bonding wire formed between the electrode pads 41 and 41 arranged between the IC bare chip 2 and the IC bare chip 3 so as to cross the arrangement direction of the IC bare chips 2 and 3. is there. The first dummy bonding wire 4 is, for example, an aluminum wire having a diameter of 100 to 500 μm, and the apex portion of the bonding wire 4 is located at a substantially central portion in the width direction between the IC bare chip 2 and the IC bare chip 3. . When the height of the apex portion of the bonding wire 20 is H 1 , the height of the apex portion of the bonding wire 30 is H 2 , and the height of the apex portion of the first dummy bonding wire 4 is H 3 , The height H 3 of the first dummy bonding wire 4 is set such that H 2 <H 3 <H 1 .
[0037]
The second dummy bonding wire 5 is formed, for example, on the pair of sides of the IC bare chip 2, in the figure, on the outer periphery of the upper side and the lower side between the electrode pads 51, 51 arranged in parallel to the side. Bonding wire. The second bonding wire 5 is, for example, an aluminum wire having a diameter of 100 to 500 μm, and the apex portion of the bonding wire 5 is designed in consideration of the apex of the bonding wire 20 connected to the IC bare chip 2. In the cross section shown in FIG. 2, it is desirable that the bonding wire 20 connected to the IC bare chip 2 is positioned in the second dummy bonding wire 5.
[0038]
The height H 4 of the apex portion of the second dummy bonding wire 5 is set so that H 4 > H 1 when the apex height H 1 of the bonding wire 20 connected to the IC bare chip 2 is set.
[0039]
The silicone covering member 7 insulates the IC bare chips 2 and 3 mounted on the wiring board 1 and the bonding wires 20 and 30 bonded thereto in an insulating manner, protects them from mechanical shocks from the outside, and prevents corrosion. belongs to. Specifically, it is a gel-like or rubber-like silicone resin. The silicone coating member 7 is continuously coated on the IC bare chips 2 and 3 in common. The precursor liquid of the silicone-coated member 7 has a liquid viscosity of 3000 poise or more, and has a thixotropy (degree of plastic deformation, that is, a property indicating the degree of maintaining the original shape when the precursor liquid is applied and supplied, for example, application and supply 5 The ratio of the viscosity obtained when rotating / sec and the viscosity obtained when applying / feeding 15 rpm is 10 or more), and by heating and curing the precursor liquid, the silicone-coated member 7 Is obtained. The obtained silicone-coated member 7 is rubber-like or gel-like and has a predetermined elasticity.
[0040]
In the first invention, as described above, the IC bare chips 2 and 3 connected by the bonding wires 20 and 30 having apex heights H 1 and H 2 different from each other are arranged adjacently on the wiring board 1. The bare chips 2 and 3 and the bonding wires 20 and 30 are continuously covered with the silicone covering member 7. The surface of the silicone coating member 7 is thicker than the silicon coating member 7 with the first dummy bonding wire 4 formed in the wiring substrate region at the interval between the IC bare chips 2 and 3 being adjacent to the boundary A. The area of the IC bare chip 2 is divided into the area of the other IC bare chip 3 where the silicone covering member 7 is thin.
[0041]
The thickness of the silicone-coated member 7 in the region of one IC bare chip 2 is such that the thickness of the second dummy bonding wire 5 at the apex (H 4 ) is higher than the bonding wire 20 (apex height H 1 ). , Defined by the precursor liquid being held by surface tension. That is, the bonding wire 20 is embedded by the silicone coating member 7. Thereby, corrosion of the bonding wire 20 can be effectively prevented. It is desirable to set the difference ΔH (= H 4 −H 1 ) between the apex portions of the bonding wire 20 and the second dummy bonding wire 5 to 0.5 mm to 0.2 mm. That is, when ΔH is less than 0.5 mm, the bonding wire 20 is not exposed from the silicone covering member 7 between the pair of second dummy bonding wires 5 and 5. When ΔH exceeds 2.0 mm, the amount of the silicone covering member 7 is relatively increased, and the surface of the insulating substrate 11 is expanded, and the silicone covering member 7 is excessively formed on the other IC bare chip 3 side. It is not preferable because it shifts.
[0042]
In addition, the silicone covering member 7 in the area of the other IC bare chip 3 changes the degree of inclination of the surface by the surface tension of the first dummy bonding wire 4, and the first dummy bonding wire 4 changes the other IC. The inclination of the surface of the bare chip 3 becomes very gentle, and the thickness of the silicone-coated member 7 on the other IC bare chip 3 is reduced.
[0043]
In this way, in particular, the thickness of the upper part of the IC bare chip 3 can be reduced, so that even if resin vibration occurs due to external impact, the stress due to the vibration can be reduced, and the bonding wire 30 can be disconnected, peeled off, or collapsed. Can be prevented.
[0044]
Therefore, the two IC bare chips 2 and 3 are arranged close to each other, the connection between the IC bare chips 2 and 3 and the wiring patterns 22 and 32 is stable, and the bonding wires 20 and 30 are not corroded, and the electronic circuit device is small. It becomes.
[0046]
Further , the height H 1 of the apex portion of the bonding wire 20 connected to the IC bare chip 2 on the outer periphery of a pair of opposite sides (upper and lower sides in FIG. 1) of the IC bare chip 2 is parallel to the upper and lower sides. A dummy bonding wire (second dummy bonding wire 5) having a height H 4 at the highest apex portion is formed.
[0047]
With such a structure, as described above, it is possible to prevent the precursor liquid of the silicone coating member 7 supplied onto the wiring board 1 from spreading, and the wiring board can be reduced in size.
[0048]
At the same time, since the bonding wire 20 connected to the IC bare chip 2 can be completely embedded in the silicone coating member 7, corrosion can be prevented.
[0049]
3 and 4 are a plan view and a cross-sectional view of a state in which the second invention is applied to the first invention.
[0050]
3 and 4, a pair of third dummy bonding wires 6 and 6 are provided on the wiring substrate 1 as compared with FIGS. 1 and 2.
[0051]
The pair of third dummy bonding wires 6, 6 are joined to electrode pads 61, 61, 61, 61 formed on the diagonal extension of the IC bare chip 3 whose plane is rectangular, and are mutually connected above the IC bare chip 3. It is formed to intersect.
[0052]
Of the pair of third dummy bonding wires 6, H 2 <H 5 , where H 5 is the height of the lower apex.
[0053]
In this way, the thickness of the silicone coating member 7 on the IC bare chip 3 can be regulated by the pair of third dummy bonding wires 6 and 6 that intersect with each other substantially diagonally above the IC bare chip 3. And it can prevent completely that the bonding wire 30 connected to IC bare chip 3 is exposed from the surface of the silicone coating | coated member 7. FIG. Moreover, the silicone coating | coated member 7 spreading on the surface of the wiring board 1 can be suppressed. Thereby, corrosion of three bonding wires can be prevented and it becomes a small electronic circuit device.
[0054]
In addition, since the third dummy bonding wire 6 is embedded in the thickness of the silicone coating member 7 on the IC bare chip 3, the rigidity of the silicone coating member 7 itself is increased. 7 can effectively suppress the occurrence of resin vibration. Further, the resin vibration can be finely dispersed by the pair of dummy bonding wires 6 and 6, and the stress itself can be reduced. As a result, it is possible to prevent the bonding wire 30 from being cut, peeled off or collapsed.
[0055]
The signal IC bare chip 3 generally has many input / output pads, and the bonding wires 30 are led out from the four sides. However, since the pair of third dummy bonding wires 6, 6 are formed so as to straddle the diagonal line of the IC bare chip 3, they directly contact the bonding wires 30 connected to the input / output pads of the IC bare chip 3. There is nothing to do.
[0056]
In the above description, the pair of third dummy bonding wires 6 and 6 are formed so as to straddle the diagonal line of the rectangular IC bare chip 3, but the electrode pads 61 and 61 are formed on the diagonal line. If this is not possible, the pair of third dummy bonding wires 6 and 6 may be formed in the vicinity of the diagonal line.
[0057]
3 and 4 show an example in which the IC bare chip 2 and 3 are applied to an electronic circuit device in which they are arranged close to each other. However, in the electronic circuit device in which one IC bare chip 3 shown in FIGS. Is also applicable. In the above example, the upper part of the IC bare chip 3 is formed so as to straddle the two third dummy bonding wires 6, 6, but one third dummy bonding that straddles one diagonal line. The wire 6 may be formed.
[0058]
Although the electrical connection of the first to third dummy bonding wires 4, 5, 6 is not mentioned, for example, the inductance component may be used as an inductance element. Moreover, you may use as a jumper conductor for simplifying the complicated wiring pattern around IC bare chip.
[0059]
【The invention's effect】
As described above, in addition to the bonding wires for connecting the IC bare chip and the predetermined wiring pattern of the wiring board, the IC bare chip is diagonally connected between the two IC bare chips and in parallel with the pair of sides of the IC bare chip. The dummy bonding wires are formed so as to cross each other. Therefore, the thickness of the silicone-coated member that covers the IC bare chip can be easily controlled, and the bonding wire to be bonded to the IC bare chip and the IC bare chip can be completely covered with the silicone-coated member, thereby preventing corrosion of the bonding wire. it can.
[0060]
Further, it is possible to effectively suppress the resin vibration due to the external impact generated in the thickness portion of the silicone-coated member on the IC bare chip, and it is possible to prevent the bonding wire from being disconnected, peeled off, and the wire collapsed.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of an electronic circuit device of the present invention.
FIG. 2 is a cross-sectional view taken along line XX in FIG. 1 of the present invention.
FIG. 3 is a schematic plan view of another electronic circuit device of the present invention.
4 is a cross-sectional view taken along line YY in FIG. 1 of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Electronic circuit device 1 ... Wiring board 11 ... Insulating substrate 21, 31 ... Electrode pad 22, 32 ... Wiring pattern 41, 51, 61 ... Electrode pad 2 ... IC bare chip (Power processing IC bare chip)
3 .... IC bare chip (signal processing IC bare chip)
4 ... 1st dummy bonding wire 5 ... 2nd dummy bonding wire 6 ... 3rd dummy bonding wire

Claims (2)

配線基板上に、頂点部の高さが異なるボンディングワイヤが接合された少なくとも２つのＩＣベアチップを隣接配置するとともに、前記２つのＩＣベアチップ及びボンディングワイヤを樹脂で被覆して成る電子回路装置において、
前記２つのＩＣベアチップ間の配線基板領域に、第１のダミー用ボンディングワイヤを前記２つのＩＣベアチップの配列方向を横切る方向に配設するとともに、頂点部の高いボンディングワイヤが接続されたＩＣベアチップ外周の配線基板領域に、前記第１のダミー用ボンディングワイヤと直交する方向に一対の第２のダミー用ボンディングワイヤを配設して成り、かつ前記頂点部の高いボンディングワイヤの頂点部高さをＨ1、頂点部の低いボンディングワイヤの頂点部高さをＨ2、第１のダミー用ボンディングワイヤの頂点部高さをＨ3 、第２のダミー用ボンディングワイヤの頂点部高さをＨ4とした時、各々の高さがＨ4＞Ｈ1であり、且つＨ4＞Ｈ3＞Ｈ2であることを特徴とする電子回路装置。In an electronic circuit device in which at least two IC bare chips to which bonding wires having different heights of apexes are bonded are arranged adjacent to each other on a wiring board, and the two IC bare chips and the bonding wires are covered with a resin.
In the wiring board region between the two IC bare chips, the first dummy bonding wires are arranged in a direction crossing the arrangement direction of the two IC bare chips, and the outer periphery of the IC bare chip to which the bonding wires having high apex portions are connected of the wiring substrate area, the apex height of the first made by arranging a pair of second dummy bonding wire to the dummy bonding wires and straight direction orthogonal, and high the apex portion bonding wire H 1 , the vertex height of the bonding wire having a low vertex is H 2 , the vertex height of the first dummy bonding wire is H 3 , and the vertex height of the second dummy bonding wire is H 4 . The electronic circuit device is characterized in that each height is H 4 > H 1 and H 4 > H 3 > H 2 . 配線基板上に、ボンディングワイヤによって接続されたＩＣベアチップを配置するとともに、該ＩＣベアチップの対角線上に、該ＩＣベアチップに接続するボンディングワイヤの頂点部の高さよりも高い頂点部を有し、且つＩＣベアチップを跨ぐダミー用ボンディングワイヤを配設し、かつ前記ＩＣベアチップ及びダミー用ボンディングワイヤを樹脂で被覆したことを特徴とする電子回路装置。An IC bare chip connected by bonding wires is arranged on the wiring board, and has a vertex higher than the height of the vertex of the bonding wire connected to the IC bare chip on the diagonal of the IC bare chip, and the IC An electronic circuit device comprising: a dummy bonding wire straddling a bare chip; and the IC bare chip and the dummy bonding wire are covered with a resin.
JP05123799A 1999-02-26 1999-02-26 Electronic circuit equipment Expired - Fee Related JP3825196B2 (en)

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