JPH0670243U - Circuit board device - Google Patents
Circuit board deviceInfo
- Publication number
- JPH0670243U JPH0670243U JP016062U JP1606293U JPH0670243U JP H0670243 U JPH0670243 U JP H0670243U JP 016062 U JP016062 U JP 016062U JP 1606293 U JP1606293 U JP 1606293U JP H0670243 U JPH0670243 U JP H0670243U
- Authority
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- Japan
- Prior art keywords
- wiring
- wiring pattern
- chip
- circuit element
- bare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】
【目的】 回路基板装置の配線パターン形成の自由度を
増大し、、配線長を短縮して特性を向上させると共に、
回路素子を電気的に安定化させる。
【構成】 ＣＯＢ等の回路基板装置において、絶縁基板
（５）のチップ回路素子（１）のダイボンディング領域
を含む領域に配線パターン（４）を形成し、チップ回路
素子（１）裏面と電気的接続させる配線部分以外のダイ
ボンディング領域には絶縁体層（６）を被覆し、その上
から導電ペースト（７）を塗布してチップ回路素子
（１）をダイボンディングする。
(57) [Abstract] [Purpose] While increasing the degree of freedom in forming the wiring pattern of the circuit board device and shortening the wiring length to improve the characteristics,
Electrically stabilize the circuit element. [Structure] In a circuit board device such as a COB, a wiring pattern (4) is formed in an area including a die bonding area of a chip circuit element (1) of an insulating substrate (5) to electrically connect to the back surface of the chip circuit element (1). The die bonding area other than the wiring portion to be connected is covered with the insulator layer (6), and the conductive paste (7) is applied thereon to die bond the chip circuit element (1).
Description
【０００１】[0001]
本考案は回路基板装置に関し、特にベア半導体チップ等の回路素子を配線基板 に直接実装して回路を構成したＣＯＢ（Ｃｈｉｐ ｏｎ Ｂｏａｒｄ）等の回路 基板装置において、配線基板のダイボンディング領域にも配線パターンを形成し て、高密度配線を可能にした技術に関する。 The present invention relates to a circuit board device, and in particular, in a circuit board device such as a COB (Chip on Board) in which a circuit element such as a bare semiconductor chip is directly mounted on a wiring board to form a circuit, wiring is also performed in a die bonding area of the wiring board. It relates to the technology that enables high-density wiring by forming patterns.
【０００２】[0002]
電子回路を構成するための電子部品として、一般に個別半導体素子が使用され ている。個別半導体素子は、半導体チップ等の回路素子を金属等からなるリード フレームに搭載して電極をワイヤボンディング等により接続したものを、湿気等 の外部環境から保護するために絶縁性部材で密閉封止し、回路素子をプリント基 板に実装するための接続端子を導出させたものである。しかし、最近の電子機器 はますます小型化と高機能化が進んでおり、例えばコンピュータ等の論理回路で は回路素子の集積度を高めるため、回路素子をさらに効率良く実装する技術が必 要とされている。 Individual semiconductor elements are generally used as electronic components for forming electronic circuits. An individual semiconductor element is a circuit element such as a semiconductor chip mounted on a lead frame made of metal, etc., with electrodes connected by wire bonding, etc., and hermetically sealed with an insulating material to protect it from the external environment such as moisture. Then, the connection terminals for mounting the circuit element on the printed circuit board are led out. However, recent electronic devices are becoming smaller and more sophisticated, and for example, in logic circuits such as computers, in order to increase the degree of integration of circuit elements, there is a need for technology for more efficient mounting of circuit elements. Has been done.
【０００３】 そこで、あらかじめ配線パターンを形成したガラスエポキシやセラミック等の 絶縁基板からなるプリント配線基板にベアＩＣチップ等の回路素子を直接ダイボ ンディングし、回路素子の電極と配線パターンをワイヤボンディング等の方法に より接続して電子回路を構成したＣＯＢ（Ｃｈｉｐ ｏｎ Ｂｏａｒｄ）の技術 が開発された。ＣＯＢは個別半導体素子のようなプリント基板に実装するための パッケージや外部端子がないため回路素子の実装密度を高めることができ、また 素子を接続する配線の長さを短縮できるので、配線抵抗や容量による遅延を減少 させて素子の高速動作を可能とする。Therefore, a circuit element such as a bare IC chip is directly die-bonded to a printed wiring board made of an insulating substrate such as glass epoxy or ceramic on which a wiring pattern is formed in advance, and the electrode of the circuit element and the wiring pattern are subjected to wire bonding or the like. A COB (Chip on Board) technology has been developed in which electronic circuits are connected by a method. Since COB does not have a package or an external terminal for mounting on a printed circuit board such as an individual semiconductor element, the packaging density of circuit elements can be increased, and the length of the wiring connecting the elements can be shortened. It reduces the delay caused by capacitance and enables high-speed operation of the device.
【０００４】 このようなＣＯＢの特徴をいかすためには、配線基板上に実装された各回路素 子を接続する配線パターンの配線長さを短くして導体抵抗や容量を減少させるこ とが必要であり、従って配線基板上の限られた領域で配線パターンをどのように 形成するかは、ＣＯＢの特性に大きな影響を及ぼす。In order to take advantage of such characteristics of COB, it is necessary to shorten the wiring length of the wiring pattern for connecting the circuit elements mounted on the wiring board to reduce the conductor resistance and capacitance. Therefore, how the wiring pattern is formed in a limited area on the wiring board has a great influence on the characteristics of the COB.
【０００５】[0005]
ところが、このようなＣＯＢの配線パターンは、従来、配線基板の回路素子実 装領域以外の領域にのみ形成されていたため、配線の自由度が低く、ＣＯＢの特 徴を充分に活用できなかった。例えば、最近の高集積デジタルＩＣチップのよう に大型化した回路素子を配線基板に実装するためには大きな実装面積が必要であ り、配線基板上での配線パターンを形成することができる領域を充分に確保する ためには配線基板も大きくする必要があり、装置の小型化が制約されるという不 都合があった。 However, since such a COB wiring pattern is conventionally formed only in a region other than the circuit element mounting region of the wiring board, the degree of freedom in wiring is low and the characteristics of COB cannot be fully utilized. For example, a large mounting area is required to mount a large-sized circuit element such as a recent highly integrated digital IC chip on a wiring board, and an area where a wiring pattern can be formed on the wiring board is required. In order to secure it sufficiently, it is necessary to make the wiring board large, which is an inconvenience that the miniaturization of the device is restricted.
【０００６】 また、大きなチップを迂回して配線パターンを形成しなければならない場合に は、配線パターンは複雑化し配線長も長くなるので、配線抵抗や容量が増大し回 路性能に悪影響を与えていた。Further, when a wiring pattern has to be formed bypassing a large chip, the wiring pattern becomes complicated and the wiring length becomes long, so that wiring resistance and capacitance increase, which adversely affects the circuit performance. It was
【０００７】 またさらに、回路素子がダイボンドされる配線基板部分がグランド等に接続で きないため、回路素子裏面は電気的にフロ−ティング状態となって電位が不安定 になり雑音等の影響を受けやすかった。Furthermore, since the wiring board portion to which the circuit element is die-bonded cannot be connected to the ground or the like, the back surface of the circuit element is electrically floating and the potential becomes unstable, and the influence of noise or the like is caused. It was easy to receive.
【０００８】 従って、本考案の目的は、ＣＯＢ等の回路基板装置において、ＩＣチップ回路 素子のダイボンディング領域にも配線パターンを形成可能とすることにより、配 線の自由度を向上させて、各回路素子を効率よく配線接続できるようにし、もっ て回路基板装置の高集積化と高性能化を図ることである。Therefore, an object of the present invention is to improve the degree of freedom of wiring by forming a wiring pattern in a die bonding area of an IC chip circuit element in a circuit board device such as a COB. The aim is to make it possible to connect circuit elements efficiently and to achieve high integration and high performance of circuit board devices.
【０００９】 さらに本考案の他の目的は、回路素子裏面に、例えば電源電圧またはグランド の電圧が接続できるようにして、回路素子の電位を安定させ、外部からの雑音に よる影響を低減することにある。Still another object of the present invention is to allow the power supply voltage or the ground voltage to be connected to the back surface of the circuit element to stabilize the potential of the circuit element and reduce the influence of external noise. It is in.
【００１０】[0010]
上記問題点の解決のため、本考案の回路基板装置は、配線パターンを形成した 配線基板に回路素子を直接ダイボンドし、回路素子の電極と配線パターンを接続 して電子回路を構成した回路基板装置において、配線パターンを回路素子のダイ ボンディング領域にも形成し、回路素子はダイボンディング領域に形成した配線 パターンの少なくとも一部に絶縁体層を積層形成した上に、導電性のろう部材に よりダイボンディングするようにしたものである。 In order to solve the above problems, the circuit board device of the present invention is a circuit board device in which a circuit element is directly die-bonded to a wiring board having a wiring pattern, and an electrode of the circuit element and the wiring pattern are connected to form an electronic circuit. A wiring pattern is also formed in the die bonding area of the circuit element, and the circuit element is formed by stacking an insulating layer on at least a part of the wiring pattern formed in the die bonding area and then using a conductive brazing material to form a die. It is designed to be bonded.
【００１１】 また、このダイボンディング領域には電源電圧Ｖｃｃまたはグランドに接続す る配線パターンを形成しておくことにより、回路素子裏面をこれらの電源電圧ま たはグランドに接続できる。By forming a wiring pattern for connecting to the power supply voltage Vcc or the ground in the die bonding region, the back surface of the circuit element can be connected to the power supply voltage or the ground.
【００１２】[0012]
このように、回路素子のダイボンディング領域にも配線パタ−ンを形成したの で、配線の自由度が増大し、配線パタ−ンを設計する際にダイボンディング領域 を迂回して形成する必要がなく、配線パタ−ンを単純化し高密度化することがで きるとともに配線の長さを短くして配線抵抗や容量を減少させることができるの で、電子回路の小型高性能化を図ることができる。 Since the wiring pattern is also formed in the die bonding area of the circuit element in this way, the degree of freedom of wiring is increased, and it is necessary to form the wiring pattern by bypassing the die bonding area when designing the wiring pattern. In addition, the wiring pattern can be simplified and the density can be increased, and the wiring length can be shortened to reduce the wiring resistance and capacitance. it can.
【００１３】 またさらに、ダイボンディング領域に電源電圧Ｖｃｃかグランドの配線パタ− ンを形成し、回路素子裏面に接続することにより、回路素子の電位を固定させて 電気的特性を安定させることができ、外部からの雑音の影響を受けにくくするこ とができる。Furthermore, by forming a wiring pattern of power supply voltage Vcc or ground in the die bonding area and connecting it to the back surface of the circuit element, the potential of the circuit element can be fixed and the electrical characteristics can be stabilized. , It is possible to reduce the influence of external noise.
【００１４】[0014]
以下、図面を参照して本考案の実施例につき説明する。図１は本考案の一実施 例に係わる回路基板装置で、チップ回路素子を基板に取り付けワイヤボンディン グが終了した状態を上から見たようすを示す。図２は図１の回路基板装置のＡ− Ａ′線に沿った断面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit board device according to an embodiment of the present invention, showing a top view of a state in which a chip circuit element is mounted on a substrate and wire bonding is completed. FIG. 2 is a sectional view taken along the line AA ′ of the circuit board device of FIG.
【００１５】 これらの図に示される回路基板装置においては、Ｃｕ等により配線パタ−ン４ をガラスエポキシやセラミックからなる絶縁基板５上に形成したプリント基板に ベアＩＣチップ１がダイボンディングされている。すなわち、ベアＩＣチップ１ は、銀などを含む導電ペ−スト７によって絶縁基板５および該絶縁基板５上の配 線パタ−ン４ａにダイボンディングされている。In the circuit board device shown in these figures, the bare IC chip 1 is die-bonded to a printed board on which the wiring pattern 4 is formed of Cu or the like on the insulating board 5 made of glass epoxy or ceramic. . That is, the bare IC chip 1 is die-bonded to the insulating substrate 5 and the wiring pattern 4a on the insulating substrate 5 by the conductive paste 7 containing silver or the like.
【００１６】 絶縁基板５上には、ベアＩＣチップ１がダイボンディングされている領域、す なわちダイボンディング領域の周囲に配線パターン４を構成する配線が形成され ている。これらの配線パターン４は、ベアＩＣチップ１の対応するボンディング パッド２とＡｕワイヤ３でワイヤボンディング接続されている。On the insulating substrate 5, a wiring forming the wiring pattern 4 is formed in the area where the bare IC chip 1 is die-bonded, that is, around the die-bonding area. These wiring patterns 4 are wire-bonded to the corresponding bonding pads 2 of the bare IC chip 1 by Au wires 3.
【００１７】 また、ベアＩＣチップ１の下側の領域には、図１の破線で示されるように配線 パタ−ンが設けられている。これらの配線パタ−ンは絶縁体層６で被覆され、該 絶縁体層６の上に導電ぺ−スト７を介してベアＩＣチップ１が接合されている。 これらの絶縁体層６で被覆された配線パタ−ンは、前記配線パターン４に繋がる ものであっても良く、あるいは配線パターン４とは独立の配線パタ−ンであって も良い。In the area below the bare IC chip 1, a wiring pattern is provided as indicated by the broken line in FIG. These wiring patterns are covered with an insulating layer 6, and the bare IC chip 1 is bonded onto the insulating layer 6 via a conductive paste 7. The wiring pattern covered with the insulating layer 6 may be connected to the wiring pattern 4 or may be a wiring pattern independent of the wiring pattern 4.
【００１８】 具体的には、上記ベアＩＣチップ１の下側に伸びる配線パタ−ンの内、配線パ ターン４ａは電源Ｖｃｃまたはグランドに接続する配線であり、ベアＩＣチップ １の底部中央付近に配線の先端が形成されている。この配線の先端部には絶縁体 層６が形成されておらず、導電ぺ−スト７に接触している。したがって、この配 線パターン４ａはベアＩＣチップ１裏面と電気的に接続されている。Specifically, of the wiring patterns extending to the lower side of the bare IC chip 1, the wiring pattern 4a is a wiring for connecting to the power supply Vcc or the ground, and is provided near the center of the bottom of the bare IC chip 1. The tip of the wiring is formed. The insulating layer 6 is not formed on the tip of this wiring, but is in contact with the conductive paste 7. Therefore, the wiring pattern 4a is electrically connected to the back surface of the bare IC chip 1.
【００１９】 また、ベアＩＣチップ１をはさみ互いに対向する辺に配置された配線パターン ４ｂ，４ｃは、ベアＩＣチップ１の下を通る配線により互いに電気的に接続され ている。そして、これら配線パターン４ｂ，４ｃは、それぞれベアＩＣチップ１ のボンディングパッド２ａ，２ｂとワイヤボンディング接続されている。したが って、ベアＩＣチップ１の異なるボンデイングパッド２ａ，２ｂは同じ配線パタ −ン４ｂ、４ｃに接続され、互いに電気的に接続されることになる。Further, the wiring patterns 4b and 4c arranged on opposite sides of the bare IC chip 1 with the bare IC chip 1 sandwiched therebetween are electrically connected to each other by a wiring passing under the bare IC chip 1. The wiring patterns 4b and 4c are connected to the bonding pads 2a and 2b of the bare IC chip 1 by wire bonding. Therefore, the different bonding pads 2a and 2b of the bare IC chip 1 are connected to the same wiring patterns 4b and 4c and electrically connected to each other.
【００２０】 さらに、ベアＩＣチップ１のボンディングパッド２ｃがワイヤボンディングさ れる配線パターン４ｄは、ベアＩＣチップ１の下側、すなわちダイボンディング 領域を引き回されてボンディングパッド２ｃから直接ボンディング接続できない 領域を通る配線パターン４ｅに接続されている。Further, the wiring pattern 4d to which the bonding pad 2c of the bare IC chip 1 is wire-bonded has a lower side of the bare IC chip 1, that is, a region which cannot be directly connected to the bonding pad 2c by being drawn around the die bonding region. It is connected to the passing wiring pattern 4e.
【００２１】 なお、図２の参照番号８は、ベアＩＣチップ１およびボンディングワイヤ３な どを含む部分を密封封止して保護するためのチップコ−ト樹脂を示している。Reference numeral 8 in FIG. 2 indicates a chip coat resin for hermetically sealing and protecting a portion including the bare IC chip 1 and the bonding wire 3.
【００２２】 このように、ベアＩＣチップ１の下部の領域、すなわちダイボンディング領域 にも配線パタ−ンを形成することにより、ベアＩＣチップ１の配線接続の自由度 が大幅に増大し、回路基板装置の小型化および高性能化を図ることができる。As described above, by forming the wiring pattern also in the lower region of the bare IC chip 1, that is, in the die bonding region, the degree of freedom of the wiring connection of the bare IC chip 1 is significantly increased, and the circuit board The device can be downsized and the performance can be improved.
【００２３】 このように、ダイボンディング領域にも配線パタ−ンを形成したので、配線パ ターン４ａのようにベアＩＣチップ１裏面に配線接続することが可能となり、こ の配線を電源電圧Ｖｃｃまたはグランドに接続することにより、ベアＩＣチップ １裏面の電位を固定する事ができ、素子の電気的特性を安定させることができる 。Since the wiring pattern is also formed in the die bonding area as described above, it becomes possible to connect the wiring to the back surface of the bare IC chip 1 like the wiring pattern 4a, and the wiring can be connected to the power supply voltage Vcc or By connecting to the ground, the potential of the back surface of the bare IC chip 1 can be fixed, and the electrical characteristics of the element can be stabilized.
【００２４】 また、ベアＩＣチップ１のボンディングパッド２ａ，２ｂのように互いに電気 的に接続すべきボンディングパッドが離れた位置に配置されている場合でも、配 線をダイボンディング領域を通って引き回すことにより最短距離で接続すること ができる。In addition, even if the bonding pads to be electrically connected to each other, such as the bonding pads 2a and 2b of the bare IC chip 1, are arranged at distant positions, the wiring should be routed through the die bonding region. Allows you to connect at the shortest distance.
【００２５】 また、ベアＩＣチップ１上のボンディングパッドの位置が、２ｃのように通常 の配線パタ−ンの引き回しでは所望の配線パタ−ンに接続することが困難な位置 にある場合でも、ダイボンディング領域を通って配線を引き回すことにより容易 に接続することができる。Further, even when the position of the bonding pad on the bare IC chip 1 is in a position where it is difficult to connect to a desired wiring pattern by routing a normal wiring pattern like 2c, the die It can be easily connected by routing the wiring through the bonding area.
【００２６】 図３は、本考案の別の実施例による回路素子基板の配線パタ−ンを示し、絶縁 基板５上に配線パターン４が形成されており、破線は絶縁体層６の形成予定領域 を示す。この実施例によれば、ベアＩＣチップの下を通り配線パタ−ンを通過さ せることによって、例えば、該ベアＩＣチップをはさんで両側に位置する回路間 の接続をも含む配線も容易に行なうことができる。FIG. 3 shows a wiring pattern of a circuit element substrate according to another embodiment of the present invention, in which a wiring pattern 4 is formed on an insulating substrate 5 and a broken line indicates a region where an insulating layer 6 is to be formed. Indicates. According to this embodiment, by passing the wiring pattern under the bare IC chip, for example, the wiring including the connection between the circuits located on both sides of the bare IC chip can be easily carried out. Can be done.
【００２７】 なお本実施例では、ダイボンディング領域に配線パタ−ンを単層で形成してい るが、配線層を絶縁体層と複数積層することにより多層配線を形成して、その上 に回路素子をダイボンディングしてもよい。In this embodiment, the wiring pattern is formed in a single layer in the die bonding region, but a multilayer wiring is formed by laminating a plurality of wiring layers with an insulating layer, and a circuit is formed on the multilayer wiring. The element may be die-bonded.
【００２８】 また回路素子を配線パターンに電気的に接続し回路を形成する方法はワイヤボ ンディングではなく、バンプによって接続してもよい。Further, the method of electrically connecting the circuit element to the wiring pattern to form the circuit may be connected by bumps instead of wire bonding.
【００２９】[0029]
以上のように、本考案によれば、ベアＩＣチップ等の回路素子を配線基板に直 接実装して電子回路を構成したＣＯＢ等の回路基板装置において、回路素子のダ イボンディング領域にも配線パターンを形成することにより、回路素子相互を効 率よく接続するための配線の引き回しが可能となり、高密度配線が可能になるの で、回路素子の集積度を高め、回路基板装置を小型化することができる。 As described above, according to the present invention, in a circuit board device such as a COB in which a circuit element such as a bare IC chip is directly mounted on a wiring board to form an electronic circuit, wiring is also performed in a die bonding area of the circuit element. By forming a pattern, it is possible to route the wiring to efficiently connect the circuit elements to each other, and high-density wiring is possible, so that the degree of integration of the circuit elements is increased and the circuit board device is downsized. be able to.
【００３０】 また、配線の長さを短縮することができるので、配線抵抗や容量を減少させて 回路基板装置の性能を大幅に高めることができる。Further, since the length of the wiring can be shortened, the wiring resistance and the capacitance can be reduced and the performance of the circuit board device can be significantly improved.
【００３１】 また、ダイボンディング領域に形成した配線パターンを回路素子裏面に接続し 、その配線により電源電圧Ｖｃｃやグランドを回路素子裏面に接続することがで きるので、回路素子の電位を固定し、電気的特性を安定させ、外部からの雑音の 影響を低減することができる。Further, since the wiring pattern formed in the die bonding region can be connected to the back surface of the circuit element and the wiring can connect the power supply voltage Vcc and the ground to the back surface of the circuit element, the potential of the circuit element is fixed, It is possible to stabilize the electrical characteristics and reduce the influence of external noise.
【図１】本考案の一実施例に係る回路基板装置の構成を
概略的に示す説明図である。FIG. 1 is an explanatory view schematically showing a configuration of a circuit board device according to an embodiment of the present invention.
【図２】図１の回路基板装置のＡ−Ａ′線に沿った断面
図である。FIG. 2 is a cross-sectional view taken along the line AA ′ of the circuit board device of FIG.
【図３】本考案の別の実施例による回路基板装置の配線
パターンを概略的に示す説明図である。FIG. 3 is an explanatory view schematically showing a wiring pattern of a circuit board device according to another embodiment of the present invention.
１ ベアＩＣチップ ２ ボンディングパッド ２ａ〜２ｃ ボンディングパッド ３ ボンディングワイヤ ４ 配線パターン ４ａ〜４ｅ 配線パターン ５ 絶縁基板 ６ 絶縁体層 ７ 導電ペースト ８ チップコート樹脂 1 Bare IC Chip 2 Bonding Pads 2a to 2c Bonding Pad 3 Bonding Wire 4 Wiring Pattern 4a to 4e Wiring Pattern 5 Insulating Substrate 6 Insulator Layer 7 Conductive Paste 8 Chip Coat Resin
Claims (1)
プ回路素子を直接ダイボンディングし、前記チップ回路
素子の電極と前記配線パターンを接続して電子回路を構
成した回路基板装置において、 前記配線パターンが前記チップ回路素子のダイボンディ
ング領域にも形成されており、該ダイボンディング領域
に形成された配線パターンの少なくとも一部分と前記チ
ップ回路素子との間には絶縁層が形成されていることを
特徴とする回路基板装置。1. A circuit board device in which a chip circuit element is directly die-bonded to a wiring board on which a wiring pattern is formed, and an electrode of the chip circuit element is connected to the wiring pattern to form an electronic circuit. It is also formed in a die bonding area of the chip circuit element, and an insulating layer is formed between at least a part of the wiring pattern formed in the die bonding area and the chip circuit element. Circuit board device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP016062U JPH0670243U (en) | 1993-03-09 | 1993-03-09 | Circuit board device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP016062U JPH0670243U (en) | 1993-03-09 | 1993-03-09 | Circuit board device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0670243U true JPH0670243U (en) | 1994-09-30 |
Family
ID=11906096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP016062U Pending JPH0670243U (en) | 1993-03-09 | 1993-03-09 | Circuit board device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0670243U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007208276A (en) * | 2007-03-08 | 2007-08-16 | Texas Instr Japan Ltd | Semiconductor device and its manufacturing method |
-
1993
- 1993-03-09 JP JP016062U patent/JPH0670243U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007208276A (en) * | 2007-03-08 | 2007-08-16 | Texas Instr Japan Ltd | Semiconductor device and its manufacturing method |
| JP4484891B2 (en) * | 2007-03-08 | 2010-06-16 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor device and manufacturing method thereof |
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