JPH06291165A - Flip chip connecting construction - Google Patents
Flip chip connecting constructionInfo
- Publication number
- JPH06291165A JPH06291165A JP5075922A JP7592293A JPH06291165A JP H06291165 A JPH06291165 A JP H06291165A JP 5075922 A JP5075922 A JP 5075922A JP 7592293 A JP7592293 A JP 7592293A JP H06291165 A JPH06291165 A JP H06291165A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- insulating film
- multilayer wiring
- wiring board
- electrode pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子のフリップチ
ップ接続構造に関し、多層配線基板と接続するはんだボ
ールの多段構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip connection structure for semiconductor devices, and more particularly to a multi-stage structure of solder balls connected to a multilayer wiring board.
【０００２】[0002]
【従来の技術】従来のフリップチップ接続構造は、夫々
に設けた相互接続用電極パッドの少なくとも一方にはん
だ揚げまたは印刷等の手法ではんだを付着しておき、こ
れにより予め所謂はんだのタマリを形成しておいて、し
かる後両者を重ね合わせて熱処理することによって形成
している。図４に代表的な従来例を示す。半導体素子１
の表面周辺部とこれに対向する多層配線基板１３の表面
にそれぞれ電極パット２と１０を形成し、これらを接続
用はんだボール４を用いて接着する。かかる接続構造に
おいては、半導体素子を多層配線基板との熱膨張差によ
り、はんだ接続部に熱ストレスがかかり、半導体素子が
大型化するに従い、また、多層配線基板の樹脂基材化が
進むに従い、はんだ接続部の疲労による破壊が発生する
という欠点を生じていた。そこで図５に示す接続構造等
も発案されている。半導体素子１と多層配線基板１３の
表面の間に、スルーホール７により電気的に導通を表裏
面に持つ絶縁フィルム６を介在させ、半導体素子１の表
面周辺部とこれに対向する多層配線基板１３の表面の電
極パッド１０をこれらと同一軸上に位置する様に形成さ
れた前記スルーホール部７に設けた電極パッドを介して
はんだボール４により接着される。絶縁フィルム６は少
なくとも数枚以上重ね合わされ、半導体素子と多層配線
基板間の熱膨張差による熱ストレスをこの絶縁フィルム
と複数のはんだボールにより吸収緩和するものである。2. Description of the Related Art In the conventional flip chip connection structure, solder is attached to at least one of the interconnecting electrode pads provided for each by a method such as soldering or printing, thereby forming a so-called solder summary in advance. After that, the two are superposed and heat-treated. FIG. 4 shows a typical conventional example. Semiconductor element 1
The electrode pads 2 and 10 are formed on the peripheral portion of the surface of and the surface of the multilayer wiring substrate 13 facing the peripheral portion, and these are bonded by using the solder balls 4 for connection. In such a connection structure, due to the difference in thermal expansion between the semiconductor element and the multilayer wiring board, thermal stress is applied to the solder connection portion, and as the semiconductor element increases in size, and as the resin material of the multilayer wiring board progresses, There has been a drawback in that the solder joint is broken due to fatigue. Therefore, a connection structure and the like shown in FIG. 5 has also been proposed. An insulating film 6 having electrical conduction on the front and back sides through a through hole 7 is interposed between the semiconductor element 1 and the front surface of the multilayer wiring board 13, and a peripheral portion of the surface of the semiconductor element 1 and the multilayer wiring board 13 facing the peripheral portion. The electrode pads 10 on the surface of the are bonded by the solder balls 4 via the electrode pads provided in the through holes 7 formed so as to be positioned on the same axis as these. At least several sheets of the insulating film 6 are stacked, and the thermal stress due to the difference in thermal expansion between the semiconductor element and the multilayer wiring board is absorbed and relaxed by the insulating film and the plurality of solder balls.
【０００３】[0003]
【発明が解決しようとする課題】この従来のフリップチ
ップ接続構造では、半導体素子と多層配線基板の間の熱
膨張差による熱ストレスを吸収するために、幾重もの絶
縁フィルムを介して多段にはんだボールを重ねているた
め、コスト、生産性、歩留りを悪くしていた。絶縁フィ
ルムにかかる資材費は言うに及ばず、多段に絶縁フィル
ムを重ねるには、幾重にも積み上げられたはんだボール
の中心軸を合わせるための位置決め精度、はんだボール
の形成を絶縁フィルムの上部層、下部層で均等にするた
めの困難性がある。予めアライメントを合せておいても
同時に同じ温度プロファイルで行うには、絶縁フィルム
の下層になればなる程重力の影響が働きはんだボールを
つぶし易くなる。本来、はんだボールははんだペースト
印刷等によるタマリを形成した後、熱処理により溶融形
成される。溶融時、はんだボールはセルフアライメント
能力を有しており、自ら位置決めするが、絶縁フィルム
の反り、はんだタマリの量によりはんだボールを各々均
等に形成するのは難しい。また、はんだボールを絶縁フ
ィルムを介しているとはいえ、幾段にも重ねていること
より熱ストレス的には大きな緩衝効果はなく、絶縁フィ
ルムの弾性にたよるのみである。In this conventional flip-chip connection structure, in order to absorb the thermal stress due to the difference in thermal expansion between the semiconductor element and the multilayer wiring board, the solder balls are arranged in multiple stages via multiple insulating films. Therefore, cost, productivity, and yield were deteriorated. Not to mention the material cost of the insulating film, in order to stack the insulating films in multiple stages, the positioning accuracy for aligning the central axes of the solder balls stacked in multiple layers, the formation of solder balls in the upper layer of the insulating film, There is a difficulty to even out in the lower layers. In order to perform the same temperature profile at the same time even if alignment is performed in advance, the lower the insulating film is, the more the influence of gravity acts and the solder balls are easily crushed. Originally, a solder ball is melted and formed by heat treatment after forming a summary by solder paste printing or the like. At the time of melting, the solder balls have a self-alignment capability and position themselves, but it is difficult to form the solder balls evenly due to the amount of warpage of the insulating film and the amount of solder tamari. Further, although the solder balls are interposed through the insulating film, there is no great buffering effect in terms of heat stress due to the fact that the solder balls are stacked in multiple layers, and only relying on the elasticity of the insulating film.
【０００４】[0004]
【課題を解決するための手段】本発明のフリップチップ
接続構造はスルーホールにより電気的導通を表裏面に持
ち、表裏面にスルーホールと電気的に導通され、且つ表
裏面において対向しない位置に設けた電極パッドを有す
る、少なくとも一枚以上の絶縁フィルムを前記半導体素
子表面と多層配線基板表面の間に介在させ、前記半導体
素子と多層配線基板の電極パッドを絶縁フィルム表裏面
の電極パッドを経由して、はんだボールにより接着かつ
電気接続させる。The flip-chip connection structure of the present invention has electrical conduction on the front and back sides by through holes, is electrically conducted to the through holes on the front and back sides, and is provided at positions not facing each other on the front and back sides. At least one insulating film having an electrode pad is interposed between the semiconductor element surface and the surface of the multilayer wiring board, and the electrode pads of the semiconductor element and the multilayer wiring board are routed through the electrode pads on the front and back surfaces of the insulating film. Then, they are bonded and electrically connected by solder balls.
【０００５】[0005]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）、図２（拡大断面図）は本発明の一実施
例のフリップチップ接続構造の断面図である。図１
（ｂ）は絶縁フィルムの平面図である。厚さ数十マイク
ロメートルから数百マイクロメートルに成る耐熱性ある
樹脂、例えば、ポリイミドの絶縁フィルム６を所望の位
置にスルーホール７をパンチングにより形成しておき、
次に絶縁フィルム６の表裏面にＡｌ，Ｎｉ，Ｃｕ等の金
属を蒸着または無電界メッキ等により電極パッド５と
３、パッド引き出し線８を形成する。一方半導体素子１
と多層配線基板１３または、絶縁フィルム同士間の間隔
を所定の値にするために、数マイクロメートルから数百
マイクロメートルの厚さを持ちＡｌ，ＡｌＮまたはＳｉ
Ｃから成る金属、セラミック等からなるスタンドオフ１
１をパンチまたはプレスにより形成し、両面にポリイミ
ド等の耐熱性接着剤１２を塗布しておく。印刷またはプ
リフオームしたはんだを絶縁フィルム上または半導体素
子、多層配線基板表面の電極パッド上に予め、タマリと
して形成しておき、半導体素子と絶縁フィルムと多層配
線基板とを重ね合せ、必要に応じて半導体素子の裏面上
部より荷重を掛けながら熱処理を施す。電極パッド上の
はんだは溶け、はんだボール４と９が形成される。半導
体素子と多層配線基板の相互電極パッドは絶縁フィルム
の配線電極パッドを介して接着及び電気的接続される。The present invention will be described below with reference to the drawings. FIG. 1A and FIG. 2 (enlarged sectional view) are sectional views of a flip-chip connection structure according to an embodiment of the present invention. Figure 1
(B) is a top view of an insulating film. A heat-resistant resin having a thickness of several tens of micrometers to several hundreds of micrometers, for example, an insulating film 6 of polyimide is formed at a desired position through holes 7 by punching,
Next, metal such as Al, Ni, and Cu is vapor-deposited or electroless plated on the front and back surfaces of the insulating film 6 to form the electrode pads 5 and 3, and the pad lead wire 8. On the other hand, semiconductor device 1
And a multi-layer wiring substrate 13 or Al, AlN or Si having a thickness of several micrometers to several hundreds of micrometers in order to set the distance between the insulating films to a predetermined value.
Standoff 1 made of C metal, ceramic, etc.
1 is formed by punching or pressing, and a heat resistant adhesive 12 such as polyimide is applied to both surfaces. Printed or preformed solder is formed on the insulating film or the semiconductor element or electrode pad on the surface of the multilayer wiring board in advance as a summary, and the semiconductor element, the insulating film, and the multilayer wiring board are superposed, and the semiconductor is formed if necessary. Heat treatment is applied from above the back surface of the device while applying a load. The solder on the electrode pads melts and solder balls 4 and 9 are formed. The mutual electrode pads of the semiconductor element and the multilayer wiring board are bonded and electrically connected via the wiring electrode pads of the insulating film.
【０００６】半導体素子表面周辺部に設けた電極パッド
２と絶縁フィルム６表面９の電極パッド５は対向する位
置に設けておく。絶縁フィルム裏面の電極パッド３は、
引き出し線８により内部へ配置され、表面を対向する位
置からずれる。このずれ量は、絶縁フィルムの厚さ、弾
性に加え、半導体素子の大きさ、半導体素子と多層配線
基板との熱膨張差の大きさにより決定される。はんだボ
ールに発生する応力が大きい場合程、ずれ量は大きくと
る必要がある。ずれ量は絶縁フィルム厚の約２倍以上あ
ることが好ましい。多層配線基板表面の電極パッドは、
絶縁フィルム裏面の電極パッドと対向するように位置し
ている。The electrode pad 2 provided on the peripheral portion of the surface of the semiconductor element and the electrode pad 5 on the surface 9 of the insulating film 6 are provided so as to face each other. The electrode pad 3 on the back surface of the insulating film is
It is arranged inside by the lead wire 8 and is displaced from the position where the surfaces are opposed to each other. This shift amount is determined by the thickness of the insulating film, elasticity, the size of the semiconductor element, and the difference in thermal expansion between the semiconductor element and the multilayer wiring board. The greater the stress generated in the solder ball, the greater the amount of displacement must be. The amount of deviation is preferably about twice or more the thickness of the insulating film. The electrode pads on the surface of the multilayer wiring board are
It is located so as to face the electrode pad on the back surface of the insulating film.
【０００７】半導体素子の電極パッドに対し、多層配線
基板の電極パッドの位置を内側に位置させるのは、Ｓｉ
から成る半導体素子に比べ多層配線基板がＡｌ2 Ｏ3 、
ガラスエポキシまたはポリイミド基材から成り、膨張率
が２倍から１０倍程大きいためで、はんだ接続後の基板
収縮は半導体素子の２倍から１０倍程になり、はんだボ
ール接続部に大きな熱ストレスを与えることになる。よ
って基板側のはんだボール接続領域を少しでも小さくす
ることで、基板側の収縮量を低減することができる。The position of the electrode pad of the multi-layer wiring substrate is located inside the electrode pad of the semiconductor element is Si.
Multilayer wiring substrate as compared to a semiconductor device composed of the Al 2 O 3,
It is made of glass epoxy or polyimide base material, and its expansion coefficient is about 2 to 10 times larger. Therefore, the shrinkage of the board after soldering is about 2 to 10 times that of the semiconductor element, and a large thermal stress is applied to the solder ball connection part. Will be given. Therefore, the shrinkage amount on the substrate side can be reduced by making the solder ball connection region on the substrate side as small as possible.
【０００８】他の実施例の断面図を図３に示す。多層配
線基板１３表面の電極パッドは格子上に配列され、絶縁
フィルム６の裏面上の電極パッドも引き出し線により、
多層配線基板表面の電極パッド１０と対向する位置に格
子上に配列されている。したがって絶縁フィルム６と多
層配線基板１３とは多数のはんだボール９で接続され、
絶縁フィルム６と半導体素子１とは先の実施例と同じ接
続構造にて接続される。A cross-sectional view of another embodiment is shown in FIG. The electrode pads on the front surface of the multilayer wiring board 13 are arranged in a grid, and the electrode pads on the back surface of the insulating film 6 are also connected by lead lines
They are arranged on a grid at positions facing the electrode pads 10 on the surface of the multilayer wiring board. Therefore, the insulating film 6 and the multilayer wiring board 13 are connected by a large number of solder balls 9.
The insulating film 6 and the semiconductor element 1 are connected by the same connection structure as in the previous embodiment.
【０００９】この実施例の場合、多層配線基板側のはん
だボール９の領域を半導体素子１の周辺に設けられた電
極パッド２の領域よりも小さくすることが可能で、半導
体素子１と多層絶縁基板１３の熱膨張差を小さくするこ
とができ、はんだボール部への熱ストレスを小さくする
効果がある。In the case of this embodiment, the area of the solder ball 9 on the multilayer wiring board side can be made smaller than the area of the electrode pad 2 provided around the semiconductor element 1, and the semiconductor element 1 and the multilayer insulating substrate. The difference in thermal expansion of No. 13 can be reduced, and the thermal stress on the solder ball portion can be reduced.
【００１０】[0010]
【発明の効果】以上説明したように、本発明は、半導体
素子と多層配線基板の間に表裏面の電極パッドが対向し
ない様にずらして配置された絶縁シートを介在したこと
で半導体素子と基板の間に生じる熱膨張差による熱スト
レスを絶縁フィルムに吸収させることができ、はんだボ
ール部への直接的な熱ストルスを半分から数％にまで低
減することが可能となる。As described above, according to the present invention, the semiconductor element and the substrate are provided by interposing the insulating sheets which are arranged so as not to face the electrode pads on the front and back surfaces between the semiconductor element and the multilayer wiring board. The insulating film can absorb the thermal stress caused by the difference in thermal expansion between the two, and the thermal stress directly applied to the solder ball portion can be reduced from half to several percent.
【００１１】従来例にも絶縁フィルムを介在させるもの
はあったが、従来例ははんだボールをフィルムの表裏面
で対向し、同一軸上に位置していたため、半導体素子と
多層配線基板の熱膨張差から来る熱ストレスを吸収する
には、幾段にも絶縁フィルム及びはんだボールを重ねる
必要があった。しかし、本発明によれば、数十ｍｍ角の
半導体素子をＡｌ2 Ｏ3 等の多層配線基板に一枚の絶縁
フィルムを介しただけで、はんだボールの疲労破壊を防
ぐことが可能となるように、一枚の絶縁フィルムを介在
させるだけで、はんだボール部に発生する熱ストレスを
大幅に低減することが可能となる。Although there is a conventional example in which an insulating film is interposed, in the conventional example, since the solder balls face each other on the front and back surfaces of the film and are located on the same axis, the thermal expansion of the semiconductor element and the multilayer wiring board is caused. In order to absorb the thermal stress caused by the difference, it was necessary to stack the insulating film and the solder balls in multiple stages. However, according to the present invention, it is possible to prevent a fatigue breakdown of a solder ball by simply placing a semiconductor element having a size of several tens of mm on a multilayer wiring board such as Al 2 O 3 with one insulating film interposed. In addition, it is possible to greatly reduce the thermal stress generated in the solder ball portion by interposing only one insulating film.
【図１】図１（ａ）は本発明の一実施例の断面図、
（ｂ）は構成部材である絶縁フィルムの平面図。FIG. 1A is a sectional view of an embodiment of the present invention,
(B) is a top view of the insulating film which is a structural member.
【図２】図１（ａ）の拡大図。FIG. 2 is an enlarged view of FIG.
【図３】他の一実施例の断面図。FIG. 3 is a sectional view of another embodiment.
【図４】従来例の断面図。FIG. 4 is a sectional view of a conventional example.
【図５】従来例の断面図。FIG. 5 is a sectional view of a conventional example.
１ 半導体素子 ２ 素子上の電極パッド ３，５ 絶縁フィルム上の電極パッド ４，９ はんだボール ６ 絶縁フィルム ７ スルーホール ８ 引き出し線 １０ 基板表面の電極パッド １１ スタンドオフ １２ 接着剤 １３ 多層配線基板 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Electrode pad on element 3,5 Electrode pad on insulating film 4,9 Solder ball 6 Insulating film 7 Through hole 8 Lead wire 10 Electrode pad on board surface 11 Standoff 12 Adhesive 13 Multilayer wiring board
Claims (3)
多層配線基板表面の電極パッドとをはんだボールにより
接続するフリップチップ接続構造において、スルーホー
ルにより電気的導通を表裏面に持ち、表裏面にスルーホ
ールと電気的に導通され、かつ、表裏面において対向し
ない位置に設けた電極パッドを有する、少なくとも一枚
以上の絶縁フィルムを前記半導体素子表面と多層配線基
板表面の間に介在させ、前記半導体素子と多層配線基板
の電極パッドとを絶縁フィルム表裏面の電極パッドを経
由して、はんだボールにより接着かつ電気接続したこと
を特徴とするフリップチップ接続構造。1. In a flip-chip connection structure in which an electrode pad provided on the surface of a semiconductor device and an electrode pad on the surface of a multilayer wiring board are connected by solder balls, electrical conduction is provided on the front and back surfaces by through holes, and front and back surfaces are provided. At least one insulating film, which is electrically connected to the through hole and has electrode pads provided at positions not facing each other on the front and back surfaces, is interposed between the semiconductor element surface and the multilayer wiring board surface, A flip chip connection structure characterized in that a semiconductor element and an electrode pad of a multilayer wiring board are bonded and electrically connected by solder balls via electrode pads on the front and back surfaces of an insulating film.
体素子表面の電極パッドの少なくとも一部の位置が内周
側に位置することを特徴とする請求項１記載のフリップ
チップ接続構造。2. The flip chip connection structure according to claim 1, wherein at least a part of the electrode pad on the surface of the multilayer wiring board is located on the inner peripheral side.
タンドオフを絶縁フィルムの表裏面に対向しない位置に
設けたことを特徴とする請求項１記載のフリップチップ
接続構造。3. The flip chip connection structure according to claim 1, wherein standoffs having good heat conductivity and having no electrical connection are provided at positions not facing the front and back surfaces of the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5075922A JPH06291165A (en) | 1993-04-01 | 1993-04-01 | Flip chip connecting construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5075922A JPH06291165A (en) | 1993-04-01 | 1993-04-01 | Flip chip connecting construction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06291165A true JPH06291165A (en) | 1994-10-18 |
Family
ID=13590288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5075922A Pending JPH06291165A (en) | 1993-04-01 | 1993-04-01 | Flip chip connecting construction |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06291165A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183333A (en) * | 1993-11-16 | 1995-07-21 | Internatl Business Mach Corp <Ibm> | Electronic package and manufacture thereof |
| US5859407A (en) * | 1996-07-17 | 1999-01-12 | Ngk Spark Plug Co., Ltd. | Connecting board for connection between base plate and mounting board |
| EP0827191A3 (en) * | 1996-08-20 | 1999-12-29 | Nec Corporation | Semiconductor device mounting structure |
| US6069407A (en) * | 1998-11-18 | 2000-05-30 | Vlsi Technology, Inc. | BGA package using PCB and tape in a die-up configuration |
| US6080936A (en) * | 1996-04-26 | 2000-06-27 | Ngk Spark Plug Co., Ltd. | Connecting board with oval-shaped protrusions |
| KR100339178B1 (en) * | 1998-04-28 | 2002-05-31 | 포만 제프리 엘 | Methods and apparatus for balancing differences in thermal expansion in electronic packaging |
| WO2002030166A3 (en) * | 2000-10-04 | 2002-06-13 | Honeywell Int Inc | Compliant attachment interface |
| US6492715B1 (en) | 2000-09-13 | 2002-12-10 | International Business Machines Corporation | Integrated semiconductor package |
| US6816385B1 (en) | 2000-11-16 | 2004-11-09 | International Business Machines Corporation | Compliant laminate connector |
| WO2017112135A1 (en) * | 2015-12-21 | 2017-06-29 | Intel Corporation | Warpage mitigation in printed circuit board assemblies |
| US10260961B2 (en) | 2015-12-21 | 2019-04-16 | Intel Corporation | Integrated circuit packages with temperature sensor traces |
| US10880994B2 (en) | 2016-06-02 | 2020-12-29 | Intel Corporation | Top-side connector interface for processor packaging |
-
1993
- 1993-04-01 JP JP5075922A patent/JPH06291165A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183333A (en) * | 1993-11-16 | 1995-07-21 | Internatl Business Mach Corp <Ibm> | Electronic package and manufacture thereof |
| US6080936A (en) * | 1996-04-26 | 2000-06-27 | Ngk Spark Plug Co., Ltd. | Connecting board with oval-shaped protrusions |
| US6148900A (en) * | 1996-04-26 | 2000-11-21 | Ngk Spark Plug Co., Ltd. | Connecting board for connection between base plate and mounting board |
| US5859407A (en) * | 1996-07-17 | 1999-01-12 | Ngk Spark Plug Co., Ltd. | Connecting board for connection between base plate and mounting board |
| EP0827191A3 (en) * | 1996-08-20 | 1999-12-29 | Nec Corporation | Semiconductor device mounting structure |
| US6016013A (en) * | 1996-08-20 | 2000-01-18 | Nec Corporation | Semiconductor device mounting structure |
| KR100339178B1 (en) * | 1998-04-28 | 2002-05-31 | 포만 제프리 엘 | Methods and apparatus for balancing differences in thermal expansion in electronic packaging |
| US6069407A (en) * | 1998-11-18 | 2000-05-30 | Vlsi Technology, Inc. | BGA package using PCB and tape in a die-up configuration |
| US6468834B1 (en) * | 1998-11-18 | 2002-10-22 | Ahmad Hamzehdoost | Method of fabricating a BGA package using PCB and tape in a die-up configuration |
| US6492715B1 (en) | 2000-09-13 | 2002-12-10 | International Business Machines Corporation | Integrated semiconductor package |
| WO2002030166A3 (en) * | 2000-10-04 | 2002-06-13 | Honeywell Int Inc | Compliant attachment interface |
| US6816385B1 (en) | 2000-11-16 | 2004-11-09 | International Business Machines Corporation | Compliant laminate connector |
| WO2017112135A1 (en) * | 2015-12-21 | 2017-06-29 | Intel Corporation | Warpage mitigation in printed circuit board assemblies |
| US10178763B2 (en) | 2015-12-21 | 2019-01-08 | Intel Corporation | Warpage mitigation in printed circuit board assemblies |
| US10260961B2 (en) | 2015-12-21 | 2019-04-16 | Intel Corporation | Integrated circuit packages with temperature sensor traces |
| US10880994B2 (en) | 2016-06-02 | 2020-12-29 | Intel Corporation | Top-side connector interface for processor packaging |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6297141B1 (en) | Mounting assembly of integrated circuit device and method for production thereof | |
| JP2533511B2 (en) | Electronic component connection structure and manufacturing method thereof | |
| US6016013A (en) | Semiconductor device mounting structure | |
| US5569960A (en) | Electronic component, electronic component assembly and electronic component unit | |
| JP3838331B2 (en) | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus | |
| JP6489965B2 (en) | Electronic component device and manufacturing method thereof | |
| JPH09199635A (en) | Multilayer film for forming circuit substrate, multilayer circuit substrate using it, and package for semiconductor device | |
| JP2000100987A (en) | Semiconductor chip module multilayer circuit board and manufacture thereof | |
| JPH06291165A (en) | Flip chip connecting construction | |
| JP2006114604A (en) | Semiconductor device and assembly method thereof | |
| JPH1174312A (en) | Semiconductor device and method for forming solder bump | |
| JP2000068328A (en) | Wiring board for flip-chip mounting | |
| JP6639934B2 (en) | Wiring board, semiconductor device, and method of manufacturing wiring board | |
| JP4521984B2 (en) | Multilayer semiconductor device and mounting substrate | |
| US7804179B2 (en) | Plastic ball grid array ruggedization | |
| JP3549316B2 (en) | Wiring board | |
| JP2847949B2 (en) | Semiconductor device | |
| JPH10256428A (en) | Semiconductor package | |
| JP3783754B2 (en) | Insulating substrate, semiconductor device, and semiconductor mounting device | |
| JP4342577B2 (en) | Semiconductor chip mounting structure | |
| JPH11274372A (en) | Semiconductor device and its semiconductor package | |
| JPH11204565A (en) | Semiconductor device | |
| JPH11307718A (en) | Three dimensional package and its manufacture | |
| JP2915186B2 (en) | Semiconductor device mounting structure and mounting method | |
| JPH0644583B2 (en) | Board-to-board connection terminal and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19991214 |