JPH06232210A - Semiconductor device, and method for preventing deformation of chip - Google Patents

Abstract

PURPOSE:To provide a highly reliable semiconductor device having a superior thermal cycle characteristic, and to provide a method for preventing the deformation of a chip to obtain such a semiconductor device. CONSTITUTION:A semiconductor device is provided with a mounting board 3, and a semiconductor chip 1 which is electrically connected to the board 3 via bump electrodes 2. A polyimide film 5A is sandwiched between the chip 1 and the board 3, and the chip 1 and the board 3 are adhered to each other. An adjusting plate 7A is disposed on the top of the chip 1, whereby the flexure and deformation of the chip 1 is adjusted. With this construction, the chip 1 and the board 3 are bonded to each other by the film 5A, and hence the expansion and contraction of the board 3 induces the flexure and deformation of the chip 1. For this reason, the concentration of stress on the bump electrode 2 is suppressed, and a thermal cycle characteristic is improved. The adjusting plate 7 disposed on the chip 1 simultaneously makes it possible to solve the problem of the cracking of the chip 1 caused by the flexure and deformation of the chip 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a semiconductor device mounted on a mounting substrate.

[0002]

2. Description of the Related Art Conventionally, there is a flip-chip type semiconductor device as a semiconductor device used for a product having a large number of pins.
FIG. 9 shows a flip-chip type semiconductor device.
(A) is a cross-sectional view of an ideal product, and (b) is a cross-sectional view of an actual product.

As shown in FIG. 9A, the semiconductor chip 1
The bump electrode 2 is provided on the surface of the. The bump electrode 2 is connected to the wiring pattern 4 formed on the mounting substrate 3 by soldering.

The material forming the chip 1 and the material forming the substrate 3 are different from each other, and there is a difference in the coefficient of linear expansion between them. For example, if the coefficient of linear expansion of the substrate 3 is larger than that of the chip 1, the substrate 3 shrinks greatly when the device is returned to room temperature after the mounting process is completed, and the bump electrode 2 is formed in a shape as shown in FIG. 9B. Distorted.

After the product is commercialized, the chip 1 generates heat each time it is operated. Therefore, the tip 1 expands /
Repeat contraction. The application of such a heat cycle causes the bump electrode 2 to be repeatedly distorted, and eventually causes fatigue and becomes fragile. Therefore, the reliability of the semiconductor device is deteriorated.

[0006]

As described above, the conventional semiconductor device has a structure in which the chip 1 is supported on the substrate 3 only by the bump electrodes 2, and the bump electrodes 2 are not affected by the stress due to the difference in linear expansion coefficient. I will receive it directly. As a result, stress concentrates on the bump electrodes 2, and fatigue (thermal fatigue) caused by thermal cycles is particularly likely to occur.

The present invention has been made in view of the above points, and an object thereof is a semiconductor device having good thermal cycle characteristics and high reliability, and a chip deformation for obtaining such a semiconductor device. It is to provide a prevention method.

[0008]

A semiconductor device according to the present invention includes a semiconductor chip flip-chip connected on a mounting substrate via a conductive electrode, and a semiconductor chip other than the conductive electrode between the chip and the mounting substrate. It is characterized in that it is provided with a fixing means for fixing the provided chip and the mounting substrate, and an adjusting means for adjusting the bending of the chip.

Further, in the chip deformation preventing method according to the present invention, a fixing means for fixing the chip and the mounting substrate is provided between the chip and the mounting substrate in addition to the conductive electrodes, so that the chip is expanded and contracted in accordance with the expansion and contraction of the mounting substrate. It is characterized in that the chip is deformed and the chip is prevented from being deformed by providing adjusting means for adjusting the bending of the chip so as to cancel the bending due to the fixing means.

[0010]

According to the semiconductor device and the chip deformation preventing method having the above-described configurations, the chip is bent and deformed in accordance with the expansion and contraction of the mounting substrate by the fixing means provided between the chip and the mounting substrate. It is possible to disperse the stress caused by the stress not only to the conductive electrode but also to the chip itself. Therefore, stress is not concentrated on the conductive electrode, and the conductive electrode has a structure in which thermal fatigue does not easily occur. further,
When the chip bends and deforms, the chip may crack. In order to improve this point, adjusting means for adjusting the bending deformation of the chip is provided on the chip to correct the bending of the chip,
Or try to ease it.

[0011]

EXAMPLES The present invention will be described below with reference to examples. In this description, common parts are denoted by common reference symbols throughout the drawings, and redundant description will be avoided.
1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

As shown in FIG. 1, bump electrodes 2 are provided on the surface of the semiconductor chip 1. The bump electrode 2 is connected to the wiring pattern 4 formed on the mounting substrate 3 by soldering. The substrate 3 is made of alumina. A polyimide film 5A is sandwiched between the surface of the chip 1 and the substrate 3. Adhesives are attached to the front surface and the back surface of the polyimide film 5A, and the front surface and the back surface are bonded to the chip 1 and the substrate 3, respectively. As a result, the chip 1 and the substrate 3 are fixed to each other. A control plate 7A is attached to the back surface of the chip 1 via an adhesive layer 6 made of an insulating and low elastic modulus adhesive. In this embodiment, the heat dissipation of the chip 1 is also taken into consideration by using a copper plate for the adjusting plate 7A. When the substrate 3 is made of alumina and the adjusting plate 7A is made of copper, the film thickness of the adjusting plate 7A is made thinner than that of the substrate 3 due to the linear expansion coefficient.

Next, a method of adjusting the bending deformation of the chip by the adjusting plate will be described. This adjusting method includes a substrate 3, an adhesive layer 5 (corresponding to the polyimide film 5A in FIG. 1),
It is performed by applying a calculation formula based on material mechanics on the assumption that a portion composed of the chip 1, the adhesive layer 6 and the adjusting plate 7 is a multi-layer composite “beam”. Prior to the description of the adjusting method, the thermal stress of the multilayer composite beam model will be described with reference to FIG. FIG. 2 is a diagram schematically showing a multilayer composite beam. The stress of the i-th layer of the multilayer composite beam as shown in FIG. 2 can be expressed by the following equation.

[0014]

[Equation 1]

In the above equation, σ _i is the stress of the i-th layer, ε _i
The i layer of the thermal strain, (t-δ) / ρ the coordinates between the first distortion by bending of the i layer, t is t _{i + 1} ~t _i, [delta] is the neutral line coordinates,
ρ is the radius of curvature, and E _i is the Young's modulus of the i-th layer. Here, the thermal strain of the i-th layer is expressed by the following equation.

[0016]

[Equation 2]

When the coordinates δ of the neutral line and the radius of curvature ρ are δ = B / A and ρ = C / A, respectively, A = -6 [ΣE _j ε _j (t _{j + 1} −t _j ) · ΣE _j (T _{j + 1} ² -T _j ² ) −ΣE _j ε _j (t _{j + 1} ² -T _j ² ) · ΣE _j (t _{j + 1} −t _j )] B = −4ΣE _j ε _j (t _{j + 1} −t _j ) · ΣE _j (t _{j + 1} ³ -T _j ³ ) + 3ΣE _j ε _j (t _{j + 1} ² -T _j ² ) ・ ΣE _j (t _{j + 1} ² -T _j ² ) C = 3 [ΣE _j (t _{j + 1} ² -T _j ² )] ² -4ΣE _j (t _{j + 1} ³ -T _j ³ ) · ΣE _j (t _{j + 1} −t _j ).

FIG. 3 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to the present invention. FIG. 3 (a) shows a chip 1 mounted on a substrate 3, and FIG. 3 (b) shows a chip. Each of the stages when the adjusting plate 7 is attached to the upper part 1 is shown.

Assuming that the structure shown in FIG. 3 (a) is a "beam", the stress and warpage generated in the chip 1 are calculated by the equation of the multi-layer composite beam model based on the above-mentioned material mechanics. The physical properties of the material are as shown below.

Chip 1: Thickness t 1 = 0.6 mm, linear expansion coefficient α 1 = 0.35 ×
Ten^-Five/ ° C, Young's modulus E1 = 17,000 kg / mm²  Adhesive layer 5: thickness t2 = 0.2 mm, linear expansion coefficient α2 = 5.00 ×
Ten^-Five/ ° C, Young's modulus E2 = 100kg / mm²  Base plate 3: thickness t3 = 1.0 mm, linear expansion coefficient α3 = 1.60 x
Ten^-Five/ ° C, Young's modulus E3 = 2000kg / mm²  The load condition is -200 ° C (that is, lower the temperature by 200 ° C.
It is).

According to such conditions, in the structure shown in FIG. 3 (a), the top surface of the chip is 8 kg / mm ² Tensile stress occurs. The lower surface is compressed. Radius of curvature is -5
If the chip 1 size is 10 mm,
It also bends by 25 μm.

Therefore, as in the structure shown in FIG. 3B, the adjusting plate 7 is attached to the upper surface of the chip 1 to improve the stress generated in the chip 1 and the overall deflection. The plate is a copper plate,
The optimum value of the thickness tx is obtained as follows.
The physical properties of the material are as shown below.

Chip 1: Thickness t 1 = 0.6 mm, linear expansion coefficient α 1 = 0.35 ×
Ten^-Five/ ° C, Young's modulus E1 = 17,000 kg / mm²  Adhesive layer 5: thickness t2 = 0.2 mm, linear expansion coefficient α2 = 5.00 ×
Ten^-Five/ ° C, Young's modulus E2 = 100kg / mm²  Base plate 3: thickness t3 = 1.0 mm, linear expansion coefficient α3 = 1.60 x
Ten^-Five/ ° C, Young's modulus E3 = 2000kg / mm²  Adjustment plate 7: Thickness tx (below), linear expansion coefficient αx = 1.70x
Ten^-Five/ ℃, Young's modulus Ex = 11000kg / mm²  Adhesive layer 6: Thickness ty = 0.2 mm, linear expansion coefficient αy = 5.00 ×
Ten^-Five/ ℃, Young's modulus Ey = 100kg / mm²  The load condition is -200 ° C (that is, lower the temperature by 200 ° C.
It is).

Under these conditions, the plate thickness tx is 0.3 m
If m, the stress generated in the chip is all compressive stress. The radius of curvature is 5920 mm, and it will bend in the opposite direction (top side). When the plate thickness tx is 0.2 mm, all the stress generated in the chip is also compressive stress, and the radius of curvature is -3594 mm. From this, it can be seen that the chip does not bend when the thickness of the adjusting plate is between 0.2 mm and 0.3 mm. However, in both cases, the stress generated in chip 1 is -15kg / mm ² Since it is a compressive stress of a certain degree and a tensile stress is not generated, the chip 1 is not destroyed.

By the way, the breaking strength of the chip surface (element forming surface) is 20 kg / mm ^{2 in} tensile. Degree, compression 30kg / mm ² However, due to the processing on the back of the chip, the breaking strength is 8 kg / mm in tension.
² Degree, compression 30kg / mm ² The degree is low and it is weak in tension.

4A and 4B are views showing a semiconductor device according to a second embodiment of the present invention. FIG. 4A is a plan view showing the arrangement of bump electrodes, and FIG. 4B is a view in FIG. It is sectional drawing which follows the bb line.

As shown in FIGS. 4A and 4B, the bump electrodes 2 are arranged only on the outer periphery of the chip 1,
Are bonded to the substrate 3 via the bump electrodes 2. Further, the chip 1 is adhered to the substrate 3 also via the adhesive layer 5B. The adhesive layer 5B is an insulating resin (for example, silicone). On the back surface of the chip 1, a plastic plate having a coefficient of linear expansion larger than that of the chip 1 is bonded as an adjusting plate 7B via an adhesive layer 6.

In the structure according to the second embodiment, since the adhesive layer 5B made of an insulating resin is embedded between the chip 1 and the substrate 3, the adhesive surface between the chip 1 and the substrate 3 can be widened, and the adhesiveness can be improved. Can be increased.

5A and 5B are views showing a semiconductor device according to a third embodiment of the present invention. FIG. 5A is a plan view showing the arrangement of bump electrodes, and FIG. 5B is a plan view in FIG. It is sectional drawing which follows the bb line.

As shown in FIGS. 5A and 5B, the bump electrodes 2 are concentrated on a part of the surface of the chip 1. In this embodiment, the bump electrodes 2 have a grid shape and are concentrated in one corner of the chip 1. Dummy bumps 8 unrelated to signal transmission are provided in the other three corners. Dummy bump 8 does not transmit signals,
The size is made larger than that of the bump electrode 2 in order to improve heat transfer. The chip 1 is bonded to the substrate 3 by the bump electrodes 2 and the dummy bumps 8. Further, the chip 1 is also adhered to the substrate 3 by the adhesive layer 5B. The adhesive layer 5B in this embodiment is an insulating adhesive (for example, epoxy resin). On the back surface of the chip 1, the same material (for example, silicon) as that of the chip 1 and having a size larger than that of the chip 1 is bonded as an adjusting plate 7C via an adhesive layer 6.

With the structure according to the third embodiment, since the bump electrodes 2 are concentrated on a part of the surface of the chip 1, fatigue of the bump electrodes 2 can be suppressed. This is because if the bump electrode 2 is provided on the outer periphery of the chip 1, the distorted difference between the chip 1 and the substrate 3 becomes large, but if the bump electrode 2 is concentrated on a part so as to deviate from the outer periphery of the chip 1, the distorted strain is reduced. This is because the difference can be reduced.

6A and 6B are views showing a semiconductor device according to a fourth embodiment of the present invention. FIG. 6A is a plan view showing the arrangement of bump electrodes, and FIG. 6B is a view in FIG. It is sectional drawing which follows the bb line.

From the viewpoint described in the third embodiment, as shown in FIGS. 4A and 4B, the bump electrodes 2 are formed in a grid shape and are concentrated in the central portion of the chip 1. You may do it. The effect is that the fatigue progression of the bump electrode 2 can be suppressed as in the third embodiment.
In this embodiment, since a device having a small amount of heat generation is taken as an example, there is no dummy bump, and a plastic plate 7B is used as the adjusting plate. Further, the arrangement pattern of the bump electrodes 2 in the third and fourth embodiments is not limited to the grid pattern,
It may be staggered. FIG. 7 is a sectional view of a semiconductor device according to the fifth embodiment of the present invention.

As shown in FIG. 7, a plurality of chips 1-1, 1
In this case, the adjusting plate 7 is shared by a plurality of chips 1-1 and 1-2. As described above, even if the adjusting plate 7 is shared by the plurality of chips 1-1 and 1-2, the chips 1-1 and 1-2 can be prevented from being broken due to bending deformation. It should be noted that a copper plate, plastic, silicon or the like can be used for the adjusting plate 7. Figure 8
It is sectional drawing of the semiconductor device concerning the 6th Example of this invention.

The size of the adjusting plate 7 is not limited to the size larger than that of the chip 1, and as shown in FIG.
The size of the adjusting plate 7 may be smaller than that of the chip 1 when the chip 1 can be adjusted so as to cancel the bending of the chip 1.
It is possible to use a copper plate, plastic, silicon, or the like for the adjusting plate 7, but when using the adjusting plate 7 of a small size, it is desirable to select a material having a high breaking strength.

According to the semiconductor device having the structure described in each of the above-described embodiments, the chip 1 and the mounting substrate 3 are fixed to each other by the adhesive layer 5, and the chip 1 and the substrate 3 are mutually connected even in the portions other than the bump electrodes 2. It is supposed to be fixed.
Therefore, when the substrate 3 expands and contracts, the chip 1 itself bends and deforms in accordance with the deformation. As a result, the stress associated with the expansion and contraction of the substrate 3 is distributed to the chip 1 and the stress concentration on the bump electrode 2 can be prevented. Therefore,
The amount of strain of the bump electrode 2 is reduced, the thermal fatigue resistance is increased, and the thermal cycle characteristics of the semiconductor device are improved.

Further, in each of the above embodiments, the substrate 3 is made of alumina, and has a larger linear expansion coefficient than that of silicon which constitutes the chip 1. For this reason, when the device goes from a high temperature state to a room temperature (low temperature) state, the chip 1 warps so that its back surface becomes convex. When the chip 1 is warped in this way, tensile stress is generated on the back surface of the chip 1, and the back surface of the chip 1 is cracked or broken, or the internal integrated circuit is destroyed. In order to prevent such damage of the chip 1, an adjusting plate 7 made of a material having a linear expansion coefficient larger than that of the chip 1 is attached on the back surface of the chip 1. By attaching the adjusting plate 7 as described above, the deformation of the chip 1 itself due to the deformation of the substrate 3 is adjusted or alleviated, and the above problem can be solved.

The adjusting plate 7 is preferably made of a material having a coefficient of linear expansion larger than that of the chip 1.
When such a material cannot be procured, it is possible to consider the adhesive layer 6 as a part of the adjusting plate 7 and adjust the material and the coating thickness to adjust the linear expansion coefficient. Also, the adjusting plate 7
The effect equivalent to adjusting the coefficient of linear expansion can also be obtained by changing the thickness of the film and changing its rigidity.

In each of the above-described embodiments, a plate-shaped member such as a copper plate or a plastic plate is used as the adjusting member for adjusting the bending of the chip. In addition to this, a film having a coefficient of linear expansion larger than that of the chip 1 is used. It is also possible to use a resinous material or a thermosetting resin.

Further, the position of attaching the adjusting member is not limited to the back surface of the chip 1, but may be from the back surface of the chip 1 to the side surface thereof, or may be only on the side surface of the chip 1. Of course, various modifications can be made without departing from the spirit of the present invention.

[0041]

As described above, according to the present invention, it is possible to provide a semiconductor device having good thermal cycle characteristics and high reliability, and a chip deformation preventing method for obtaining such a semiconductor device. .

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic view of a multi-layer composite beam.

FIG. 3 is a schematic diagram of a cross-sectional structure of a semiconductor device according to the present invention, FIG. 3A is a diagram showing a stage in which a chip is mounted on a substrate, and FIG. 3B is a diagram showing an adjusting plate on the chip. The figure which shows the stage attached.

4A and 4B are views showing a semiconductor device according to a second embodiment of the present invention, in which FIG. 4A is a plan view and FIG.
Sectional drawing which follows the bb line in a figure.

5A and 5B are views showing a semiconductor device according to a third embodiment of the present invention, wherein FIG. 5A is a plan view and FIG. 5B is a drawing.
Sectional drawing which follows the bb line in a figure.

6A and 6B are views showing a semiconductor device according to a fourth embodiment of the present invention, wherein FIG. 6A is a plan view and FIG. 6B is a drawing.
Sectional drawing which follows the bb line in a figure.

FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

9A and 9B are views showing a flip-chip type semiconductor device. FIG. 9A is an ideal product sectional view, and FIG. 9B is an actual product sectional view.

[Explanation of symbols]

1, 1-1, 1-2 ... Semiconductor chip, 2 ... Bump electrode, 3 ...
Mounting substrate, 4 ... Wiring pattern, 5, 5A, 5B ... Adhesive layer, 6 ... Adhesive layer, 7, 7A, 7B, 7C ... Adjusting plate, 8 ...
Dummy bump.

Claims (5)

[Claims] 1. A semiconductor chip flip-chip connected to a mounting substrate via a conductive electrode, the chip and the mounting substrate provided between the chip and the mounting substrate except for the conductive electrode. A semiconductor device comprising: a fixing means for fixing a chip and an adjusting means for adjusting the bending of the chip. 2. The conductive electrode is a bump electrode provided on the chip, and the bump electrode is concentrated on a part of the chip. Semiconductor device. 3. A chip deformation preventing method for a semiconductor device having a structure in which a semiconductor chip is flip-chip connected via a conductive electrode on a mounting substrate, wherein the conductive material is provided between the chip and the mounting substrate. In addition to the electrodes, a fixing means for fixing the chip and the mounting board is provided so that the chip bends according to the expansion and contraction of the mounting board, and the bending of the chip is adjusted so as to cancel the bending by the fixing means. A chip deformation preventing method, characterized in that the chip is prevented from being deformed by providing adjusting means for controlling the chip deformation. 4. The chip according to claim 3, wherein the bending of the chip is adjusted by adjusting the thickness of the material forming the adjusting means, its Young's modulus and its linear expansion coefficient. Deformation prevention method. 5. The adjustment of the deflection of the chip is calculated by the material mechanics, assuming that the multi-layer composite part including the mounting substrate, the fixing means, the chip and the adjusting means is a multi-layer composite beam. The method for preventing deformation of a chip according to claim 4, wherein the method is performed by applying an equation.