1254429 九、發明說明： 【發明所屬之技術領域】 特別是有 本發明係有關於一種覆晶型電子構裝結構 關於一種可撓式覆晶構裝結構。 【先前技術】 近^來’由於電子產品之應用面越趨廣泛，除 桌上型筆記型電腦之外’亦漸有電子產品應用於民生用 ^ 的趨勢。在此㈣下’電子產品的可穿戴性、可攜帶性及 ^小化為基本考量外，亦需考量到電子產品的柔軟度。在 =子產品具有柔軟的特質時，其可攜帶性、 =所，的空間㈣題即可有效料。㈣電子元二晶 片溥化後雖具有柔軟可撓曲之特性，但同時亦相當:曰， =:在易發生斷裂及微小破裂等負面效應。除 好為*屯冓衣70件中，各種不同材料之溫度分佈狀況 及…祕餘(C〇effieient Gf Thefmal 之界面區域形成不匹配的熱應力，進—步有可 接點斷裂’而造成元件損壞。此類破壞現象多 電子構裝元件之主要模式。因此，如何 件：用二：兔；軟可撓曲且不發生破壞與能延長電子元 件使用a守間成為電子元件構裝之重要嗶題。 I前的電子縣技術其焊點連接方式皆採表面 3 2 ee mGunt) ’無法達到超薄可撓曲之要求。例 :2:朕上晶片封裝技術 C〇F(ChiP_〇n_Hlm package) 固化合限制麻狀太直毛未上，且使用的底膠（underfi11) ^ =絲本身可行動性，並且底膠於溫度循環之膨 '"里"、>%·日日片與相電路板之間的接觸力，使封裝結 12544291254429 IX. Description of the invention: [Technical field to which the invention pertains] In particular, the present invention relates to a flip-chip type electronic package structure relating to a flexible flip chip structure. [Prior Art] Since the application of electronic products has become more widespread, in addition to desktop notebook computers, there has been a trend toward the use of electronic products for people's livelihood. Under this (4), the wearability, portability and miniaturization of electronic products are basic considerations, and the softness of electronic products must also be considered. When the sub-product has a soft trait, its portability, space, and space (4) can be effectively used. (4) Although the electronic element two crystals have soft and flexible properties after deuteration, they are also equivalent: 曰, =: are susceptible to breakage and micro-fracture and other negative effects. In addition to the 70 pieces of * 屯冓, the temperature distribution of various materials and ... secret (C〇effieient Gf Thefmal interface area forms a mismatched thermal stress, the step has a joint break) Damage. This type of destruction is the main mode of multi-electronic components. Therefore, how to use: two: rabbit; soft and flexible without damage and can extend the use of electronic components to become an important part of electronic components. I. Before the electronic county technology, the solder joint connection method was adopted on the surface 3 2 ee mGunt) 'The ultra-thin flexible requirements could not be achieved. Example: 2: Chip package technology C〇F(ChiP_〇n_Hlm package) Curing and restraining hemp is too straight, and the underlying glue (underfi11) ^ = the wire itself is mobile, and the primer is The temperature cycle of the expansion '" in ", >% · the contact force between the Japanese film and the phase circuit board, so that the package junction 1254429
才ίΐί度降低ϋ已知採表面黏著方式的電子構裝技 ^ 用順型凸塊(Compliant Bump)，此技術需於凸塊表 盘鑛上5至材料，藉由凸塊底面之合金材料，以接觸方式 人土板連接而此底面合金材料會限制凸塊橫向所能吸收 ^應力與應變。第-圖係另—種已知電子構裝結構截面示 其丈干點凸塊14係使用高分子核心材料142外面包覆 $電性材料層144。由於此種電子構裝結構亦採用表面黏 著方式將晶片12結合於軟性基板1〇上，焊點凸塊14於承 叉撓曲時易因晶片12與軟性基板1〇之勁度(stiffness)差異 太大，使焊點凸塊14承受撓曲之集中力，而容易發生斷 裂’造成電性不導通。 、據上述，由於現有的焊點連接技術仍採用表面黏著方 式，其結構的设計與材料的選用致使目前的電子構裝結構 無法有可撓特性，而無法因應未來軟性電子產業的需求。 因此，亟待提出一種改良的電子構裝技術，其可解決上述 之缺失。 【發明内容】 本發明之主要目的係提供一種可撓式覆晶構裝結 構，係利用半導體晶片主動面的可撓性導電凸塊電性接觸 地伸入軟性基板的電性連接孔，結合前述半導體晶片與軟 性基板，以獲得超薄可撓曲低應力的電子構裝結構。 本發明之另一目的係提供一種可撓式覆晶構裝結 構，其可相容於現有製程，不增加製程的複雜度，可大幅 提升產品玎靠度。 本發明之又一目的係提供一種超薄可撓式覆晶構裝結 構，可滿足現有軟性電子市場可穿戴、可攜帶及微小化的 6 1254429 需求。 為達上述目的，本發明提供一種 a 構’其包括-可撓性基板及單或複數;;,曰曰 可撓性基板之:表面具有單或複數個電丄 數條吼號傳輪導線，而前述複數停 ’、稷 導體曰 對的兩表面。每一前述半 接觸地伸入前述可撓性基板之前述電 電性ii使前料導體晶片㈣述可触基板產生 刖1可撓性導電凸塊使前述半導體 基板之間的焊點具有柔軟的特性，At :钔达了“挫 熱膨脹係數不匹配所產生的敎應月，匕並=3幵^及吸收因 可撓性基板之可撓性達到可配a缚型晶片與 之可撓式覆晶構裝結構可以現有▲程义作=外，，明 般構裝製程步驟’大幅降低成本。、a，1可簡化一 【實施方式】 有製程下，將其等組:構;==:在 單或複數個半導體晶片。構係包括一可撓性基板及 導電性貫穿孔：ΞΪ4ϊ:ϊ性基板上有單或複數個 電子被動元件，曰曰片可以是電子主動元件或 塊，以供做焊點凸塊。太称、有早或複數個可撓性導電凸 電性接觸地伸入前述貫穿x明係利用前述可徺性導電凸塊 、孔，以使前述半導體晶片結合於 1254429 剞述可撓性基板上，而藉由前述可撓性基板上的電訊傳 輸導線將前述半導體晶片的電子訊號連通於前述可撓性基 板的焊墊上。本發明的覆晶構裝結構可適用超薄晶^& 構衣正體尽度可小於0.3晕米（mm)，而利用超薄晶片具可 撓之特性與可撓性基板可撓特點，配合可撓性導電凸塊可 承受大變形的特性，使本發明的構裝結構具有可承受撓曲 的特點。再者，因為可撓性基板之彈性係數較一般有^基 板為小，且可撓性基板厚度亦較一般基板為薄，故可撓性 基板之力學勁度將較有機基板為小，因熱膨脹係數不匹配 之差異性對於結構造成的影響，將由於可撓性基板勁度較 晶片為小，於^度負載下無法因熱膨脹效應對電子構^結 構產生較大之勇力應力，且由於可撓性導電凸塊吸收應力 之效應，使本發明構裝結構為低應力結構，而能有g的 可靠度。 本發明之目的及諸多優點藉由以下具體實施例之詳 、，、田况=，並參照所附圖式，將趨於明瞭。 第圖係*發明可挽式覆晶（fHp chip)構裝結構的 可搞：體實施例的截面示意圖。在第-具體實施例中， 數ϋΐ晶構裝結構2〇係包括一可挽性基板2卜單或複 24。^體晶片22、一高分子保護層23及一基板保護層 圓私^可挽式覆晶構裝結構20具有單或複數個貫穿具 於前、^ σ壁的電性連接孔211。前述電性連接孔211分佈 array^可撓性基板21所形成的圖案，包含面陣列（靡 或以外圏排列(penpheraiarrangement)、個別焊點排列 線重八Γ]之組合。前述可撓性基板21之—表面具有導 傳導:。f 案（WireredistributionPattern)212,係供做訊號 岫述導線重分佈圖案212係電氣連接於前述電 1254429 於#、以將珂述半導體晶片22 述可撓性从214 ί +體4 22係安置於前 上。每述半導顺前述導線重分佈圖案212的一表面 柱狀的：⑵片 性接觸地伸入前述可娃 ’、、點凸塊，其係電The electronic assembly technique is known to use a Compliant Bump. This technique requires 5 to the material on the bump dial, and the alloy material on the bottom surface of the bump The contact method is connected to the earth plate and the bottom alloy material limits the stress and strain absorbed by the lateral direction of the bump. The first-figure is a cross section of a known electronic structure. The bump 14 is covered with a polymer core material 142 and coated with a layer 144 of an electrical material. Since the electronic structure also bonds the wafer 12 to the flexible substrate 1 by surface adhesion, the solder bumps 14 are susceptible to the difference in stiffness between the wafer 12 and the flexible substrate 1 when the carrier is flexed. Too large, the solder bumps 14 are subjected to the concentrated force of the deflection, and the breakage is likely to cause electrical non-conduction. According to the above, since the existing solder joint connection technology still adopts the surface adhesion method, the design of the structure and the selection of materials make the current electronic structure structure unable to have flexible characteristics, and cannot meet the needs of the future soft electronics industry. Therefore, an improved electronic assembly technique is urgently needed to solve the above-mentioned drawbacks. SUMMARY OF THE INVENTION The main object of the present invention is to provide a flexible flip-chip structure, which is formed by electrically connecting a flexible conductive bump of a semiconductor wafer active surface into an electrical connection hole of a flexible substrate. The semiconductor wafer and the flexible substrate are used to obtain an ultra-thin flexible low-stress electronic structure. Another object of the present invention is to provide a flexible flip-chip structure that is compatible with existing processes without increasing the complexity of the process and greatly improving product reliability. It is yet another object of the present invention to provide an ultra-thin flexible flip-chip structure that meets the needs of the existing flexible electronics market for wearable, portable and miniaturized 6 1254429. In order to achieve the above object, the present invention provides a structure comprising: a flexible substrate and a single or plural;; a flexible substrate: the surface has a single or a plurality of electric turns and a number of pass wires, And the aforementioned plurality of stops, the two surfaces of the pair of conductors. The electro-optic ii of each of the aforementioned semi-contacting projections of the flexible substrate causes the front-end conductor wafer (4) to produce a 可1 flexible conductive bump to make the solder joint between the semiconductor substrates soft. , At : 钔 了 “ “ “ “ “ “ “ “ “ “ 挫 挫 挫 挫 挫 挫 挫 挫 挫 挫 挫 挫 挫 挫 挫 挫 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及The structure of the structure can be ▲ 程 作 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Single or plural semiconductor wafers. The structure includes a flexible substrate and a conductive through hole: ϊ4ϊ: a single or a plurality of electronic passive components on the flexible substrate, and the cymbal may be an electronic active component or block for making Solder bumps, too long, or a plurality of flexible conductive bumps are electrically contacted into the aforementioned through-holes to utilize the aforementioned conductive bumps and holes to bond the semiconductor wafer to 1254429. On the flexible substrate, by the aforementioned flexible substrate The upper telecommunication transmission wire connects the electronic signal of the semiconductor chip to the pad of the flexible substrate. The flip-chip structure of the present invention can be applied to an ultra-thin crystal and the body can be less than 0.3 halo. Mm), while utilizing the flexible characteristics of the ultra-thin wafer and the flexible characteristics of the flexible substrate, the flexible conductive bump can withstand the characteristics of large deformation, so that the structure of the invention can withstand the characteristics of deflection Furthermore, since the elastic modulus of the flexible substrate is smaller than that of the general substrate, and the thickness of the flexible substrate is thinner than that of the general substrate, the mechanical stiffness of the flexible substrate is smaller than that of the organic substrate. The difference in thermal expansion coefficient mismatch will have a greater impact on the structure, because the stiffness of the flexible substrate is smaller than that of the wafer, and the thermal expansion effect cannot cause a large stress on the electronic structure due to the thermal expansion effect, and The effect of the stress relaxation of the flexible conductive bumps makes the structure of the present invention a low stress structure, and can have a reliability of g. The objects and many advantages of the present invention are as follows by the following specific embodiments. Field condition =, and with reference to the accompanying drawings, it will be apparent. Fig. 4 is a schematic cross-sectional view of a body embodiment of the invention, which can be used in a pull-on flip-chip (fHp chip) structure. The ϋΐ 构 构 包括 包括 包括 ϋΐ ϋΐ 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 体 体 体 体 体 体 体 体 体 体 体The structure 20 has a single or a plurality of electrical connection holes 211 extending through the front wall of the σ. The electrical connection holes 211 are distributed in a pattern formed by the array of flexible substrates 21, including an array of planes (靡 or 圏a combination of (penpheraiarrangement) and individual solder joint arrangement line weights. The surface of the flexible substrate 21 has a conductive conduction: .f (WireredistributionPattern) 212, which is used for signal to describe the wire redistribution pattern 212. Connected to the aforementioned electric 1254429 in # to place the flexible semiconductor wafer 22 on the front side from the 214 ί + body 4 22 series. Each of the semi-conductors follows a surface of the wire redistribution pattern 212 in a columnar shape: (2) a sheet contacted into the aforementioned watts, and a bump, which is electrically charged
Φ ^了撓性基板21之前述電性i車桩別9U 中’以傳遞前述半導俨曰ΰ 9?盥前 連接孔211 間的電子1於。义、+、日日片，、刖述可撓性基板21之Φ ^ The above-mentioned electric i-carriage 9U of the flexible substrate 21 is used to transmit the electrons 1 between the semi-conductive 俨曰ΰ 9 盥 front connection holes 211. Yi, +, Japanese, and the flexible substrate 21
22U 性導電凸堍2 21 a的#白勺内科狀相匹配，所以前述可撓 内部形狀^ la::何形狀係視前述電性連接孔211的 ^ 1 前述可撓性導電凸塊221a係可以 + 、艮、至及鋁寺可撓性金屬材料形成，或者由埴充導 顆粒的高分子材料形成。前述半導體晶片22接合於 :込可撓性基板21的手段包含合金回焊接合、膠合、壓 3或以上手段之組合。前述半導體晶片22可以是電子= t元件或電子被動元件。在第一具體實施例中，前述可 ，式覆晶構造結構可以是超薄覆晶構裝結構，其可採用 厚度不超過50宅微米（um)的薄型晶片22及可撓性基板 21 ’使得整體構裝後的厚度不超過〇·3毫米。再者， 由於鈾述半導體晶片22薄化後剛性減弱，具有可撓性但 易破裂，所以在其背面塗覆一高分子材料層222，做為晶 片補強結構，以消除前述半導體晶片22於製程與撓曲時 易發生破裂的負面效應。前述高分子材料層222較佳是 多孔性高分子材料(porous polymer material)，藉其多孔特 性以利於消散應力。此外，可以一高分子保護層23，例 如是多孔性高分子材料層，包覆前述高分子材料層222、 前述半導體晶片22及前述可撓性基板21表面，以保護 1254429 ，個構裝結構。再者，前述基板保護層24The inner conductive shape of the 22U conductive projection 2 21 a is matched, so the flexible inner shape is: the shape depends on the electrical connection hole 211. The flexible conductive bump 221a can be +, 艮, 至, and aluminum temples are formed of a flexible metal material or a polymer material that entangles particles. The means for bonding the semiconductor wafer 22 to the 込 flexible substrate 21 includes alloy reflow bonding, gluing, pressing 3 or a combination of the above. The aforementioned semiconductor wafer 22 may be an electronic=t element or an electronic passive element. In the first embodiment, the foregoing flip-chip structure may be an ultra-thin flip-chip structure, which may be formed by using a thin wafer 22 and a flexible substrate 21' having a thickness of not more than 50 um. The thickness after the overall assembly does not exceed 〇·3 mm. Furthermore, since the uranium semiconductor wafer 22 is thinned and has reduced rigidity and is flexible but easily broken, a polymer material layer 222 is coated on the back surface thereof to serve as a wafer reinforcing structure to eliminate the semiconductor wafer 22 in the process. Negative effects that are prone to rupture when flexed. The polymer material layer 222 is preferably a porous polymer material, and its porous property is advantageous for dissipating stress. Further, a polymer protective layer 23, for example, a porous polymer material layer, may be coated on the surface of the polymer material layer 222, the semiconductor wafer 22, and the flexible substrate 21 to protect 1254429. Furthermore, the aforementioned substrate protection layer 24
撓性基板21的下方，以保罐盆矣而沾、， ；刖处T 案212。）下彳以保4其表面的可述導線重分佈圖 前述可撓性導電凸塊221a因具有 達到柔軟的特性，而配合薄型晶片22輿前述 ，_性，可達到可撓構裝的 二導電凸塊22la因具有柔軟性故能吸收 =: 力，使構裝結構具有低應力。再者，前持:生二應上 具有較低的剛性勁度，可達到焊點高 板21 弟一 B圖係弟一具體實施例的一變化例，1盥 肢貫施例的差異係在於其可撓性導電凸 ς二2乂二 雷性i表拔*71 Ο Ί 4+ 1 b係、貝牙如述 ^生連接孔2H，而其餘職部件係與第—具體實施例相 實施二^第圖係i發Λ可Λ式覆晶構農結構的第二具體 貫施例中’可撓式覆晶構裝結構3〇 匕括可說性基板31、單或複數個半導體晶一古 分子保護層33及一基板俘婼屏34。铪、+、日日 、一问 么士槿30呈右-々、-ί又層 返可挽式覆晶構裝 Γι im 貫穿具圓柱形内壁的電性連接孔Below the flexible substrate 21, the cans are immersed in the cans, and the T is the case 212. The above-mentioned flexible conductive bump 221a has a softness characteristic, and is matched with the thin wafer 22, as described above, to achieve a flexible two-conducting structure. The bump 22la is capable of absorbing = force due to its flexibility, so that the structure has low stress. Furthermore, the pre-holding: the second should have a lower stiffness, which can reach a variation of the welding point high plate 21, a brother, a B-picture, a specific embodiment, the difference between the 1 limbs and the limbs is The flexible conductive embossing 2 2 乂 雷 i i * 71 71 71 71 71 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ^图图I Λ Λ Λ 覆 覆 覆 ' ' ' ' ' ' ' ' ' 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可The molecular protective layer 33 and a substrate captive screen 34.铪,+,日日,一问 槿士槿30 is right-々,- ί又层回回式覆晶装 Γι im through the electrical connection hole with cylindrical inner wall
成的接孔311分佈於前述可繞性基板31所形 成勺圖木，〇 3面陣列（area array)、外圈排 W arrangement)、個別焊點排列或以上排列之纟且人。前述可 撓性基板31之一表面具有導線重分佈圖案…以 red1Stnbim〇npattem)312，係供做訊號傳導線。前述導線 重分佈圖案312係電氣連接於前述電性連接孔3ΐι，以將 前述半導體晶片32的電子訊號連通於前述電性連接孔 311。前述半導體晶片32係安置於前述可撓性基板31相 對前述導線重分佈圖案312的一表面上。每一前述半導 10 1254429 體晶片32的主動面具右 凸塊321a,係供做焊呈圓柱狀的可撓性導電 可撓性基板之前係電性接觸地伸入前述 巧32與前述可撓性基板孔3131 二的述i 述可撓性導電凸塊32h及π 就。耵 、、》#rr) #&、， 可以可撓性高分子材料做為核 覆-導雷材枓323 — 連接 壁接觸的周壁包 復W材枓323別述半導體晶片32接合於前述 性基板31的手段包含合金回焊接合、膠合、壓合或以^ 手段之組合。前述”體晶片32可以是電子主動元件 電子被動元件。在第二具體實施例中，前述可撓式覆曰 構造結構可以是超薄覆晶構裝結構，其可採用厚度不 過50毫微米（um)的薄型晶片32及可撓性基板31，使得 整體構裝後的厚度不超過0.3毫米（mm)。再者，可於前述 半導體晶片32背面塗覆一高分子材料層324，做為晶片** 補強結構，以消除前述半導體晶片32於製程與撓曲時易 發生破裂的負面效應。前述高分子材料層324較佳是多 孔性高分子材料(Por〇us polymer material)，藉其多孔特性 以利於消散應力。此外，可以一高分子保護層33，例如 是多孔性高分子材料層，包覆前述高分子材料層322、前 述半導體晶片3 2及兩述可挽性基板31表面’以保護整 個構裝結構。再者，前述基板保護層34形成於前述可撓 性基板31的下方，以保護其表面的前述導線重分佈圖案 312。 第三B圖係第二具體實施例的一變化例，其與第二具 體實施例的差異係在於其可撓性導電凸塊321b係貫穿前述 電性連接孔311，而其餘構裝部件係與第二具體實施例才目 同。 11 1254429 弟二C圖係弟二具體實施例的另一變化例，其與第一 具體實施例的差異係在於其可撓性導電凸塊321c係具有一 可撓性高分子材料做為核心材料322,及一導電材料勺 覆整個核心材料322。 匕 弟四A圖係本發明可撓式覆晶構裝結構的第三具體 實施例。在第三具體實施例中，可撓式覆晶構裝結^籌、^ 係包括一可撓性基板41、單或複數個半導體晶片42、一 面分子保凌層43及一基板保護層44。前述可撓式覆晶 裝結構40具有單或複數個貫穿具角柱形内壁的電性 孔411。前述電性連接孔411分佈於前述可挽性基板μ 所形f的圖案，包含面陣列—array)、外圈排列The formed vias 311 are distributed over the aforementioned flexible substrate 31 to form a scoop, an array of arrays, an outer array of arrays, individual solder joint arrangements or the above arrangement. One surface of the aforementioned flexible substrate 31 has a wire redistribution pattern ... to be a signal transmission line. The wire redistribution pattern 312 is electrically connected to the electrical connection hole 3ΐ to connect the electronic signal of the semiconductor wafer 32 to the electrical connection hole 311. The semiconductor wafer 32 is disposed on a surface of the flexible substrate 31 opposite to the wire redistribution pattern 312. The active mask right bump 321a of each of the aforementioned semi-conductive 10 1254429 body wafers 32 is electrically contacted into the flexible flexible conductive substrate before being soldered into the aforementioned flexible 32 and the aforementioned flexible The substrate holes 3131 are described as the flexible conductive bumps 32h and π.耵,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The means of the substrate 31 comprise alloy reflow soldering, gluing, pressing or a combination of means. The foregoing "body wafer 32 may be an electronic active element electronic passive element. In the second embodiment, the foregoing flexible cover structure may be an ultra-thin flip-chip structure, which may be a thickness of 50 nanometers (um). The thin wafer 32 and the flexible substrate 31 have a thickness of not more than 0.3 millimeters (mm) after the overall assembly. Further, a polymer material layer 324 may be coated on the back surface of the semiconductor wafer 32 as a wafer* * Reinforcing the structure to eliminate the negative effect that the semiconductor wafer 32 is prone to cracking during the process and deflection. The polymer material layer 324 is preferably a porous polymer material (porous polymer material), In addition, a polymer protective layer 33, for example, a porous polymer material layer, may be coated on the surface of the polymer material layer 322, the semiconductor wafer 32, and the two removable substrates 31 to protect the entire Further, the substrate protective layer 34 is formed under the flexible substrate 31 to protect the wire redistribution pattern 312 on the surface thereof. The third B is the second A variation of the embodiment is different from the second embodiment in that the flexible conductive bump 321b penetrates through the electrical connection hole 311, and the remaining components are different from the second embodiment. 11 1254429 Another variation of the specific embodiment of the second embodiment is different from the first embodiment in that the flexible conductive bump 321c has a flexible polymer material as The core material 322, and a conductive material scoop the entire core material 322. The fourth embodiment of the present invention is a third embodiment of the flexible flip chip structure of the present invention. In the third embodiment, the flexible cover The crystal structure comprises a flexible substrate 41, a single or plurality of semiconductor wafers 42, a molecularly secured layer 43 and a substrate protective layer 44. The flexible flip-chip structure 40 has a single or a plurality of electrical holes 411 penetrating through the inner wall of the prismatic column. The electrical connection holes 411 are distributed in the pattern of the shape f of the printable substrate μ, including an array of arrays, and an outer ring arrangement.
IenPi:a=rangement)、個別焊點排列或以上排列之組 ,。則，可撓性基板41之—表面具有導 redlstributionpattern)412，係供做訊號傳導線。= :12係電氣連接於前述電性連接孔411， 料料料性連接 干^體日日片42係安置於前述可择槌其把W 相對前述導線重分佈圖冑 基板41 導體晶片42的主1 *面上。每—前述半 電凸塊42U，係供做焊點凸‘，狀的可撓性導 撓性基板41之前述電性連接二: = +導體晶片42與前述可垆 $ U傳遞“ 導電凸塊42二幾二===接 孔川的内部形狀相匹配 二月^d生連接 如係可以銅、銀 ^ Μ可触導電凸塊 者由填充導電性難的t =撓性金屬材料形成，或 …合於前述可繞：基:二 1254429IenPi: a = rangement), individual solder joints or groups of above. Then, the surface of the flexible substrate 41 has a redstribution pattern 412 for signal transmission. = : 12 is electrically connected to the above-mentioned electrical connection hole 411, and the material material is connected to the dry body of the solar cell 42 to be disposed in the foregoing, and the main body of the conductor wafer 42 is re-distributed with respect to the wire. 1 * face. Each of the semi-electric bumps 42U is electrically connected to the flexible conductive substrate 41 of the solder bumps. The conductive wafers 42 and the aforementioned conductive wafers are transferred to the conductive bumps. 42二二二=== The internal shape of the Kongchuanchuan matches the February ^d raw connection, such as copper, silver ^ Μ contactable conductive bumps are formed by t = flexible metal material filled with conductivity, or ...in combination with the foregoing: base: two 1254429
合、膠合、壓合或以上手段之組合。前述半導體晶片42 可以是電子主動元件或電子被動元件。在第三具體實施 例中，前述可撓式覆晶構造結構可以是超薄覆晶構裝結 構，其可採用厚度不超過50毫微米（um)的薄型晶片22 及可撓性基板41，使得整體構裝後的厚度不超過〇.3毫 米（mm)。再者，可於前述半導體晶片42背面塗覆一高分 子材料層422，做為晶片補強結構，以消除前述半導體晶 片42於製程與撓曲時易發生破裂的負面效應。前述高分 子材料層422較佳是多孔性高分子材料(porous polymer material)，藉其多孔特性以利於消散應力。此外，可以一 高分子保護層43，例如是多孔性高分子材料層，包覆前 述高分子材料層422、前述半導體晶片42及前述可撓性 基板41表面，以保護整個構裝結構。 再者’前述基板保護層44形成於前述可撓性基板41的下 方，以保護其表面的前述導線重分佈圖案412。 第四B圖係第三具體實施例的一變化例，其與第三具 體實施例的差異係在於其可撓性導電凸塊42沁係貫穿前^ 電性連接孔411，而其餘構裝部件係與第三具體實施例相 同0 第五A圖係本發明可撓式覆晶構|結構的第四呈體 實施例。在第四具體實施例中，可繞式覆晶構裝結構％ 包括一可撓性基板51、單或複數個半導體晶片52、一古 分子保護層53及-基板保護層54。前财撓 ^ 結構^0具有單或複數個貫穿具㈣形_的電。= =j電=L 511分佈於前迷可繞性基板51所形 4 ^ ® ^ ^ , ® (area array) . # ^ arrangement)、個別焊點排列或以上梆列之組合。前述可 13 1254429 挽性基板51之一表面呈有導έ redistribution pattern)5l2，总# /u·:泉重分佈圖案（wire 重分佈圖案M2係電氣連接於前述=專=。，述導線 前述半導體晶片52的雷早却Γ生連接孔511，以將 51卜前述半導體晶片52係安f 於前述電性連接孔 對前述導線重分佈圖案512的一 述可撓性基板51相 體晶片52的主動面具有至少一二，上。每一前述半導 凸塊52U，係供做焊點凸 J 性導電 導體晶…前述可撓性 遞前述半 係可以可撓性以 : 電性連接孔5U内壁接觸的周壁包 d材料523。前述半導體晶片52接合於前述可样 基板51的手段包含合金轉接合、膠合、壓合: 手段之組合。前述半導體晶片52可以是電子主動元 電子被動元件。在第四具體實施例中，前述可撓式覆2曰 構造結構可以是超薄覆晶構裝結構，其可採用厚度^ 過50宅微米（um)的薄型晶片32及可撓性基板3卜 整體構裝後的厚度不超過〇·3毫米（mm)。再者，可於求 半導體晶片52背面塗覆一高分子材料層524，做為晶> 補強結構，以消除前述半導體晶片52於製程與撓曲時易 發生破裂的負面效應。前述高分子材料層524較佳是多 孔性咼分子材料(Porous polymer material)，藉其多孔特性 =利於消散應力。此外，可以一高分子保護層53，^如 是多孔性高分子材料層，包覆前述高分子材料層524、前 述半導體晶片52及前述可撓性基板51表面，以保護整 個構裝結構。再者，前述基板保護層54形成於前述可^ 14 1254429 性基板51的下方，以保護其表面的前述導線重分佈圖案 512。 第五B圖係第四具體實施例的一個變化例，其與第四 具體實施例的差異係在於其可撓性導電凸塊5 21 b係貫穿前 述電性連接孔511，而其餘構裝部件係與第四具體實施例相 同0Combination, gluing, pressing or a combination of the above. The aforementioned semiconductor wafer 42 may be an electronic active component or an electronic passive component. In the third embodiment, the flexible flip chip structure may be an ultra-thin flip chip structure, and the thin wafer 22 and the flexible substrate 41 having a thickness of not more than 50 nanometers (um) may be used. The thickness after the overall assembly does not exceed 〇.3 mm (mm). Furthermore, a high molecular material layer 422 may be coated on the back surface of the semiconductor wafer 42 as a wafer reinforcing structure to eliminate the negative effect of the semiconductor wafer 42 being susceptible to cracking during process and deflection. The aforementioned high molecular material layer 422 is preferably a porous polymer material, which has a porous property to facilitate dissipation of stress. Further, a polymer protective layer 43, for example, a porous polymer material layer, may coat the surface of the polymer material layer 422, the semiconductor wafer 42, and the flexible substrate 41 to protect the entire structure. Further, the substrate protective layer 44 is formed under the flexible substrate 41 to protect the wire redistribution pattern 412 on the surface thereof. The fourth B is a modification of the third embodiment, which differs from the third embodiment in that the flexible conductive bump 42 is passed through the front electrical connection hole 411, and the remaining components are The same as the third embodiment. FIG. 5A is a fourth embodiment of the flexible flip-chip structure of the present invention. In a fourth embodiment, the wraparound flip-chip structure comprises a flexible substrate 51, a single or plurality of semiconductor wafers 52, an ancient molecular protective layer 53, and a substrate protective layer 54. The front of the structure ^ 0 has a single or a plurality of electricity through the (four) shape _. = = j = L 511 is distributed in the shape of the front mesa 51. 4 ^ ® ^ ^ , ® (area array) . # ^ arrangement), individual solder joint arrangement or a combination of the above. The surface of one of the above-mentioned 13 1254429 tractable substrates 51 is guided by a redistribution pattern 5l2, and the total # /u·: spring weight distribution pattern (wire redistribution pattern M2 is electrically connected to the above-mentioned = specific =. The bumps of the wafer 52 are earlyly connected to the connection holes 511, so that the semiconductor wafers 52 of the wafers 52 are electrically connected to the flexible substrate 51 of the conductive wiring holes 512 of the flexible substrate 51. The surface has at least one or two, and each of the semi-conductive bumps 52U is provided as a solder joint convex conductive conductive crystal. The flexible portion of the foregoing half-system can be flexible to: the inner connecting surface of the electrical connecting hole 5U The peripheral wall package d material 523. The means for bonding the semiconductor wafer 52 to the sampleable substrate 51 includes a combination of alloy transfer bonding, gluing, and pressing: the semiconductor wafer 52 may be an electronic active element electronic passive component. In the fourth embodiment, the flexible structure can be an ultra-thin flip-chip structure, and the thin wafer 32 and the flexible substrate 3 having a thickness of 50 um can be used. Post-installation thickness It is not more than 〇3 mm (mm). Further, a polymer material layer 524 may be coated on the back surface of the semiconductor wafer 52 as a crystal reinforcing structure to eliminate the semiconductor wafer 52 during processing and deflection. The negative effect of the rupture occurs. The polymer material layer 524 is preferably a porous magnetic material, and the porous property is favorable for dissipating the stress. Further, the polymer protective layer 53 may have a high porosity. The molecular material layer covers the surface of the polymer material layer 524, the semiconductor wafer 52, and the flexible substrate 51 to protect the entire structure. Further, the substrate protection layer 54 is formed on the aforementioned substrate. The lower portion of 51 is used to protect the aforementioned wire redistribution pattern 512. The fifth B is a variation of the fourth embodiment, which differs from the fourth embodiment in the flexible conductive bump 5 thereof. 21 b is through the aforementioned electrical connection hole 511, and the remaining components are the same as the fourth embodiment.
弟五C圖係第四具體實施例的另一變化例，其與第四 具體貫施例的差異係在於其可撓性導電凸塊52ic係具有一 叮才to f生同为子材料做為核心材料522 ’及一導電材料523包 覆整個核心材料522。 第=圖係本發明可撓式覆晶構裝結構的第五具體實施 例。在第五具體實施例中，可挽式覆晶構裝結構6〇包括一 可撓性基板6卜單或複數個半導體晶片幻及一高分子保確 可撓式基板61具有單或複數個貫穿具圓柱形ϊ 連接孔6U。前述電性連接孔611分佈於前述可撓 【基板61所形成的圖案，包含面陣列(_ a，、外圈排 列（peripheral arrangement)、個別焊點排列或以上 合。W述可撓性基板6!相對的兩個表面 ^ = t(W redistr^ , ^Another variation of the fourth embodiment is that the difference between the fourth embodiment and the fourth embodiment is that the flexible conductive bump 52ic has a singularity as a sub-material. Core material 522' and a conductive material 523 encase the entire core material 522. Fig. = is a fifth embodiment of the flexible flip chip structure of the present invention. In a fifth embodiment, the pull-up flip-chip structure 6A includes a flexible substrate 6 or a plurality of semiconductor wafers and a polymer-preservable flexible substrate 61 having a single or a plurality of penetrating substrates 61 With cylindrical ϊ connecting hole 6U. The electrical connection holes 611 are distributed over the flexible pattern formed by the substrate 61, and include a surface array (_a, an outer arrangement, a single solder joint arrangement or a combination of the above). The opposite two surfaces ^ = t(W redistr^ , ^
二，電氣連接於前述電性連^ 將刖述丰導體晶片62的電子 〇U U 611。前述半導體晶片62係安置於虎十於珂述電性連接孔 表面上。每—前述半導體晶片62的性基板61的一 圓柱狀的可撓性導電凸塊621， 力面具有至少一個呈 接觸地貫料述可触基板61 凸塊，其係電性 傳遞前述半導體晶片62與前述性連接孔61卜以 訊號。前述可撓性導電 凸塊621 基ί 61之間的電子 了以可撓性高分子材料 15 1254429 做為核心材料622,其與前述電性連接孔611内壁接觸的阄 壁包覆一導電材料623。前述半導體晶片62接合於前述玎 撓性基板61的手段包含合金回焊接合、膠合、壓合或以上 手段之組合。前述半導體晶片62可以是電子主動^件或電 ^被動元件。在第五具體實施财，前述可撓式覆晶構造 、、、。構60可Μ超薄覆晶構裝結構’其可採用厚度不超過％ t微采（um)的薄型晶片62及可撓性基板61 ’使得整體構裝 後的厚度不超過〇.3毫米（mm)。再者，可於前述半導體晶 片62背面塗覆-高分子材料層624，做為晶片補強結^曰 以消除W述半導體晶片6 2於製程與撓曲時易發生破裂 面效應。前述高分子材料層624較佳是多孔性高分子材料 (:USp〇1ymer material藉其多孔特性以利於消散應力。 i 子保護層63,例如是多孔性高分子材料 、;、二包復前述μ子材料層624、前述半導體晶片62及前 述可撓性基板61表面，以保護整個構裝結構。 *第五具體實補之可撓式覆晶構裝結構6g Μ它且體 二施例不同處f於其可撓性基板61 i的導線重分佈圖案 係分佈於絲㈣的_表面±，前料齡基板= 可藉由其兩表面上的導線重分佈圖案612傳 再者，前述半導體J片62的可撓性導電凸塊6'^也；：有 不同的變化例，如第二A圖、第二B圖、第三c A圖、第四B圖、第五A圖、第五B圖及四 的可撓性導電凸塊結構’前述可撓性基板61的== 611形狀則隨著變化，以達到焊點接觸的目的 低應r的二有產的 性’其適用於任何需求輕薄軟性的產品，例特 16 1254429 可攜式電子紙及無線射頻辨識p (RFID，Radio Frequency Identification)等等。 以上所述僅為本發明之具體實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 1254429 【圖式簡單說明】 第一圖係本發明一傳統覆晶構裝結構截面示意圖； 第二A圖係本發明可撓式覆晶構裝結構的第一具體實 施例的截面示意圖； 第二B圖係第二A圖的變化例的截面示意圖； 第三A圖係本發明可撓式覆晶構裝結構的第二具體實 施例的截面示意圖； 第三B圖係第三A圖的一個變化例的截面示意圖； 第三C圖係第三A圖的另一個變化例的截面示意圖； • 第四A圖係本發明可撓式覆晶構裝結構的第三具體實 施例的截面示意圖； 第四B圖係第四A圖的變化例的截面示意圖； 第五A圖係本發明可撓式覆晶構裝結構的第四具體實 施例的截面示意圖； 第五B圖係第五A圖的一個變化例的截面示意圖； 第五C圖係第五A圖的另一個變化例的截面示意圖； 及 第六圖係本發明可撓式覆晶構裝結構的第五具體實施 @例的截面示意圖。 主要部份之代表符號： 10—軟性基板 12 —晶片 14—焊點凸塊 142 —南分子核心材料 144-—-導電性材料層 20—可挽式覆晶構裝結構 21 可換性基板 22—半導體晶片 24-…基板保護層 18 1254429 23 —南分子保護層 211 —電性連接孔 212-…導線重分佈圖案221a，221b-…可撓性導電凸塊. 222-…高分子材料層 30-…可撓式覆晶構裝結構 31----可挽性基板 32----半導體晶片 33 —南分子保護層 311 —電性連接孔 34-…基板保護層 312 —導線重分佈圖案 321a，321b，321c…-可撓性導電凸塊 鲁 322----核心材料 323----導電材料 324—南分子材料層 40 —可挽式覆晶構裝結構 41 ----可挽性基板 42----半導體晶片 43 南分子保護層 411 電性連接孔 44 ----基板保護層 412----導線重分佈圖案 421a，421b-…可撓性導電凸塊 422—南分子材料層 50 —可挽式覆晶構裝結構 51 ----可挽性基板 52----半導體晶片 53 南分子保護層 511 電性連接孔 54 ----基板保護層 512 —導線重分佈圖案 521a, 521b，521c…·可撓性導電凸塊 522—核心材料 523 —導電材料 524——高分子材料層 60-…可撓式覆晶構裝結構 19 1254429 -半導體晶片 電性連接孔 61 可挽性基板 62— 63 南分子保護層 611 — 612 —導線重分佈圖案 621- …可撓性導電凸塊 --導電材料 622— 核心材料 623-624——高分子材料層 20Second, the electrical connection is made to the electronic 〇U U 611 of the conductive conductor wafer 62. The aforementioned semiconductor wafer 62 is disposed on the surface of the electrical connection hole. Each of the cylindrical flexible conductive bumps 621 of the substrate 72 of the semiconductor wafer 62 has a force surface having at least one bump that contacts the substrate 61 electrically, and electrically transfers the semiconductor wafer 62 The signal is connected to the aforementioned connection hole 61. The electrons between the flexible conductive bumps 621 157 are made of a flexible polymer material 15 1254429 as a core material 622, and the sidewalls of the conductive connecting holes 611 are covered with a conductive material 623. . The means for bonding the semiconductor wafer 62 to the flexible substrate 61 includes alloy reflow bonding, gluing, pressing, or a combination of the above. The aforementioned semiconductor wafer 62 may be an electronic active device or an electro-active component. In the fifth concrete implementation, the flexible flip chip structure, and the above. The structure 60 can be an ultra-thin flip-chip structure, which can adopt a thin wafer 62 having a thickness of not more than % t micron (um) and a flexible substrate 61 ' so that the thickness after the overall assembly does not exceed 〇.3 mm ( Mm). Furthermore, the polymer material layer 624 may be coated on the back surface of the semiconductor wafer 62 as a wafer reinforcement structure to eliminate the occurrence of crack surface effects during the process and deflection of the semiconductor wafer 62. The polymer material layer 624 is preferably a porous polymer material (the USP〇1ymer material has a porous property to facilitate dissipation of the stress. The i-protective layer 63 is, for example, a porous polymer material; The sub-material layer 624, the semiconductor wafer 62 and the surface of the flexible substrate 61 are protected to protect the entire structure. * The fifth specific complement of the flexible flip-chip structure 6g is different from the second embodiment f The wire redistribution pattern on the flexible substrate 61 i is distributed on the surface of the wire (4) ±, the front age substrate = can be transmitted by the wire redistribution pattern 612 on both surfaces, the aforementioned semiconductor J piece Flexible conductive bumps 6' of 62; also have different variations, such as second A, second B, third c A, fourth B, fifth A, fifth B The flexible conductive bump structure of the figure and the fourth 'the shape of the == 611 of the flexible substrate 61 is changed to achieve the purpose of solder joint contact, and the low yield of r should be applied to any demand. Light and soft products, such as 16 1254429 portable electronic paper and radio frequency identification p (RFID, Radio Frequ The above description is only for the specific embodiments of the present invention, and is not intended to limit the scope of the claims of the present invention; any other equivalent changes or modifications made without departing from the spirit of the invention, All of them should be included in the following patent application. 1254429 [Simple description of the drawings] The first figure is a schematic cross-sectional view of a conventional flip-chip structure of the present invention; the second A is a flexible flip-chip structure of the present invention. A cross-sectional view of a first embodiment of the present invention; a third cross-sectional view of a second embodiment of the flexible flip-chip structure of the present invention; 3B is a schematic cross-sectional view of a variation of the third A diagram; the third C is a schematic cross-sectional view of another variation of the third A diagram; • The fourth A diagram is a flexible flip-chip assembly of the present invention. A cross-sectional view of a third embodiment of the structure; a fourth cross-sectional view of a variation of the fourth embodiment; a fifth embodiment of the fourth embodiment of the flexible flip-chip structure of the present invention schematic diagram 5B is a schematic cross-sectional view of a variation of the fifth A diagram; a fifth C diagram is a schematic cross-sectional view of another variation of the fifth A diagram; and the sixth diagram is a flexible flip-chip structure of the present invention. The fifth embodiment is a cross-sectional view of the example. The main part of the symbol: 10 - flexible substrate 12 - wafer 14 - solder bumps 142 - south molecular core material 144 - - conductive material layer 20 - portable Flip-chip structure 21 replaceable substrate 22 - semiconductor wafer 24 - ... substrate protective layer 18 1254429 23 - south molecular protection layer 211 - electrical connection hole 212 - ... wire redistribution pattern 221a, 221b - ... flexible conductive Bumps 222-...Polymer material layer 30-...Flexible flip-chip structure 31----Releasable substrate 32----Semiconductor wafer 33-South molecular protection layer 311-Electrical connection hole 34 - substrate protection layer 312 - wire redistribution pattern 321a, 321b, 321c... - flexible conductive bump 322 - core material 323 - conductive material 324 - south molecular material layer 40 - pullable Flip-Chip Structure 41 ----Producible Substrate 42----Semiconductor Wafer 43 Southern Molecular Protection Layer 411 electrical connection hole 44 ---- substrate protection layer 412 - wire redistribution pattern 421a, 421b - ... flexible conductive bump 422 - south molecular material layer 50 - pullable flip chip structure 51 ----Releasable substrate 52----Semiconductor wafer 53 South molecular protection layer 511 Electrical connection hole 54 ---- Substrate protection layer 512 - Wire redistribution pattern 521a, 521b, 521c...·Flexibility Conductive bump 522 - core material 523 - conductive material 524 - polymer material layer 60 - ... flexible flip chip structure 19 1254429 - semiconductor wafer electrical connection hole 61 traceable substrate 62 - 63 south molecular protection layer 611 - 612 - wire redistribution pattern 621 - ... flexible conductive bump - conductive material 622 - core material 623 - 624 - polymer material layer 20