JP4465891B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4465891B2
JP4465891B2 JP2001030578A JP2001030578A JP4465891B2 JP 4465891 B2 JP4465891 B2 JP 4465891B2 JP 2001030578 A JP2001030578 A JP 2001030578A JP 2001030578 A JP2001030578 A JP 2001030578A JP 4465891 B2 JP4465891 B2 JP 4465891B2
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semiconductor device
electrode
layer
wiring
semiconductor chip
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JP2002231765A (en
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隆一 佐原
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Description

【０００１】
【発明の属する技術分野】
本発明は、配線基板への実装効率を高め、高密度実装を可能にし、信頼性の高い基板実装を実現できるチップ状の半導体装置に関するものであり、特に半導体チップ上で外部端子用の電極パッドが再配線され、外部端子が２次元エリア配置された半導体装置に関するものである。
【０００２】
【従来の技術】
近年、携帯機器の軽量小型化、高密度化にともない、リード端子を外部端子として有した半導体パッケージの高密度実装化が進む中、より高密度実装を図るため、チップ状の半導体装置を電子機器の配線基板等に実装する技術が開発されている。
【０００３】
以下、従来の配線基板への基板実装における半導体装置と、その半導体装置の実装方法について図面を参照しながら説明する。
【０００４】
図７は従来の半導体装置を示す断面図である。
【０００５】
図７に示す従来の半導体装置は、ベアチップ実装に用いられるチップ状の半導体装置であり、その上面内に半導体集積回路が形成された半導体チップ１上の電極パッド（図示せず）上に突起電極２が形成されたものである。そして突起電極２は半導体チップ１の周辺部に形成され、外部との電気的接続のための外部端子を構成するものである。また突起電極２はバンプ、半田ボールなどの導電性金属突起よりなるものである。また図示していないが、半導体チップ１上面の電極パッドを除く表面内には絶縁層が形成されているものである。
【０００６】
次に従来の半導体装置の実装方法について図８を参照しながら説明する。
【０００７】
図７に示したような半導体装置を配線基板上に実装する場合、まず図８（ａ）に示すように、電子機器に組み込むプリント基板等の配線基板３の接続用の配線電極４と半導体装置の半導体チップ１の主面側の突起電極２とを位置合わせする。
【０００８】
そして図８（ｂ）に示すように、配線基板３の配線電極４と半導体装置の突起電極２とを接続する。この際、突起電極２が半田ボールの場合、半田ボールを溶融させた状態で配線基板３の配線電極４と接合する。
【０００９】
そして図８（ｃ）に示すように、配線基板３に半導体装置をその突起電極２が接続された状態に対して、半導体装置の半導体チップ１と配線基板３との間隙に絶縁性樹脂等のアンダーフィル材５を充填封止し、アンダーフィル材５を硬化させて基板実装を完了する。
【００１０】
また別の実装方法として、図９に示すように、配線基板上に予めアンダーフィル材を供給しておき、そのアンダーフィル材を挟み込むように半導体装置を押圧して接続する実装方法もあった。
【００１１】
図９（ａ）に示すように、まず、電子機器に組み込むプリント基板等の配線基板３の配線電極４上に所望の厚みと面積で形成された絶縁性樹脂シートよりなるアンダーフィル材５を貼付する。
【００１２】
そして図９（ｂ）に示すように、配線基板３の配線電極４と半導体装置の突起電極２とを位置合わせし、配線基板３上に供給した絶縁性樹脂シートよりなるアンダーフィル材５を挟み込むように半導体装置をフェースダウンで加熱加圧条件下で押圧し、突起電極２でアンダーフィル材５を突き破り、半導体チップ１の突起電極２を配線電極４と接続させる。
【００１３】
そして図９（ｃ）に示すように、シート状のアンダーフィル材５を硬化させることにより基板実装を完了する。
【００１４】
以上のように従来においては、配線基板の配線電極とベアチップ実装に用いるチップ状の半導体装置とを突起電極を介して接続し、両者の間隙にアンダーフィル材を形成して実装するものであり、アンダーフィル材は両者の接続後または、接続前に予め供給して形成するものであった。
【００１５】
【発明が解決しようとする課題】
しかしながら、前記従来の半導体装置においては、半導体装置の構造として、突起電極が半導体チップの周辺に配置された電極パッド上に設けられたものであり、その電極パッド自体は半導体チップの半導体集積回路素子の領域から外れた周辺領域に形成されているため、電極パッドのチップ面内での２次元エリア配置はできず、半導体装置としての高密度化には限界があった。
【００１６】
そのため最近では、半導体チップの電極パッドを配線で引き回し（再配線）、半導体チップの主面上（半導体集積回路素子上）に２次元エリアで電極パッドと接続したコンタクトパッドを形成したタイプの半導体装置が開発されているが、そのような半導体集積回路素子領域上に電極パッドと接続したコンタクトパッドが形成された半導体装置と配線基板とを接続するには、種々の制約があった。
【００１７】
例えば、配線基板上にシート状またはフィルム状のアンダーフィル材を供給し、そのアンダーフィル材を挟んで半導体装置のコンタクトパッド上に形成した突起電極を押圧して基板実装する場合、加圧力が半導体装置に印加されてしまう。そのためその加圧力により半導体装置のコンタクトパッド下の半導体集積回路素子領域へのダメージが発生するという問題があり、基板実装時の制約を受けていた。また配線基板の配線電極とコンタクトパッドとを接続した後に両者の間隙にアンダーフイル材を充填封止する場合においては、アンダーフィル材内でのボイド発生、また実装後のリペア性に乏しいという制約があった。
【００１８】
また従来の半導体装置の実装方法では、配線基板に対して、１個１個の半導体装置単位で基板実装する必要があるため、基板実装の実装効率上の問題があった。さらに基板実装の際に使用する高精度な実装設備の新規導入による実装コストの増大も問題となっていた。
【００１９】
本発明は前記従来の課題を解決するものであり、高集積の半導体チップを有した高密度実装型の半導体装置であって、配線基板への実装効率を高め、高密度実装を可能にし、信頼性の高い基板実装を実現できる半導体装置を提供することを目的とする。
【００２０】
【課題を解決するための手段】
前記従来の課題を解決するために本発明の半導体装置は、その主面上に複数の電極パッドを有した半導体チップと、前記複数の電極パッドを除く半導体チップの主面上に形成された弾性体層と、前記半導体チップの主面内であって、前記弾性体層上に前記複数の電極パッドと接続した配線層により再配線接続で配置された複数のコンタクトパッドと、前記複数のコンタクトパッドを除く半導体チップの主面上に形成された絶縁性樹脂層と、前記コンタクトパッド上に各々設けられた突起電極と、前記突起電極の頂部を露出させ、前記絶縁性樹脂層に設けられたアンダーフィル材層とよりなる半導体装置であって、前記半導体チップの周辺部のみのアンダーフィル材層の上面は突起電極の頂部よりも上方にある半導体装置である。
【００２１】
また具体的には、突起電極は半田ボールである半導体装置である。
【００２２】
また、アンダーフィル材層はエポキシ樹脂層である半導体装置である。
【００２３】
さらに、弾性体層の端部は、断面形状において斜辺を構成している半導体装置である。
【００２４】
前記構成の通り、弾性体層上に配線層と接続したコンタクトパッドが形成されているので、マザー・ボードなどの配線基板への実装後に、配線基板と半導体装置との熱膨張率差によって接続部に加わる応力が弾性体層の弾性によって吸収される。すなわち、応力の緩和機能の高い半導体装置を実現することができる。また、配線層の一部に大きな集中応力の印加が回避されるので、配線層の断線等を防止することができ、半導体装置の信頼性が向上する。さらに半導体装置として基板実装時に要するアンダーフィル材を有しているので、より効率的で信頼性の高い基板実装を実現できる半導体装置である。特に半導体装置の周辺部には厚みの厚いアンダーフィル材層を配置しているので、基板実装時のフィレット部を効率よく形成でき、信頼性の高い基板実装を実現できる。
【００２５】
【発明の実施の形態】
以下、本発明の半導体装置およびその製造方法ならびに半導体装置の実装方法の一実施形態について、図面を参照しながら説明する。
【００２６】
まず本実施形態の半導体装置について説明する。
【００２７】
図１は本実施形態の半導体装置の前提構造を示すチップ状の電極再配線型の半導体装置を示す図である。図１において、図１（ａ）は斜視図であり、図１（ｂ）は図１（ａ）でのＡ−Ａ１箇所の断面図である。なお、図１（ａ）では視覚便宜上、一部の構成に斜線を付している。
【００２８】
図１に示すように、本実施形態の半導体装置の前提構造としては、一主面上の周辺領域に内部の半導体集積回路素子と接続した複数の電極パッド６を有した半導体チップ７と、各電極パッド６を除く半導体チップ７の主面領域上に形成された低弾性樹脂よりなる弾性体層８と、半導体チップ７の主面内であって、形成された弾性体層８上に各電極パッド６と接続した金属導体よりなる配線層９により再配線接続で２次元配置された複数のコンタクトパッド１０と、それらコンタクトパッド１０を除く半導体チップ７の主面上に形成され、電極パッド６、配線層９を保護したソルダーレジストなどの絶縁性樹脂層１１と、コンタクトパッド１０上に各々設けられた半田ボールなどの突起電極１２より構成されている。
【００２９】
そして本実施形態の半導体装置は図２（ａ）の断面図に示すように、図１に示した構造において、コンタクトパッド１０上の突起電極１２の頂部を露出させ、絶縁性樹脂層１１上に設けられたアンダーフィル材層１３を有した構造である。
【００３０】
本実施形態において、アンダーフィル材層１３の上面は突起電極１２の頂部と実質的同一面にあるものであるが、基板実装の際の実装方法如何によっては、突起電極１２の頂部はアンダーフィル材層１３の上面から１［μｍ］〜２００［μｍ］、好ましくは５０［μｍ］で突出して露出した構造としてもよい。
【００３１】
さらに図２（ｂ）に示すように、半導体チップ７の周辺部であって、コンタクトパッド１０のうちの最外周のコンタクトパッドより外方部分のアンダーフィル材層１３の上面は突起電極１２の頂部よりも上方になるように膜厚を厚く調整することにより、基板実装した際、配線基板と半導体装置との間隙の気密封止とともに、アンダーフィル材によるフィレット部を形成でき、実装信頼性を高めることができる。
【００３２】
また本実施形態では、突起電極１２は半田ボールとしているが、金属材料によるバンプ状の突起電極でもよい。
【００３３】
また、弾性体層８は弾性率（ヤング率）として１０〜２０００［ｋｇ／ｍｍ2］の範囲にあることが好ましく、さらに１０〜１０００［ｋｇ／ｍｍ2］ の範囲にあることがより好ましい。また、弾性体層８の線膨張率は５〜２００［ｐｐｍ／℃］の範囲にあることが好ましく、さらに１０〜１００［ｐｐｍ／℃］の範囲にあることがより好ましい。例えばエステル結合型ポリイミドやアクリレート系エポキシ等のポリマーでよく、低弾性率を有し、絶縁性であればよい。またその厚みとしては、１〜１００［μｍ］であり、好ましくは３０［μｍ］である。
【００３４】
そして、弾性体層８の端部は、図１，図２に示すように、断面形状において斜辺を構成しているものであり、これにより電極パッド６の引き回しで使用する配線層９の形成精度と、断線防止などの信頼性を高めることができる。
【００３５】
また、アンダーフィル材層１３はエポキシ樹脂により形成されているものであり、基板実装した際に気密封止が可能で絶縁性の材料であればよい。
【００３６】
さらに本実施形態の半導体装置において、弾性体層８としては弾性を有する樹脂の他、基板実装の際の実装方法如何によっては、５［μｍ］厚以上のポリイミドなどの絶縁層でもよい。
【００３７】
本実施形態の半導体装置によると、半導体装置として基板実装時に要するアンダーフィル材層１３を有しているので、より効率的で信頼性の高い基板実装を実現できる半導体装置である。
【００３８】
また、下地となる弾性体層８の上に配線層９を設けているので、半導体装置をプリント基板等の配線基板上に実装する際などにおいて、半導体装置の加熱・冷却に伴い配線層９に熱応力などの応力が印加されても、配線層９に加わる応力が緩和される。よって、基板実装時などにおける配線層９の断線を防止することができ、信頼性の高い配線構造を実現することができる。
【００３９】
そして、半導体装置の主面上に二次元的に外部端子となるコンタクトパッド１０が配置されているので、狭い面積に多数の外部端子を設けることが可能となるとともに、パターン形成可能な配線層９により電極パッド６とコンタクトパッド１０と接続することができる構造である。したがって、小型で薄型の半導体装置であり、かつ多ピン化に対応できる半導体装置である。しかも微細加工に適し、多ピン化に対応できる半導体装置である。
【００４０】
さらに、配線層９につながるコンタクトパッド１０の上に半田ボールなどの突起電極１２が設けられ、配線基板に半導体装置を搭載する工程が極めて簡易かつ迅速に行なうことができる構造となっているが、その際にも、弾性体層８により、大きな熱容量を有する半田ボールから発生する熱応力を吸収できる。
【００４１】
次に本実施形態の半導体装置の製造方法について説明する。図３，図４は本実施形態の半導体装置の製造方法を示す主要工程ごとの断面図である。
【００４２】
まず図３（ａ）に示すように、一主面上の周辺部に複数の電極パッド６が形成され、半導体集積回路素子が形成された半導体チップ７を用意する。なお、チップ単位ではなく、半導体チップがその面内に複数個形成された半導体ウェハを用意し、ウェハレベルで製造してもよく、より量産レベルでの製造が可能になる。
【００４３】
次に図３（ｂ）に示すように、用意した半導体チップ７、または半導体ウェハ内の各半導体チップの主面上であって、周辺の複数の電極パッド６を除く主面領域を覆うように低弾性材料により弾性体層８を形成する。
【００４４】
具体的には、まず半導体チップ７の主面にそれぞれ形成された電極パッド６とパッシベーション膜（図示せず）との上に、感光性を有する絶縁性の低弾性材料を１００［μｍ］程度の厚みで塗布して乾燥することにより弾性体層膜を形成する。そして乾燥された弾性体層膜に対して露光と現像とを順次行って、半導体チップ７の電極パッド６の部分を開口させた弾性体層８を形成する。この場合において、例えば露光で平行光ではなく散乱光を使用して、開口部における弾性体層８の断面形状を、半導体チップ７の主面に対して垂直ではなく鋭角部分のない斜辺状にして形成する。本実施形態では、弾性体層８の開口の端部を傾斜させて半導体チップ７の表面になめらかにつながるように形成することにより、配線層９を形成しやすく、また断線しにくい構造を構成することができる。
【００４５】
なお、半導体装置を基板実装した際の熱応力を軽減するためには弾性体層８の厚みは、塗布以降の工程に支障のない範囲で厚い方が良く、例えば５００［μｍ］程度でも良いし１［ｍｍ］程度でも良い。また、感光性を有する低弾性材料としては、例えばエステル結合型ポリイミドやアクリレート系エポキシ等のポリマーでよく、低弾性率を有し、絶縁性であればよい。また、感光性を有する低弾性材料は液状材料を乾燥させて形成する必要はなくフィルム状に予め形成された材料を用いても構わない。その場合には、フィルム状の低弾性材料を半導体チップ７上に貼り合わせ、露光、現像することで低弾性材料に開口部を形成することができ、半導体チップ７上の電極パッド６を露出させることができる。さらに、弾性体層８を構成する絶縁性の低弾性材料が感光性を有する必要はない。感光性を有しない材料を用いる場合には、レーザーやプラズマによる機械的な加工もしくはエッチングなどの化学的加工により、半導体チップ７上の電極パッド６を露出させることができる。
【００４６】
次に図３（ｃ）に示すように、半導体チップ７の主面上において、一端を電極パッド６と接続させ、他端を形成した弾性体層８上に延在させ、２次元配置でコンタクトパッド１０を構成する配線層９を形成する。
【００４７】
具体的には、まず半導体チップ７の主面において、真空蒸着法、スパッタリング法、ＣＶＤ法又は無電解めっき法によって例えば厚みが０．２［μｍ］程度のチタン（Ｔｉ）膜とその上に形成された厚みが０．５［μｍ］程度の銅（Ｃｕ）膜からなる薄膜金属層を形成する。そして形成した薄膜金属層上にネガ型感光性レジストを塗布し、仕上げ製品の所望のパターン部以外を硬化し、反応部を除去することでメッキレジスト膜を形成する。ここではメッキレジスト膜を形成する際にネガ型感光性レジストを用いたが、ポジ型感光性レジストを用いてもよいことは言うまでもない。そして電解めっき法により、メッキレジスト膜が形成された箇所以外の薄膜金属層の上に、例えばＣｕ膜からなる厚膜金属層を例えば２０［μｍ］程度の厚みで選択的に形成する。そして厚膜金属層の形成後、メッキレジスト膜を溶融除去する。そして薄膜金属層と厚膜金属層とを溶融することのできるエッチング液、例えばＣｕ膜に対しては塩化第二銅溶液で、Ｔｉ膜に対してはＥＤＴＡ溶液で全面エッチングすると、厚膜金属層よりも層厚が薄い薄膜金属層が先行して除去される。この工程によって、半導体チップ７の主面において、電極パッド６と配線層９とコンタクトパッド１０とからなる所定の金属配線パターンを形成することができる。
【００４８】
なお、薄膜金属層や厚膜金属層を構成する材料としてＣｕを使用したが、これに代えてＣｒ、Ｗ、Ｔｉ／Ｃｕ、Ｎｉ等を使用してもよい。また、薄膜金属層と厚膜金属層とをそれぞれ異なる金属材料により構成しておき、最終的なエッチング工程では薄膜金属層のみを選択的にエッチングするエッチャントを用いてもよい。
【００４９】
次に図３（ｄ）に示すように、半導体チップ７の主面上であって、形成したコンタクトパッド１０を除いて少なくとも配線層９、電極パッド６を絶縁性樹脂で被覆して絶縁性樹脂層１１を形成する。
【００５０】
具体的には、弾性体層８の上に感光性ソルダーレジスト（絶縁性樹脂）を塗布した後に、フォトリソグラフィー技術を使用して、コンタクトパッド１０の部分のみが露出するようにしてソルダーレジスト膜（絶縁性樹脂層１１）を形成する。このソルダーレジスト膜によって、コンタクトパッド１０以外の部分である電極パッド６と配線層９とが、実装時の溶融した半田から保護される。
【００５１】
次に図４（ａ）に示すように、半導体チップ７上のコンタクトパッド１０上に導電性材料により突起電極１２を形成する。
【００５２】
具体的には、半田、半田めっきされた銅、ニッケル等からなる金属ボールをコンタクトパッド１０の上に載置して、金属ボールとコンタクトパッド１０とを溶融接合して突起電極１２を形成する。
【００５３】
そして図４（ｂ）に示すように、半導体チップ７の主面上であって、コンタクトパッド１０上の突起電極１２の頂部を露出させてアンダーフィル材層１３を形成する。本実施形態では、アンダーフィル材層１３の上面は突起電極１２の頂部と実質的同一面にしているが、突起電極１２の頂部をアンダーフィル材層１３の上面から１［μｍ］〜２００［μｍ］の範囲、好ましくは５０［μｍ］で突出させるようにしてもよい。突起電極１２の頂部をアンダーフィル材層１３面より突出させることにより、基板実装時には、押圧により配線基板の配線電極に突起電極を食い込ませ、かつアンダーフィル材層を配線基板側に密着させることができるので、両者の間隙の気密封止ができるものである。
【００５４】
さらにアンダーフィル材層１３において、半導体チップ７の周辺部であって、コンタクトパッド１０のうちの最外周のコンタクトパッドより外方部分のアンダーフィル材層１３の上面は突起電極１２の頂部よりも上方になるように膜厚を調整することにより、基板実装した際、配線基板と半導体装置との間隙の気密封止とともに、アンダーフィル材によるフィレット部を形成でき、実装信頼性を高めることができる。
【００５５】
具体的には、半導体チップ７上の絶縁性樹脂層１１上にアンダーフィル材料を塗布した後に、フォトリソグラフィー技術やエッチング技術を使用して、コンタクトパッド１０の頂部が露出するようにしてアンダーフィル材層１３を形成する。ここではアンダーフィル材層の材料として、エポキシ樹脂を用いる。
【００５６】
以上のような工程により、基板実装に適したチップ状で高密度タイプの半導体装置を実現できる。
【００５７】
なお、前述の通り、本実施形態では半導体チップでの製造過程を説明したが、主面上に電極パッドが形成された半導体チップを用意する工程は、その面内に半導体チップが複数個形成された半導体ウェハとして用意し、半導体ウェハ単位で製造してもよい。これにより、半導体チップに分割される前の半導体ウェハのままで、多数の半導体チップ領域における弾性体層や配線層などが形成されるので、製造コストを大幅に低減することができる。
【００５８】
次に本実施形態の半導体装置の実装方法について説明する。図５は本実施形態の半導体装置の実装方法を示す主要工程ごとの断面図である。
【００５９】
まず図５（ａ）に示すように、主面上に複数の電極パッド６を有した半導体チップ７と、電極パッド６を除く半導体チップ７の主面上に形成された弾性体層８と、半導体チップ７の主面内であって、弾性体層８上に各電極パッド６と接続した配線層９により再配線配置で２次元配置された複数のコンタクトパッド１０と、複数のコンタクトパッド１０を除く半導体チップ７の主面上に形成された絶縁性樹脂層１１と、コンタクトパッド１０上に各々設けられた突起電極１２と、突起電極１２の頂部を露出させ、絶縁性樹脂層１１上に設けられたアンダーフィル材層１３とよりなる半導体装置の主面側と、配線電極１４を有した配線基板１５の配線電極面側とを対向させ、電極どうしを位置合わせする。
【００６０】
次に図５（ｂ）に示すように、半導体装置の突起電極１２と配線基板１５の配線電極１４とを当接させる。
【００６１】
さらに、アンダーフィル材層１３から露出した突起電極１２の頂部を配線基板１５の配線電極１４に押圧して食い込ませて当接させることで、より信頼性の高い接続を得ることができる。
【００６２】
そして図５（ｃ）に示すように、半導体装置のアンダーフィル材層１３を加熱により軟化溶融させ、半導体装置の主面と配線基板１５の主面との間隙をアンダーフィル材層１３で充填封止して基板実装を完了する。加熱条件としては、１５０［℃］で加熱することによりアンダーフィル材層１３を軟化溶融させ、間隙にボイドなく充填できる。
【００６３】
本実施形態の半導体装置の実装方法により、アンダーフィル材層１３を有した半導体装置を配線基板１５の配線電極１４と当接させ、アンダーフィル材層１３を加熱処理するだけで、電極どうしの電気的な接続と封止を行うことができ、高効率で信頼性の高い基板実装を実現することができる。
【００６４】
次に他の実施形態の半導体装置の実装方法について説明する。図６は他の実施形態にかかる半導体装置の実装方法を示す主要工程ごとの断面図である。なお、本実施形態で実装する半導体装置としては前記の図１で示した構造の半導体装置を例として説明する。
【００６５】
まず図６（ａ）に示すように、配線電極１４を有した配線基板１５の電極形成面上にアンダーフィルシート１６を貼付する。ここで貼付するアンダーフィルシート１６の厚みと面積は実装する半導体装置の面積と突起電極の高さに応じて設定する。
【００６６】
次に図６（ｂ）に示すように、主面上に複数の電極パッド６を有した半導体チップ７と、電極パッド６を除く半導体チップ７の主面上に形成された弾性体層８と、半導体チップ７の主面内であって、弾性体層８上に各電極パッド６と接続した配線層９により再配線配置で２次元配置された複数のコンタクトパッド１０と、複数のコンタクトパッド１０を除く半導体チップ７の主面上に形成された絶縁性樹脂層１１と、コンタクトパッド１０上に各々設けられた突起電極１２とよりなる半導体装置の主面側と、アンダーフィルシート１６が貼付された配線基板１５の配線電極１４面側とを対向させ、電極どうしを位置合わせする。
【００６７】
そして図６（ｃ）に示すように、半導体装置をその背面から押圧し、突起電極１２と配線基板１５の配線電極１４とを接続するとともに、両者の間隙にアンダーフィルシート１６を挟み込んで実装する。この場合、突起電極１２によりアンダーフィルシート１６を突き破って配線基板１５上の配線電極１４と接続させるものである。
【００６８】
以上のように、基板実装する半導体装置として、接続すべき突起電極１２と半導体チップの半導体集積回路素子領域との間には弾性体層が介在しているため、実装時の押圧力によって素子が破壊することを防止し、効率よく実装できるものである。
【００６９】
以上の通り、本実施形態の半導体装置は、弾性体層上に配線層と接続したコンタクトパッドが形成されているので、マザー・ボードなどの配線基板への実装後に、配線基板と半導体装置との熱膨張率差によって接続部に加わる応力が弾性体層の弾性によって吸収される。すなわち、応力の緩和機能の高い半導体装置を実現することができる。さらに半導体装置として基板実装時に要するアンダーフィル材を有しているので、より効率的で信頼性の高い基板実装を実現できる半導体装置である。特に半導体装置の周辺部には厚みの厚いアンダーフィル材層を配置しているので、基板実装時のフィレット部を効率よく形成でき、信頼性の高い基板実装を実現できる。
【００７０】
また、本実施形態の半導体装置の製造方法は、基板実装に適したチップ状で高密度タイプの半導体装置を実現できる。
【００７１】
そしてアンダーフィル材層を有した半導体装置を配線基板の配線電極と当接させ、アンダーフィル材を加熱処理することにより、高効率で信頼性の高い基板実装を実現することができる。
【００７２】
【発明の効果】
本発明の半導体装置は、半導体ウェハ状で形成可能な構造を有し、小型で薄型の半導体装置であり、また従来のようにリードによる電極の接続ではなく、金属配線層により電極と接続するものであるため、微細加工に適し、多ピン化に対応できる半導体装置である。さらに弾性体層を下地として、その上に外部電極と一体化された配線層が形成されているため、配線層の断線を防止し、また外部電極の熱応力を緩衝でき、基板実装時の接合の信頼性を向上することができる。そして何よりも基板実装時に要するアンダーフィル材を有しているので、より効率的で信頼性の高い基板実装を実現できる半導体装置である。特に半導体装置の周辺部には厚みの厚いアンダーフィル材層を配置しているので、基板実装時のフィレット部を効率よく確実に形成でき、信頼性の高い基板実装を実現できる。
【図面の簡単な説明】
【図１】本発明の一実施形態の半導体装置を示す図
【図２】本発明の一実施形態の半導体装置を示す断面図
【図３】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図４】本発明の一実施形態の半導体装置の製造方法を示す断面図
【図５】本発明の一実施形態の半導体装置の実装方法を示す断面図
【図６】本発明の一実施形態の半導体装置の実装方法を示す断面図
【図７】従来の半導体装置を示す断面図
【図８】従来の半導体装置の実装方法を示す断面図
【図９】従来の半導体装置の実装方法を示す断面図
【符号の説明】
１ 半導体チップ
２ 突起電極
３ 配線基板
４ 配線電極
５ アンダーフィル材
６ 電極パッド
７ 半導体チップ
８ 弾性体層
９ 配線層
１０ コンタクトパッド
１１ 絶縁性樹脂層
１２ 突起電極
１３ アンダーフィル材層
１４ 配線電極
１５ 配線基板
１６ アンダーフィルシート[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip-like semiconductor device capable of increasing mounting efficiency on a wiring board, enabling high-density mounting, and realizing highly reliable board mounting, and more particularly, electrode pads for external terminals on a semiconductor chip. Relates to a semiconductor device in which the wiring is rewired and the external terminals are arranged in a two-dimensional area.
[0002]
[Prior art]
In recent years, with the reduction in weight and size and the increase in density of portable devices, semiconductor packages having lead terminals as external terminals are being mounted with higher density. A technology for mounting on a wiring board or the like has been developed.
[0003]
Hereinafter, a semiconductor device in a conventional substrate mounting on a wiring board and a method for mounting the semiconductor device will be described with reference to the drawings.
[0004]
FIG. 7 is a cross-sectional view showing a conventional semiconductor device.
[0005]
The conventional semiconductor device shown in FIG. 7 is a chip-like semiconductor device used for bare chip mounting, and a protruding electrode is formed on an electrode pad (not shown) on the semiconductor chip 1 on which a semiconductor integrated circuit is formed. 2 is formed. The protruding electrode 2 is formed on the periphery of the semiconductor chip 1 and constitutes an external terminal for electrical connection with the outside. The protruding electrode 2 is made of conductive metal protrusions such as bumps and solder balls. Although not shown, an insulating layer is formed in the surface excluding the electrode pads on the upper surface of the semiconductor chip 1.
[0006]
Next, a conventional method for mounting a semiconductor device will be described with reference to FIG.
[0007]
When the semiconductor device as shown in FIG. 7 is mounted on the wiring board, first, as shown in FIG. 8A, the wiring electrode 4 for connecting the wiring board 3 such as a printed board incorporated in the electronic apparatus and the semiconductor device The protruding electrode 2 on the main surface side of the semiconductor chip 1 is aligned.
[0008]
Then, as shown in FIG. 8B, the wiring electrode 4 of the wiring substrate 3 and the protruding electrode 2 of the semiconductor device are connected. At this time, when the protruding electrode 2 is a solder ball, the solder electrode is joined to the wiring electrode 4 of the wiring board 3 in a melted state.
[0009]
Then, as shown in FIG. 8C, with respect to the state in which the bump electrode 2 is connected to the semiconductor device on the wiring substrate 3, an insulating resin or the like is provided in the gap between the semiconductor chip 1 and the wiring substrate 3 of the semiconductor device. The underfill material 5 is filled and sealed, and the underfill material 5 is cured to complete the substrate mounting.
[0010]
As another mounting method, as shown in FIG. 9, there is a mounting method in which an underfill material is supplied in advance onto a wiring board and the semiconductor device is pressed and connected so as to sandwich the underfill material.
[0011]
As shown in FIG. 9A, first, an underfill material 5 made of an insulating resin sheet formed with a desired thickness and area is pasted on a wiring electrode 4 of a wiring board 3 such as a printed board incorporated in an electronic device. To do.
[0012]
9B, the wiring electrode 4 of the wiring board 3 and the protruding electrode 2 of the semiconductor device are aligned, and the underfill material 5 made of an insulating resin sheet supplied onto the wiring board 3 is sandwiched between them. In this way, the semiconductor device is pressed face down under heat and pressure conditions, the underfill material 5 is pierced by the protruding electrode 2, and the protruding electrode 2 of the semiconductor chip 1 is connected to the wiring electrode 4.
[0013]
Then, as shown in FIG. 9C, the substrate mounting is completed by curing the sheet-like underfill material 5.
[0014]
As described above, in the past, the wiring electrode of the wiring board and the chip-like semiconductor device used for bare chip mounting are connected via the protruding electrode, and the underfill material is formed in the gap between the two and mounted. The underfill material was formed by supplying in advance after the connection between the two or before the connection.
[0015]
[Problems to be solved by the invention]
However, in the conventional semiconductor device, as the structure of the semiconductor device, the protruding electrode is provided on the electrode pad arranged around the semiconductor chip, and the electrode pad itself is a semiconductor integrated circuit element of the semiconductor chip. Since the electrode pad is formed in a peripheral region that is out of the region, the two-dimensional area arrangement in the chip surface of the electrode pad cannot be performed, and there is a limit to increasing the density as a semiconductor device.
[0016]
Therefore, recently, a semiconductor device of a type in which electrode pads of a semiconductor chip are routed by wiring (rewiring), and contact pads connected to the electrode pads in a two-dimensional area are formed on the main surface of the semiconductor chip (on the semiconductor integrated circuit element). However, there are various restrictions in connecting a semiconductor device in which a contact pad connected to an electrode pad is formed on such a semiconductor integrated circuit element region and a wiring board.
[0017]
For example, when mounting a substrate by pressing a protruding electrode formed on a contact pad of a semiconductor device by supplying a sheet-like or film-like underfill material on a wiring board and sandwiching the underfill material, the applied pressure is a semiconductor It will be applied to the device. For this reason, there is a problem that damage to the semiconductor integrated circuit element region under the contact pad of the semiconductor device occurs due to the applied pressure. In addition, when the wiring electrode of the wiring board is connected to the contact pad and the gap between the two is filled with an underfill material, there is a restriction that voids are generated in the underfill material and repairability after mounting is poor. there were.
[0018]
Further, in the conventional semiconductor device mounting method, it is necessary to mount the substrate in units of one semiconductor device on the wiring substrate, and thus there is a problem in mounting efficiency of the substrate mounting. Furthermore, an increase in mounting cost due to the introduction of high-precision mounting equipment used for board mounting has also been a problem.
[0019]
The present invention solves the above-mentioned conventional problems, and is a high-density mounting type semiconductor device having a highly integrated semiconductor chip, which improves mounting efficiency on a wiring board, enables high-density mounting, and is reliable. It is an object of the present invention to provide a semiconductor device capable of realizing highly efficient substrate mounting.
[0020]
[Means for Solving the Problems]
In order to solve the above-described conventional problems, a semiconductor device according to the present invention includes a semiconductor chip having a plurality of electrode pads on its main surface, and an elasticity formed on the main surface of the semiconductor chip excluding the plurality of electrode pads. A plurality of contact pads disposed in a rewiring connection by a wiring layer connected to the plurality of electrode pads on the elastic layer, the plurality of contact pads being within a main surface of the semiconductor chip; Insulating resin layer formed on the main surface of the semiconductor chip excluding, a protruding electrode provided on each of the contact pads, and an underside provided on the insulating resin layer exposing the top of the protruding electrode A semiconductor device comprising a fill material layer, wherein the upper surface of the underfill material layer only at the periphery of the semiconductor chip is above the top of the bump electrode.
[0021]
More specifically, the protruding electrode is a semiconductor device that is a solder ball.
[0022]
The underfill material layer is a semiconductor device that is an epoxy resin layer.
[0023]
Further, the end portion of the elastic layer is a semiconductor device that forms a hypotenuse in the cross-sectional shape.
[0024]
As described above, since the contact pad connected to the wiring layer is formed on the elastic body layer, the connection portion is formed by the difference in thermal expansion coefficient between the wiring board and the semiconductor device after mounting on the wiring board such as a mother board. The stress applied to is absorbed by the elasticity of the elastic layer. That is, a semiconductor device having a high stress relaxation function can be realized. In addition, since application of a large concentrated stress to a part of the wiring layer is avoided, disconnection of the wiring layer can be prevented and the reliability of the semiconductor device is improved. Furthermore, since the semiconductor device has an underfill material required for substrate mounting, the semiconductor device can realize more efficient and reliable substrate mounting. In particular, since a thick underfill material layer is disposed in the peripheral portion of the semiconductor device, a fillet portion can be efficiently formed at the time of substrate mounting, and highly reliable substrate mounting can be realized.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a semiconductor device, a manufacturing method thereof, and a mounting method of the semiconductor device of the invention will be described with reference to the drawings.
[0026]
First, the semiconductor device of this embodiment will be described.
[0027]
FIG. 1 is a diagram showing a chip-like electrode rewiring type semiconductor device showing a premise structure of the semiconductor device of the present embodiment. 1A is a perspective view, and FIG. 1B is a cross-sectional view taken along the line A-A1 in FIG. 1A. In FIG. 1A, some components are hatched for the sake of visual convenience.
[0028]
As shown in FIG. 1, the premise structure of the semiconductor device of this embodiment includes a semiconductor chip 7 having a plurality of electrode pads 6 connected to an internal semiconductor integrated circuit element in a peripheral region on one main surface, An elastic body layer 8 made of a low elastic resin formed on the main surface region of the semiconductor chip 7 excluding the electrode pad 6, and each electrode on the formed elastic body layer 8 in the main surface of the semiconductor chip 7. A plurality of contact pads 10 two-dimensionally arranged by rewiring connection by a wiring layer 9 made of a metal conductor connected to the pads 6, and formed on the main surface of the semiconductor chip 7 excluding the contact pads 10, An insulating resin layer 11 such as a solder resist that protects the wiring layer 9 and projecting electrodes 12 such as solder balls provided on the contact pads 10 are formed.
[0029]
As shown in the cross-sectional view of FIG. 2A, the semiconductor device of this embodiment has the structure shown in FIG. 1 with the tops of the protruding electrodes 12 on the contact pads 10 exposed, and on the insulating resin layer 11. This is a structure having an underfill material layer 13 provided.
[0030]
In the present embodiment, the upper surface of the underfill material layer 13 is substantially flush with the top of the protruding electrode 12, but the top of the protruding electrode 12 depends on the mounting method during substrate mounting. It may have a structure that protrudes from the upper surface of the layer 13 at 1 [μm] to 200 [μm], preferably 50 [μm], and is exposed.
[0031]
Further, as shown in FIG. 2B, the upper surface of the underfill material layer 13 in the periphery of the semiconductor chip 7 and outside the outermost contact pad of the contact pads 10 is the top of the protruding electrode 12. By adjusting the film thickness so as to be higher than the upper limit, when the substrate is mounted, the gap between the wiring board and the semiconductor device can be hermetically sealed, and a fillet portion can be formed by an underfill material, thereby improving mounting reliability. be able to.
[0032]
In the present embodiment, the bump electrode 12 is a solder ball, but may be a bump-like bump electrode made of a metal material.
[0033]
The elastic layer 8 has an elastic modulus (Young's modulus) of 10 to 2000 [kg / mm. 2 ], Preferably in the range of 10 to 1000 [kg / mm 2 ] Is more preferable. The linear expansion coefficient of the elastic body layer 8 is preferably in the range of 5 to 200 [ppm / ° C.], and more preferably in the range of 10 to 100 [ppm / ° C.]. For example, it may be a polymer such as an ester bond type polyimide or an acrylate epoxy, and may have a low elastic modulus and an insulating property. Moreover, as the thickness, it is 1-100 [micrometers], Preferably it is 30 [micrometers].
[0034]
As shown in FIGS. 1 and 2, the end portion of the elastic body layer 8 forms a hypotenuse in the cross-sectional shape, thereby forming the wiring layer 9 used for routing the electrode pad 6. And reliability, such as disconnection prevention, can be improved.
[0035]
The underfill material layer 13 is formed of an epoxy resin and may be any insulating material that can be hermetically sealed when mounted on a substrate.
[0036]
Furthermore, in the semiconductor device of this embodiment, the elastic layer 8 may be an insulating layer such as polyimide having a thickness of 5 [μm] or more, depending on the mounting method when mounting the substrate, in addition to an elastic resin.
[0037]
According to the semiconductor device of the present embodiment, since the semiconductor device has the underfill material layer 13 required for mounting the substrate, the semiconductor device can realize more efficient and reliable substrate mounting.
[0038]
In addition, since the wiring layer 9 is provided on the elastic body layer 8 serving as a base, when the semiconductor device is mounted on a wiring substrate such as a printed circuit board, the wiring layer 9 is formed along with heating / cooling of the semiconductor device. Even when a stress such as a thermal stress is applied, the stress applied to the wiring layer 9 is relaxed. Therefore, disconnection of the wiring layer 9 at the time of mounting on the substrate can be prevented, and a highly reliable wiring structure can be realized.
[0039]
Since the contact pads 10 that are two-dimensionally provided as external terminals are arranged on the main surface of the semiconductor device, a large number of external terminals can be provided in a small area, and a pattern-forming wiring layer 9 can be formed. Thus, the electrode pad 6 and the contact pad 10 can be connected. Therefore, the semiconductor device is a small and thin semiconductor device and can cope with an increase in the number of pins. In addition, the semiconductor device is suitable for microfabrication and can cope with the increase in pin count.
[0040]
Furthermore, a protruding electrode 12 such as a solder ball is provided on the contact pad 10 connected to the wiring layer 9, and the structure for mounting the semiconductor device on the wiring board is extremely simple and quick. Also in that case, the elastic body layer 8 can absorb the thermal stress generated from the solder ball having a large heat capacity.
[0041]
Next, a method for manufacturing the semiconductor device of this embodiment will be described. 3 and 4 are cross-sectional views for each main process showing the method of manufacturing the semiconductor device of this embodiment.
[0042]
First, as shown in FIG. 3A, a semiconductor chip 7 is prepared in which a plurality of electrode pads 6 are formed in a peripheral portion on one main surface and a semiconductor integrated circuit element is formed. It should be noted that a semiconductor wafer having a plurality of semiconductor chips formed on the surface thereof instead of a chip unit may be prepared and manufactured at the wafer level, and manufacture at a mass production level becomes possible.
[0043]
Next, as shown in FIG. 3B, on the main surface of the prepared semiconductor chip 7 or each semiconductor chip in the semiconductor wafer so as to cover the main surface region excluding the peripheral electrode pads 6. The elastic layer 8 is formed from a low elastic material.
[0044]
Specifically, first, an insulating low elastic material having photosensitivity is set to about 100 [μm] on the electrode pad 6 and the passivation film (not shown) respectively formed on the main surface of the semiconductor chip 7. The elastic body layer film is formed by applying and drying in thickness. Then, exposure and development are sequentially performed on the dried elastic layer film to form the elastic layer 8 in which the electrode pad 6 portion of the semiconductor chip 7 is opened. In this case, the cross-sectional shape of the elastic body layer 8 in the opening is not perpendicular to the main surface of the semiconductor chip 7 but has an acute angle portion, for example, using scattered light instead of parallel light in exposure. Form. In the present embodiment, the end of the opening of the elastic layer 8 is inclined so as to be smoothly connected to the surface of the semiconductor chip 7, thereby forming a structure in which the wiring layer 9 can be easily formed and is not easily broken. be able to.
[0045]
In order to reduce the thermal stress when the semiconductor device is mounted on the substrate, the thickness of the elastic body layer 8 is preferably thick as long as it does not interfere with the steps after the application, for example, about 500 [μm]. It may be about 1 [mm]. The low-elasticity material having photosensitivity may be, for example, a polymer such as ester-bonded polyimide or acrylate-based epoxy, and may have a low elastic modulus and insulation. The low-elasticity material having photosensitivity does not need to be formed by drying a liquid material, and a material previously formed in a film shape may be used. In that case, an opening can be formed in the low elastic material by laminating a film-like low elastic material on the semiconductor chip 7, exposing and developing, and the electrode pads 6 on the semiconductor chip 7 are exposed. be able to. Furthermore, the insulating low-elasticity material constituting the elastic body layer 8 does not have to be photosensitive. When a material that does not have photosensitivity is used, the electrode pad 6 on the semiconductor chip 7 can be exposed by chemical processing such as mechanical processing or etching using laser or plasma.
[0046]
Next, as shown in FIG. 3C, on the main surface of the semiconductor chip 7, one end is connected to the electrode pad 6, and the other end is extended on the elastic body layer 8 so as to be contacted in a two-dimensional arrangement. A wiring layer 9 constituting the pad 10 is formed.
[0047]
Specifically, first, on the main surface of the semiconductor chip 7, for example, a titanium (Ti) film having a thickness of about 0.2 [μm] is formed on the main surface of the semiconductor chip 7 by vacuum deposition, sputtering, CVD, or electroless plating. A thin metal layer made of a copper (Cu) film having a thickness of about 0.5 [μm] is formed. And a negative photosensitive resist is apply | coated on the formed thin-film metal layer, except a desired pattern part of a finished product is hardened, and a plating resist film is formed by removing a reaction part. Although a negative photosensitive resist is used here when forming the plating resist film, it goes without saying that a positive photosensitive resist may be used. Then, a thick metal layer made of, for example, a Cu film is selectively formed with a thickness of, for example, about 20 [μm] on the thin metal layer other than the portion where the plating resist film is formed by electrolytic plating. Then, after forming the thick metal layer, the plating resist film is melted and removed. Then, an etching solution capable of melting the thin metal layer and the thick metal layer, for example, etching the entire surface with a cupric chloride solution for a Cu film and an EDTA solution for a Ti film, The thin metal layer having a thinner layer thickness is removed first. By this step, a predetermined metal wiring pattern composed of the electrode pad 6, the wiring layer 9, and the contact pad 10 can be formed on the main surface of the semiconductor chip 7.
[0048]
In addition, although Cu was used as a material which comprises a thin film metal layer or a thick film metal layer, it may replace with this and may use Cr, W, Ti / Cu, Ni, etc. Alternatively, the thin film metal layer and the thick film metal layer may be made of different metal materials, and an etchant that selectively etches only the thin film metal layer may be used in the final etching step.
[0049]
Next, as shown in FIG. 3 (d), on the main surface of the semiconductor chip 7, except for the formed contact pads 10, at least the wiring layer 9 and the electrode pads 6 are covered with an insulating resin, thereby insulating resin. Layer 11 is formed.
[0050]
Specifically, after applying a photosensitive solder resist (insulating resin) on the elastic body layer 8, the solder resist film (only the contact pad 10 is exposed using a photolithography technique). An insulating resin layer 11) is formed. By this solder resist film, the electrode pad 6 and the wiring layer 9 which are portions other than the contact pad 10 are protected from the melted solder at the time of mounting.
[0051]
Next, as shown in FIG. 4A, the bump electrode 12 is formed on the contact pad 10 on the semiconductor chip 7 with a conductive material.
[0052]
Specifically, a metal ball made of solder, solder-plated copper, nickel, or the like is placed on the contact pad 10, and the metal ball and the contact pad 10 are melt-bonded to form the protruding electrode 12.
[0053]
Then, as shown in FIG. 4B, the underfill material layer 13 is formed on the main surface of the semiconductor chip 7 so as to expose the tops of the protruding electrodes 12 on the contact pads 10. In the present embodiment, the upper surface of the underfill material layer 13 is substantially flush with the top of the bump electrode 12, but the top of the bump electrode 12 is 1 μm to 200 μm from the top surface of the underfill material layer 13. ], Preferably 50 [μm]. By projecting the top portion of the protruding electrode 12 from the surface of the underfill material layer 13, when the board is mounted, the protruding electrode is bitten into the wiring electrode of the wiring board by pressing, and the underfill material layer is brought into close contact with the wiring board side. Therefore, the gap between the two can be hermetically sealed.
[0054]
Further, in the underfill material layer 13, the upper surface of the underfill material layer 13 at the periphery of the semiconductor chip 7 and outside the outermost contact pad of the contact pads 10 is higher than the top of the protruding electrode 12. By adjusting the film thickness so as to be, when the substrate is mounted, the fillet portion made of the underfill material can be formed together with the hermetic sealing of the gap between the wiring substrate and the semiconductor device, and the mounting reliability can be improved.
[0055]
Specifically, after applying an underfill material on the insulating resin layer 11 on the semiconductor chip 7, the underfill material is exposed using a photolithography technique or an etching technique so that the top of the contact pad 10 is exposed. Layer 13 is formed. Here, an epoxy resin is used as the material of the underfill material layer.
[0056]
Through the processes as described above, a chip-shaped and high-density type semiconductor device suitable for substrate mounting can be realized.
[0057]
As described above, in the present embodiment, the manufacturing process using a semiconductor chip has been described. However, in the step of preparing a semiconductor chip having electrode pads formed on the main surface, a plurality of semiconductor chips are formed in the surface. It may be prepared as a semiconductor wafer and manufactured in units of semiconductor wafers. Thereby, since the elastic body layer, the wiring layer, and the like in a large number of semiconductor chip regions are formed with the semiconductor wafer before being divided into semiconductor chips, the manufacturing cost can be greatly reduced.
[0058]
Next, a method for mounting the semiconductor device of this embodiment will be described. FIG. 5 is a cross-sectional view for each main process showing the mounting method of the semiconductor device of this embodiment.
[0059]
First, as shown in FIG. 5A, a semiconductor chip 7 having a plurality of electrode pads 6 on the main surface, an elastic layer 8 formed on the main surface of the semiconductor chip 7 excluding the electrode pads 6, A plurality of contact pads 10, which are two-dimensionally arranged in a rewiring arrangement by a wiring layer 9 connected to each electrode pad 6 on the elastic body layer 8 on the main surface of the semiconductor chip 7, and a plurality of contact pads 10. The insulating resin layer 11 formed on the main surface of the semiconductor chip 7 to be removed, the protruding electrode 12 provided on the contact pad 10, and the top of the protruding electrode 12 are exposed and provided on the insulating resin layer 11. The main surface side of the semiconductor device composed of the formed underfill material layer 13 is opposed to the wiring electrode surface side of the wiring substrate 15 having the wiring electrodes 14, and the electrodes are aligned.
[0060]
Next, as shown in FIG. 5B, the protruding electrode 12 of the semiconductor device and the wiring electrode 14 of the wiring board 15 are brought into contact with each other.
[0061]
Furthermore, the top part of the protruding electrode 12 exposed from the underfill material layer 13 is pressed against the wiring electrode 14 of the wiring board 15 to be brought into contact with the wiring electrode 15, whereby a more reliable connection can be obtained.
[0062]
Then, as shown in FIG. 5C, the underfill material layer 13 of the semiconductor device is softened and melted by heating, and the gap between the main surface of the semiconductor device and the main surface of the wiring board 15 is filled and sealed with the underfill material layer 13. Stop and complete board mounting. As heating conditions, the underfill material layer 13 is softened and melted by heating at 150 [° C.], and the gap can be filled without voids.
[0063]
By the semiconductor device mounting method of the present embodiment, the semiconductor device having the underfill material layer 13 is brought into contact with the wiring electrode 14 of the wiring board 15 and the underfill material layer 13 is heat-treated. Connection and sealing can be performed, and highly efficient and reliable substrate mounting can be realized.
[0064]
Next, a method for mounting a semiconductor device according to another embodiment will be described. FIG. 6 is a cross-sectional view for each main process showing a semiconductor device mounting method according to another embodiment. The semiconductor device mounted in this embodiment will be described by taking the semiconductor device having the structure shown in FIG. 1 as an example.
[0065]
First, as shown in FIG. 6A, an underfill sheet 16 is pasted on the electrode forming surface of the wiring board 15 having the wiring electrodes 14. The thickness and area of the underfill sheet 16 to be attached here are set according to the area of the semiconductor device to be mounted and the height of the protruding electrode.
[0066]
Next, as shown in FIG. 6B, a semiconductor chip 7 having a plurality of electrode pads 6 on the main surface, and an elastic body layer 8 formed on the main surface of the semiconductor chip 7 excluding the electrode pads 6; A plurality of contact pads 10, which are two-dimensionally arranged in a rewiring arrangement by a wiring layer 9 connected to each electrode pad 6 on the elastic body layer 8 within the main surface of the semiconductor chip 7, and a plurality of contact pads 10. An underfill sheet 16 is affixed to the main surface side of the semiconductor device, which includes the insulating resin layer 11 formed on the main surface of the semiconductor chip 7 excluding and the protruding electrodes 12 respectively provided on the contact pads 10. The wiring substrate 15 side of the wiring substrate 15 is opposed to each other, and the electrodes are aligned.
[0067]
Then, as shown in FIG. 6C, the semiconductor device is pressed from the back surface to connect the protruding electrode 12 and the wiring electrode 14 of the wiring board 15, and the underfill sheet 16 is sandwiched between the two and mounted. . In this case, the underfill sheet 16 is pierced by the protruding electrode 12 and connected to the wiring electrode 14 on the wiring substrate 15.
[0068]
As described above, since the elastic layer is interposed between the protruding electrode 12 to be connected and the semiconductor integrated circuit element region of the semiconductor chip as the semiconductor device to be mounted on the substrate, the element is caused by the pressing force at the time of mounting. It can prevent destruction and can be mounted efficiently.
[0069]
As described above, since the contact pad connected to the wiring layer is formed on the elastic layer in the semiconductor device of the present embodiment, after mounting on the wiring substrate such as a mother board, the wiring substrate and the semiconductor device are The stress applied to the connection portion due to the difference in thermal expansion coefficient is absorbed by the elasticity of the elastic body layer. That is, a semiconductor device having a high stress relaxation function can be realized. Furthermore, since the semiconductor device has an underfill material required for substrate mounting, the semiconductor device can realize more efficient and reliable substrate mounting. In particular, since a thick underfill material layer is disposed in the peripheral portion of the semiconductor device, a fillet portion can be efficiently formed at the time of substrate mounting, and highly reliable substrate mounting can be realized.
[0070]
In addition, the semiconductor device manufacturing method of the present embodiment can realize a high-density type semiconductor device in a chip shape suitable for substrate mounting.
[0071]
Then, a semiconductor device having an underfill material layer is brought into contact with the wiring electrode of the wiring board, and the underfill material is subjected to heat treatment, whereby high-efficiency and highly reliable substrate mounting can be realized.
[0072]
【The invention's effect】
The semiconductor device of the present invention has a structure that can be formed in the form of a semiconductor wafer, is a small and thin semiconductor device, and is connected to an electrode by a metal wiring layer instead of connecting an electrode by a lead as in the prior art. Therefore, it is a semiconductor device that is suitable for microfabrication and can cope with an increase in the number of pins. In addition, since the wiring layer integrated with the external electrode is formed on the elastic layer, the wiring layer can be prevented from being disconnected, and the thermal stress of the external electrode can be buffered. Reliability can be improved. And since it has the underfill material required at the time of board | substrate mounting above all, it is a semiconductor device which can implement | achieve more efficient and reliable board | substrate mounting. In particular, since a thick underfill material layer is disposed in the peripheral portion of the semiconductor device, a fillet portion at the time of substrate mounting can be formed efficiently and reliably, and highly reliable substrate mounting can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating a semiconductor device mounting method according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view illustrating a semiconductor device mounting method according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a conventional semiconductor device.
FIG. 8 is a cross-sectional view showing a conventional semiconductor device mounting method;
FIG. 9 is a cross-sectional view showing a conventional semiconductor device mounting method;
[Explanation of symbols]
1 Semiconductor chip
2 Projection electrode
3 Wiring board
4 Wiring electrode
5 Underfill material
6 Electrode pads
7 Semiconductor chip
8 Elastic layer
9 Wiring layer
10 Contact pads
11 Insulating resin layer
12 Projection electrode
13 Underfill material layer
14 Wiring electrode
15 Wiring board
16 Underfill sheet

Claims (4)

その主面上に複数の電極パッドを有した半導体チップと、
前記複数の電極パッドを除く半導体チップの主面上に形成された弾性体層と、
前記半導体チップの主面内であって、前記弾性体層上に前記複数の電極パッドと接続した配線層により再配線接続で配置された複数のコンタクトパッドと、
前記複数のコンタクトパッドを除く半導体チップの主面上に形成された絶縁性樹脂層と、
前記コンタクトパッド上に各々設けられた突起電極と、
前記突起電極の頂部を露出させ、前記絶縁性樹脂層に設けられたアンダーフィル材層とよりなる半導体装置であって、
前記半導体チップの周辺部のみのアンダーフィル材層の上面は突起電極の頂部よりも上方にあることを特徴とする半導体装置。A semiconductor chip having a plurality of electrode pads on its main surface;
An elastic layer formed on the main surface of the semiconductor chip excluding the plurality of electrode pads;
A plurality of contact pads arranged in a rewiring connection in a main surface of the semiconductor chip and on the elastic body layer by a wiring layer connected to the plurality of electrode pads;
An insulating resin layer formed on the main surface of the semiconductor chip excluding the plurality of contact pads;
A bump electrode provided on each of the contact pads;
A semiconductor device comprising an underfill material layer provided on the insulating resin layer, exposing a top portion of the protruding electrode;
The upper surface of the underfill material layer only in the peripheral portion of the semiconductor chip is located above the top of the protruding electrode. 突起電極は半田ボールであることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the protruding electrode is a solder ball. アンダーフィル材層はエポキシ樹脂層であることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the underfill material layer is an epoxy resin layer. 弾性体層の端部は、断面形状において斜辺を構成していることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein an end portion of the elastic layer forms a hypotenuse in a cross-sectional shape.
JP2001030578A 2001-02-07 2001-02-07 Semiconductor device Expired - Lifetime JP4465891B2 (en)

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US20050133933A1 (en) * 2003-12-19 2005-06-23 Advanpack Solutions Pte. Ltd. Various structure/height bumps for wafer level-chip scale package
US7999379B2 (en) * 2005-02-25 2011-08-16 Tessera, Inc. Microelectronic assemblies having compliancy
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US7989824B2 (en) * 2009-06-03 2011-08-02 Koninklijke Philips Electronics N.V. Method of forming a dielectric layer on a semiconductor light emitting device
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