JPH0558569B2 - - Google Patents
Info
- Publication number
- JPH0558569B2 JPH0558569B2 JP15921286A JP15921286A JPH0558569B2 JP H0558569 B2 JPH0558569 B2 JP H0558569B2 JP 15921286 A JP15921286 A JP 15921286A JP 15921286 A JP15921286 A JP 15921286A JP H0558569 B2 JPH0558569 B2 JP H0558569B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- semiconductor
- metal plate
- substrate
- semiconductor pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000008188 pellet Substances 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 239000000919 ceramic Substances 0.000 description 11
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000005219 brazing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本発明は、複数の半導体ペレツトがそれぞれヒ
ートシンクとしての金属板を介して絶縁基板上に
固定され、その絶縁基板上に支持される端子導体
と半導体ペレツト上の電極とが接続され、また絶
縁基板が金属基板上に固着され、半導体ペレツト
が樹脂層により被覆される半導体装置の製造方法
に関する。
In the present invention, a plurality of semiconductor pellets are each fixed on an insulating substrate via a metal plate serving as a heat sink, a terminal conductor supported on the insulating substrate is connected to an electrode on the semiconductor pellet, and the insulating substrate is The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor pellet is fixed on a metal substrate and covered with a resin layer.
【従来技術とその問題点】
複数の半導体ペレツトから構成される半導体装
置は、ペレツト間の絶縁のために絶縁基板上にペ
レツトを固定する。その場合、ペレツトに発生す
るヒートシヨツクを避けるためにペレツトをヒー
トシンクを介して固定し、さらに絶縁基板を介し
ての放熱のために絶縁基板の反ペレツト側に金属
基板を固着する。第３図はそのような半導体装置
を示し、複数の半導体ペレツト１がヒートシンク
としての銅板２を介してセラミツク基板３の上に
固定される。ペレツト１上の電極は絶縁基板３に
固定された端子導体４と導線５により接続され、
絶縁基板３の下面は放熱板としての銅基板６に固
着されている。セラミツク基板３と銅板２および
放熱銅基板６との接着は、セラミツク基板３に予
めメタライジングを施し、メタライズ金属層と銅
板とをはんだ付けすることにより行う。しかしこ
の場合、絶縁基板３と放熱基板６とは全面で接着
されるので、セラミツクと鋼との熱膨張係数の差
に基づく湾曲あるいはセラミツク板の割れを避け
るために放熱基板６には数mmと厚く、また封止樹
脂層７よりも大きい面積のものを用い、熱膨張係
数の差による応力がうちかつて平坦な状態が維持
されるようにしていた。しかし、この結果半導体
装置は大型になり、重くなるという欠点があつ
た。[Prior Art and its Problems] In a semiconductor device composed of a plurality of semiconductor pellets, the pellets are fixed on an insulating substrate for insulation between the pellets. In that case, the pellets are fixed via a heat sink to avoid heat shock occurring in the pellets, and a metal substrate is further fixed to the side of the insulating substrate opposite to the pellets in order to dissipate heat through the insulating substrate. FIG. 3 shows such a semiconductor device, in which a plurality of semiconductor pellets 1 are fixed onto a ceramic substrate 3 via a copper plate 2 serving as a heat sink. The electrode on the pellet 1 is connected to a terminal conductor 4 fixed to an insulating substrate 3 by a conducting wire 5,
The lower surface of the insulating substrate 3 is fixed to a copper substrate 6 as a heat sink. The ceramic substrate 3 is bonded to the copper plate 2 and the heat dissipating copper substrate 6 by metallizing the ceramic substrate 3 in advance and soldering the metallized metal layer and the copper plate. However, in this case, since the insulating substrate 3 and the heat dissipation board 6 are bonded together over their entire surface, a few millimeters are attached to the heat dissipation board 6 in order to avoid bending or cracking of the ceramic board due to the difference in thermal expansion coefficient between ceramic and steel. A layer that is thick and has a larger area than the sealing resin layer 7 is used so that the stress due to the difference in thermal expansion coefficients is absorbed and the flat state is maintained. However, as a result, the semiconductor device becomes large and heavy, which is a drawback.
本発明は、上記の欠点を除いてセラミツクと銅
との熱膨張係数の差に基づく湾曲あるいはセラミ
ツク板の割れを生ずることなく小形で軽量化され
る半導体装置の製造方法を提供することを目的と
する。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can be made smaller and lighter without causing bending or cracking of the ceramic plate due to the difference in thermal expansion coefficient between ceramic and copper, except for the above-mentioned drawbacks. do.
本発明は、絶縁基板の一面の所定の領域と他面
のほぼ全面に同じ厚さの金属板を同時に固着し、
その絶縁基板の一面の金属板上に半導体ペレツト
を固着し、半導体ペレツトの電極と端子導体とを
接続したのち、絶縁基板の他面側の金属板の反絶
縁基板側面を露出させ、金属板の側面に接触する
樹脂層によつて半導体ペレツトを覆うもので、絶
縁基板の両面に同じ厚さの金属板を同時に固着す
ることにより絶縁基板が湾曲あるいは割れること
がなく、また他面側の金属板を外部放熱体に密着
させることにより従来と同様の放熱効果が得ら
れ、厚く大きい放熱金属基板を用いる必要がない
ので上述の目的が達成される。
The present invention simultaneously fixes a metal plate of the same thickness to a predetermined area on one side of an insulating substrate and almost the entire surface of the other side,
After fixing a semiconductor pellet on the metal plate on one side of the insulating substrate and connecting the electrode of the semiconductor pellet to the terminal conductor, the side surface of the metal plate on the other side of the insulating substrate opposite to the insulating substrate is exposed. The semiconductor pellet is covered with a resin layer that contacts the side surfaces, and by fixing metal plates of the same thickness to both sides of the insulating substrate at the same time, the insulating substrate will not be bent or cracked, and the metal plate on the other side will not bend or crack. By bringing the heat sink into close contact with the external heat radiator, a heat radiation effect similar to the conventional one can be obtained, and there is no need to use a thick and large heat radiation metal substrate, so that the above-mentioned objective can be achieved.
第１図は本発明の一実施例による半導体装置を
示し、第２図と共通の部分には同一の符号が付さ
れている。この場合は、予め厚さ約0.5mmのセラ
ミツク基板の両面にメタライジングを施し、厚さ
約１mmの銅板２および８をろう付けする。両面の
ろう付けを同時に行うことによりセラミツク基板
の両面に熱膨張係数差に基づく応力が等しく加わ
りセラミツク基板は湾曲することがない。次いで
上面側の銅板２およびその下のメタライズ層を選
択的にエツチングして除去し、半導体ペレツト１
および端子導体４を支持する領域のみが残るよう
に銅板２のパターニングを行う。この残された銅
板上に複数の半導体ペレツト１および端子導体４
をはんだ付けし、ペレツト１上の電極と端子導体
４とを導線５のボンデイングにより接続する。こ
のあと、図に示すように銅板８の下面を露出させ
それと同一平面を形成する樹脂層７により半導体
ペレツト１を封止することによつて半導体装置が
でき上がる。
第２図は本発明の別の実施例による半導体装置
を示し、絶縁基板３の下面側の銅板８が樹脂層７
より突出するように樹脂成形したもので、この半
導体装置を冷却体へ直接ろう付けして効率の良い
放熱性を得るのに好都合な構造である。
FIG. 1 shows a semiconductor device according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this case, metallization is applied in advance to both sides of a ceramic substrate having a thickness of about 0.5 mm, and copper plates 2 and 8 having a thickness of about 1 mm are brazed to the ceramic substrate. By brazing both sides at the same time, stress based on the difference in coefficient of thermal expansion is equally applied to both sides of the ceramic substrate, so that the ceramic substrate does not bend. Next, the copper plate 2 on the upper surface side and the metallized layer thereunder are selectively etched and removed, and the semiconductor pellet 1 is formed.
Then, the copper plate 2 is patterned so that only the area supporting the terminal conductor 4 remains. A plurality of semiconductor pellets 1 and terminal conductors 4 are placed on this remaining copper plate.
are soldered, and the electrode on the pellet 1 and the terminal conductor 4 are connected by bonding with a conducting wire 5. Thereafter, as shown in the figure, the semiconductor pellet 1 is sealed with a resin layer 7 that exposes the lower surface of the copper plate 8 and forms the same plane as the lower surface of the copper plate 8, thereby completing the semiconductor device. FIG. 2 shows a semiconductor device according to another embodiment of the present invention, in which a copper plate 8 on the lower surface side of an insulating substrate 3 is connected to a resin layer 7.
It is molded with resin so that it protrudes more, and has a convenient structure for directly brazing the semiconductor device to a cooling body to obtain efficient heat dissipation.
本発明によれば、予め両面に同じ厚さの金属板
を同時に固着した絶縁基板を用い、一方の金属板
を半導体ペレツトとの間のヒートシンクに、他方
の金属板を封止樹脂層と同一面に露出させて外部
放熱体との熱伝導のための接触に利用することに
よつて、絶縁基板の湾曲あるいは割れをなくすと
共に厚く、大きい放熱基板が不必要になり、小形
で軽量の樹脂封止半導体装置を得ることができ
る。
According to the present invention, an insulating substrate to which metal plates of the same thickness are simultaneously fixed on both sides is used, one metal plate is used as a heat sink between the semiconductor pellet, and the other metal plate is placed on the same surface as the sealing resin layer. By exposing the insulating substrate to the external heat sink and using it for heat conduction contact, it eliminates bending or cracking of the insulating substrate, eliminates the need for a thick and large heat dissipation substrate, and creates a compact and lightweight resin-sealed substrate. A semiconductor device can be obtained.
第１図は本発明の一実施例による半導体装置の
断面図、第３図は従来の半導体装置の断面図、第
２図は本発明の別の実施例による半導体装置の断
面図である。
１：半導体ペレツト、２，８：銅板、３：絶縁
基板、４：端子導体、５：導線、７：樹脂層。
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a conventional semiconductor device, and FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. 1: Semiconductor pellet, 2, 8: Copper plate, 3: Insulating substrate, 4: Terminal conductor, 5: Conductive wire, 7: Resin layer.
Claims (1)
して絶縁基板上に固定され、絶縁基板上に支持さ
れる端子導体と半導体ペレツト上の電極とが接続
され、かつ絶縁基板が金属基板上に固着され、半
導体ペレツトが樹脂層により被覆されるものを製
造するに際し、絶縁基板の一面の所定の領域と他
面のほぼ全面に同じ厚さの金属板を同時に固着
し、絶縁基板の一面の金属板上に半導体ペレツト
を固着し、半導体ペレツトの電極と端子導体とを
接続したのち、絶縁基板の他面側の前記金属板の
反絶縁基板側の面を露出させ、前記金属板の側面
に接触する樹脂層によつて半導体ペレツトを覆う
ことを特徴とする半導体装置の製造方法。1. A plurality of semiconductor pellets are each fixed on an insulating substrate via a metal plate, a terminal conductor supported on the insulating substrate and an electrode on the semiconductor pellet are connected, and the insulating substrate is fixed on the metal substrate, When manufacturing a semiconductor pellet coated with a resin layer, a metal plate of the same thickness is simultaneously fixed to a predetermined area on one side of an insulating substrate and almost the entire surface of the other side, and then a metal plate is placed on one side of the insulating substrate. After fixing the semiconductor pellet and connecting the electrode of the semiconductor pellet and the terminal conductor, the surface of the metal plate on the opposite side of the insulating substrate on the other side of the insulating substrate is exposed, and a resin layer is placed in contact with the side surface of the metal plate. 1. A method of manufacturing a semiconductor device, which comprises covering a semiconductor pellet with a wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15921286A JPS6315430A (en) | 1986-07-07 | 1986-07-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15921286A JPS6315430A (en) | 1986-07-07 | 1986-07-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6315430A JPS6315430A (en) | 1988-01-22 |
| JPH0558569B2 true JPH0558569B2 (en) | 1993-08-26 |
Family
ID=15688773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15921286A Granted JPS6315430A (en) | 1986-07-07 | 1986-07-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6315430A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2883787B2 (en) * | 1993-07-20 | 1999-04-19 | 富士電機株式会社 | Substrate for power semiconductor device |
| US5675181A (en) * | 1995-01-19 | 1997-10-07 | Fuji Electric Co., Ltd. | Zirconia-added alumina substrate with direct bonding of copper |
| KR100765604B1 (en) | 2004-11-26 | 2007-10-09 | 산요덴키가부시키가이샤 | Circuit device and manufacturing method thereof |
| JP5061717B2 (en) * | 2007-05-18 | 2012-10-31 | 富士電機株式会社 | Semiconductor module and method for manufacturing semiconductor module |
-
1986
- 1986-07-07 JP JP15921286A patent/JPS6315430A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6315430A (en) | 1988-01-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |