JP2661230B2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JP2661230B2
JP2661230B2 JP301389A JP301389A JP2661230B2 JP 2661230 B2 JP2661230 B2 JP 2661230B2 JP 301389 A JP301389 A JP 301389A JP 301389 A JP301389 A JP 301389A JP 2661230 B2 JP2661230 B2 JP 2661230B2
Authority
JP
Japan
Prior art keywords
solder
fixed
integrated circuit
hybrid integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP301389A
Other languages
Japanese (ja)
Other versions
JPH02183557A (en
Inventor
定男 下平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP301389A priority Critical patent/JP2661230B2/en
Publication of JPH02183557A publication Critical patent/JPH02183557A/en
Application granted granted Critical
Publication of JP2661230B2 publication Critical patent/JP2661230B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components

Abstract

PURPOSE:To avoid cracks in a circuit substrate and realize superior thermal conductivity by fixing the circuit substrate divided into a plurality of segments on a heat sink by using solder, and fixing a copper thin plate so as to bridge the divided circuit substrate. CONSTITUTION:Two circuit substrates 3a and 3b, on both surfaces of which conductor patterns are formed, are fixed on one heat sink 1 by using solder 2a, so as to be adjacent with each other. A copper thin plate 6a being a metal layer is fixed so as to bridge the two circuit substrates 3a and 3b, by using solder 2b. A semiconductor chip 4 is fixed on a mounting pad 8 by using solder 2c. An electrode pad of the semiconductor chip 4 and the copper thin plate are connected by using a metal thin wire 6. Thereby, thermal conductivity is improved and the generation of cracks in the circuit substrate can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置に関し、特にヒートシンク
と回路基板との接続構造に関する。The present invention relates to a hybrid integrated circuit device, and more particularly, to a connection structure between a heat sink and a circuit board.

〔従来の技術〕[Conventional technology]

第２図は従来の第１の例を示す混成集積回路装置の断
面図、第３図は従来の第２の例を示す混成集積回路装置
の断面図である。この種の混成集積回路装置は、ヒート
シンクと回路基板との接続構造において、回路基板が15
mm平方以上の正方形の場合には二種類ある。FIG. 2 is a cross-sectional view of a hybrid integrated circuit device showing a first conventional example, and FIG. 3 is a cross-sectional view of a hybrid integrated circuit device showing a second conventional example. In this type of hybrid integrated circuit device, the connection structure between the heat sink and the circuit board is
There are two types for squares of mm square or more.

例えば、第２図に示すように、回路基板３には半導体
チップ６が金属層からなる搭載パッド８を介してはんだ
７で固着されているとともにその半導体チップ６の電極
パッドと半導体チップ６が搭載されている面と同一面上
に形成された導電層10に金属細線６で接続されている。
これらの部品が搭載された回路基板３は、ヒートシンク
１に樹脂９で接着されている。For example, as shown in FIG. 2, a semiconductor chip 6 is fixed to the circuit board 3 by solder 7 via a mounting pad 8 made of a metal layer, and the electrode pads of the semiconductor chip 6 and the semiconductor chip 6 are mounted thereon. It is connected to a conductive layer 10 formed on the same surface as the surface on which it is formed by a thin metal wire 6.
The circuit board 3 on which these components are mounted is bonded to the heat sink 1 with a resin 9.

また、同様の構造であるが、第３図に示すように、回
路基板３が部分的にはんだ２でヒートシンク１に固着さ
れているものもある。In addition, there is a structure having a similar structure, but the circuit board 3 is partially fixed to the heat sink 1 with solder 2 as shown in FIG.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、上述した従来の混成集積回路装置で
は、例えば、回路基板を樹脂でヒートシンクに接着した
場合は、この樹脂の熱伝導が劣り放熱効果が悪いという
欠点がある。また、はんだで固着する場合は、接続面積
が大きくなると、熱膨張率の差により回路基板に熱スト
レスが加わり、回路基板にクラックが発生するという欠
点がある。However, in the above-described conventional hybrid integrated circuit device, for example, when a circuit board is bonded to a heat sink with a resin, there is a disadvantage that the heat conduction of the resin is poor and the heat radiation effect is poor. In the case of fixing with solder, there is a disadvantage that when the connection area is large, a thermal stress is applied to the circuit board due to a difference in thermal expansion coefficient, and cracks are generated in the circuit board.

更に、この接着面積を小さくするために、回路基板を
小さくすると、部品を搭載する範囲や、金属細線を接続
するワイヤボンディング装置の接続する範囲を制限する
という欠点がある。Furthermore, if the circuit board is made smaller in order to reduce the bonding area, there is a drawback that the range in which components are mounted and the range in which a wire bonding apparatus for connecting thin metal wires is connected are limited.

本発明の目的は、熱伝導が良く、回路基板にクラック
を生ずることなく、また、搭載部品の配置の範囲や、金
属細線を接続する装置の接続する範囲を制限することの
ない構造をもつ混成集積回路装置を提供することであ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid having a structure that has good heat conduction, does not cause cracks in a circuit board, and does not limit the range of arrangement of mounted components and the range of connection of a device for connecting thin metal wires. An object is to provide an integrated circuit device.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の混成集積回路装置は、ヒートシンク上に複数
個に分割され固着される回路基板と、この分割された回
路基板に跨がって固着される薄導電板と、この薄導電板
に接続される金属細線あるいは発熱体である半導体装置
とを備え構成される。A hybrid integrated circuit device according to the present invention includes a circuit board divided and fixed on a heat sink, a thin conductive plate fixed across the divided circuit board, and a thin conductive plate connected to the thin conductive plate. And a semiconductor device as a heating element.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第１図は本発明による一実施例を示す混成集積回路装
置の断面図である。この混成集積回路装置は、両面が導
電パターンが形成された二つの回路基板3a及び3bを一つ
のヒートシンク１にはんだ2aで隣接し並べ固着されてい
る。また、金属層である銅薄板5aが二つの回路基板3a及
び3bに跨がってはんだ2bで固着されている。FIG. 1 is a sectional view of a hybrid integrated circuit device showing an embodiment according to the present invention. In this hybrid integrated circuit device, two circuit boards 3a and 3b each having a conductive pattern formed on both sides are arranged side by side with a solder 2a on one heat sink 1 and fixed. Further, a copper thin plate 5a as a metal layer is fixed over the two circuit boards 3a and 3b with solder 2b.

更に、従来例と同様に、半導体チップ４ははんだ2cに
より搭載パッド８に固着され、金属細線６により半導体
チップ４の電極パッドと銅薄板とが接続されている。Further, similarly to the conventional example, the semiconductor chip 4 is fixed to the mounting pad 8 by the solder 2c, and the electrode pad of the semiconductor chip 4 and the copper thin plate are connected by the thin metal wire 6.

このような構造をした混成集積回路装置を、試みに、
例えば、0.635mm厚で4.5mm平方の正方形のアルミナセラ
ミック製の二つの回路基板3a及び3bを、例えば、2.5mm
厚のアルミニユム製のヒートシンク１にはんだ2aで固着
し組立たところ、その後の信頼性評価試験である温度サ
イクルテスト、例えば、−30〜85℃の温度範囲で、500
サイクル行なっても、回路基板に異常が認められなかっ
た。また、もう一つの試みとして、例えば、前述の材料
及び構造が同じで、0.8mm厚の銅薄板5aをはんだ2bで回
路基板3a及び3bに跨がって固着し、更にその上に発熱体
であるパワートランジスタ（取付け面積・3mm平方）を
固着してその熱抵抗を測定したところ、従来、樹脂を使
用したときの熱抵抗５℃/wに比べ、1.6℃/wという良好
な結果が得られた。To try a hybrid integrated circuit device with such a structure,
For example, two circuit boards 3a and 3b made of alumina ceramic having a thickness of 0.635 mm and a square of 4.5 mm square, for example, 2.5 mm
A thick aluminum heat sink 1 was fixed with solder 2a and assembled. After that, a temperature cycle test as a reliability evaluation test, for example, in a temperature range of −30 to 85 ° C., 500
No abnormality was found on the circuit board even after the cycle was performed. As another attempt, for example, a 0.8 mm thick copper thin plate 5a having the same material and structure as described above is fixed across the circuit boards 3a and 3b with solder 2b, and a heating element is further placed thereon. When a certain power transistor (mounting area: 3 mm square) was fixed and its thermal resistance was measured, a good result of 1.6 ° C / w was obtained compared to the conventional thermal resistance of 5 ° C / w when using resin. Was.

更に、この構造の混成集積回路装置は、組立の際に、
全部の部品をはんだ付けで固着する方法を採用している
ので、還元雰囲気中で一度のはんだリーフローで組立出
来るという利点がある。Further, the hybrid integrated circuit device having this structure can
Since a method in which all parts are fixed by soldering is employed, there is an advantage that assembly can be performed by a single solder reflow in a reducing atmosphere.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、複数個に分割された回
路基板をはんだでヒートシンクに固着し、銅薄板を分割
された回路基板に跨がって固着することによって、この
上に配置される発熱体である半導体部品や金属細線の接
続個所を任意に配置出来るとともに回路基板にクラック
が生ずることなく熱伝導度の良い混成集積回路装置が得
られるという効果がある。As described above, according to the present invention, a plurality of divided circuit boards are fixed to a heat sink by soldering, and a thin copper plate is fixed across the divided circuit boards, thereby generating heat generated on the divided circuit boards. There is an effect that a connecting portion of a semiconductor component or a thin metal wire, which is a body, can be arbitrarily arranged and a hybrid integrated circuit device having good thermal conductivity without cracking on a circuit board can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明による一実施例を示す混成集積回路装置
の断面図、第２図は従来の第１の例を示す混成集積回路
装置の断面図、第３図は従来の第２の例を示す混成集積
回路装置の断面図である。 １……ヒートシンク、２、2a、2b、2c、７……はんだ、
３、3a、3b……回路基板、４……半導体チップ、５……
導電層、5a……銅薄板、６……金属細線、８……搭載パ
ッド、９……樹脂。FIG. 1 is a cross-sectional view of a hybrid integrated circuit device showing one embodiment according to the present invention, FIG. 2 is a cross-sectional view of a hybrid integrated circuit device showing a first conventional example, and FIG. FIG. 2 is a cross-sectional view of the hybrid integrated circuit device shown in FIG. 1. heat sink, 2, 2a, 2b, 2c, 7 ... solder,
3, 3a, 3b ... circuit board, 4 ... semiconductor chip, 5 ...
Conductive layer, 5a: copper thin plate, 6: thin metal wire, 8: mounting pad, 9: resin.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】ヒートシンク上に複数個に分割され固着さ
れる回路基板と、この分割された回路基板に跨がって固
着される薄導電板と、この薄導電板に接続される金属細
線あるいは発熱体である半導体装置とを有することを特
徴とする混成集積回路装置。1. A circuit board divided and fixed on a heat sink, a thin conductive plate fixed across the divided circuit board, and a thin metal wire or wire connected to the thin conductive plate. A hybrid integrated circuit device comprising: a semiconductor device serving as a heating element.
JP301389A 1989-01-09 1989-01-09 Hybrid integrated circuit device Expired - Lifetime JP2661230B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP301389A JP2661230B2 (en) 1989-01-09 1989-01-09 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP301389A JP2661230B2 (en) 1989-01-09 1989-01-09 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH02183557A JPH02183557A (en) 1990-07-18
JP2661230B2 true JP2661230B2 (en) 1997-10-08

Family

ID=11545457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP301389A Expired - Lifetime JP2661230B2 (en) 1989-01-09 1989-01-09 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP2661230B2 (en)

Also Published As

Publication number Publication date
JPH02183557A (en) 1990-07-18

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