JP2661230B2 - 混成集積回路装置 - Google Patents
混成集積回路装置Info
- Publication number
- JP2661230B2 JP2661230B2 JP301389A JP301389A JP2661230B2 JP 2661230 B2 JP2661230 B2 JP 2661230B2 JP 301389 A JP301389 A JP 301389A JP 301389 A JP301389 A JP 301389A JP 2661230 B2 JP2661230 B2 JP 2661230B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- fixed
- integrated circuit
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Description
と回路基板との接続構造に関する。
面図、第3図は従来の第2の例を示す混成集積回路装置
の断面図である。この種の混成集積回路装置は、ヒート
シンクと回路基板との接続構造において、回路基板が15
mm平方以上の正方形の場合には二種類ある。
チップ6が金属層からなる搭載パッド8を介してはんだ
7で固着されているとともにその半導体チップ6の電極
パッドと半導体チップ6が搭載されている面と同一面上
に形成された導電層10に金属細線6で接続されている。
これらの部品が搭載された回路基板3は、ヒートシンク
1に樹脂9で接着されている。
路基板3が部分的にはんだ2でヒートシンク1に固着さ
れているものもある。
は、例えば、回路基板を樹脂でヒートシンクに接着した
場合は、この樹脂の熱伝導が劣り放熱効果が悪いという
欠点がある。また、はんだで固着する場合は、接続面積
が大きくなると、熱膨張率の差により回路基板に熱スト
レスが加わり、回路基板にクラックが発生するという欠
点がある。
小さくすると、部品を搭載する範囲や、金属細線を接続
するワイヤボンディング装置の接続する範囲を制限する
という欠点がある。
を生ずることなく、また、搭載部品の配置の範囲や、金
属細線を接続する装置の接続する範囲を制限することの
ない構造をもつ混成集積回路装置を提供することであ
る。
個に分割され固着される回路基板と、この分割された回
路基板に跨がって固着される薄導電板と、この薄導電板
に接続される金属細線あるいは発熱体である半導体装置
とを備え構成される。
置の断面図である。この混成集積回路装置は、両面が導
電パターンが形成された二つの回路基板3a及び3bを一つ
のヒートシンク1にはんだ2aで隣接し並べ固着されてい
る。また、金属層である銅薄板5aが二つの回路基板3a及
び3bに跨がってはんだ2bで固着されている。
より搭載パッド8に固着され、金属細線6により半導体
チップ4の電極パッドと銅薄板とが接続されている。
例えば、0.635mm厚で4.5mm平方の正方形のアルミナセラ
ミック製の二つの回路基板3a及び3bを、例えば、2.5mm
厚のアルミニユム製のヒートシンク1にはんだ2aで固着
し組立たところ、その後の信頼性評価試験である温度サ
イクルテスト、例えば、−30〜85℃の温度範囲で、500
サイクル行なっても、回路基板に異常が認められなかっ
た。また、もう一つの試みとして、例えば、前述の材料
及び構造が同じで、0.8mm厚の銅薄板5aをはんだ2bで回
路基板3a及び3bに跨がって固着し、更にその上に発熱体
であるパワートランジスタ(取付け面積・3mm平方)を
固着してその熱抵抗を測定したところ、従来、樹脂を使
用したときの熱抵抗5℃/wに比べ、1.6℃/wという良好
な結果が得られた。
全部の部品をはんだ付けで固着する方法を採用している
ので、還元雰囲気中で一度のはんだリーフローで組立出
来るという利点がある。
路基板をはんだでヒートシンクに固着し、銅薄板を分割
された回路基板に跨がって固着することによって、この
上に配置される発熱体である半導体部品や金属細線の接
続個所を任意に配置出来るとともに回路基板にクラック
が生ずることなく熱伝導度の良い混成集積回路装置が得
られるという効果がある。
の断面図、第2図は従来の第1の例を示す混成集積回路
装置の断面図、第3図は従来の第2の例を示す混成集積
回路装置の断面図である。 1……ヒートシンク、2、2a、2b、2c、7……はんだ、
3、3a、3b……回路基板、4……半導体チップ、5……
導電層、5a……銅薄板、6……金属細線、8……搭載パ
ッド、9……樹脂。
Claims (1)
- 【請求項1】ヒートシンク上に複数個に分割され固着さ
れる回路基板と、この分割された回路基板に跨がって固
着される薄導電板と、この薄導電板に接続される金属細
線あるいは発熱体である半導体装置とを有することを特
徴とする混成集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP301389A JP2661230B2 (ja) | 1989-01-09 | 1989-01-09 | 混成集積回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP301389A JP2661230B2 (ja) | 1989-01-09 | 1989-01-09 | 混成集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02183557A JPH02183557A (ja) | 1990-07-18 |
JP2661230B2 true JP2661230B2 (ja) | 1997-10-08 |
Family
ID=11545457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP301389A Expired - Lifetime JP2661230B2 (ja) | 1989-01-09 | 1989-01-09 | 混成集積回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2661230B2 (ja) |
-
1989
- 1989-01-09 JP JP301389A patent/JP2661230B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02183557A (ja) | 1990-07-18 |
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