JPS61264744A - Semiconductor device and substrate for semiconductor device - Google Patents
Semiconductor device and substrate for semiconductor deviceInfo
- Publication number
- JPS61264744A JPS61264744A JP10566685A JP10566685A JPS61264744A JP S61264744 A JPS61264744 A JP S61264744A JP 10566685 A JP10566685 A JP 10566685A JP 10566685 A JP10566685 A JP 10566685A JP S61264744 A JPS61264744 A JP S61264744A
- Authority
- JP
- Japan
- Prior art keywords
- heater
- semiconductor device
- switching element
- substrate
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/345—Arrangements for heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は耐温度環境特性、特に低温環境における特性や
耐久性を向上させた半導体装置およびその実装用の基板
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having improved temperature environment resistance characteristics, particularly characteristics and durability in a low temperature environment, and a substrate for mounting the same.
一般に、半導体装置は半導体デツプがパッケージ内に装
着されている。又、半導体装置用基板は上面に印刷配線
層が形成された絶縁板体からなり、その上面に複数の半
導体装置が実装される。この半導体装置の電気特性は温
度に対して敏感であり、特に低温下では特性の異常が発
生して使用することができなくなる。また、湿度変化の
差が大きな環境下ではパッケージや半導体チップ等が膨
張と収縮を繰り返すと共に、これらを構成する材質の低
温下での許容応力が小さくなるため、パッケージや半導
体チップにクラックが生じ、また、半導体装置の保護膜
であるパッシベーション賎のクラックも生じる。従って
、従来の半導体装置を冷凍庫等の低温槽内や厳寒地ある
いは宇宙空間における人工衛星等で使用する場合には早
期に使用不可能となる、という問題がある。Generally, a semiconductor device has a semiconductor dip mounted in a package. Further, the semiconductor device substrate is made of an insulating plate body with a printed wiring layer formed on the upper surface, and a plurality of semiconductor devices are mounted on the upper surface. The electrical characteristics of this semiconductor device are sensitive to temperature, and especially at low temperatures, abnormalities in characteristics occur and the device becomes unusable. In addition, in an environment with large differences in humidity, packages and semiconductor chips repeatedly expand and contract, and the allowable stress of the materials that make up these components at low temperatures decreases, causing cracks in packages and semiconductor chips. In addition, cracks occur in the passivation layer, which is a protective film of the semiconductor device. Therefore, when a conventional semiconductor device is used in a low-temperature chamber such as a freezer, in an extremely cold region, or on an artificial satellite in outer space, there is a problem in that it becomes unusable at an early stage.
本発明は上記事情を考慮してなされたもので、低温環境
においても電気特性が良好で、かつクラックの発生を抑
制した半導体装置および低温環境において半導体装置の
性能を維持できる半導体装置用基板を提供することを目
的とする。The present invention has been made in consideration of the above circumstances, and provides a semiconductor device that has good electrical characteristics even in a low-temperature environment and suppresses the occurrence of cracks, and a substrate for a semiconductor device that can maintain the performance of the semiconductor device in a low-temperature environment. The purpose is to
上記目的を達成するため本発明による半導体装置は、内
蔵したスイッチング要素により一定温度以下で作動する
ヒータをパッケージ内に取り付けて、パッケージと半導
体チップの過剰な温度降下を防止したことを特徴として
いる。又、本発明の半導体装置用基板はスイッチング要
素により一定温度以下で作動するヒータを絶縁板内に埋
設して半導体装置の過剰な温度降下を間接的に防止した
ことを特徴としている。In order to achieve the above object, a semiconductor device according to the present invention is characterized in that a heater that operates at a temperature below a certain temperature by a built-in switching element is installed in the package to prevent excessive temperature drop between the package and the semiconductor chip. Further, the substrate for a semiconductor device of the present invention is characterized in that a heater that operates at a temperature below a certain temperature by a switching element is embedded in the insulating plate to indirectly prevent excessive temperature drop of the semiconductor device.
以下、本発明を添付図面を参照しながら詳述する。 Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
第１図は本発明にかかる半導体装置の一実施例の断面図
、第２図はその要部の拡大断面図である。FIG. 1 is a cross-sectional view of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is an enlarged cross-sectional view of the main part thereof.
これによれば封止面がメタライズされたセラミックベー
ス１およびセラミック蓋体２がロウ材３によって接合さ
れて内部空間を有するパッケージが形成されている。下
部のセラミック基板１ａ上には半導体チップ４がマウン
トされ、セラミックベース１およびセラミック蓋体２の
接合部からアウタリード５がパッケージの外部に導出さ
れ、各アウタリードの内端部と半導体チップ４上の電極
とが金線等のボンディングワイヤ６によって接続されて
半導体装置が構成されている。パッケージの内部空間内
のセラミック蓋体２の内部下面には半導体チップ４の対
向位置にヒータ４が設けられ、またこのヒータ７を一定
温度以下で電源線に接続するように温度変化に応じてオ
ンオフするスイッチング要素が設けられている。ヒータ
４は環境温度が降下して電源線に接続されるとパッケー
ジおよびパッケージ内の半導体チップ４、ボンディング
ワイＶ６、アウタリード５等を加熱して、これらが一定
温度以下に温度降下しないように保つものである。また
、スイッチング要素８はパッケージ内の温度を検知して
、一定温度以下になるとヒータ７を電源に接続し、一定
温度以上では切離すスイッチング動作を行うものであり
、複数のアウタリード５の内の電源供給用のアウタリー
ドと接続されて外部電流をヒータ７に供給するようにな
っている。このスイッチング要素８としては熱膨張率の
異なる２枚の金属板を貼着したバイメタルあるいは一定
温度以下で変形する形状記憶合金等を使用することがで
きる。第２図はスイッチング要素としてバイメタル８′
を使用したものを示す拡大断面図であり、ヒータ７の右
端部７ａが下方に屈曲され、この折曲部７ａにバイメタ
ルの上部が面している。そして、一定温度以下になると
、バイメタル８′がヒータ７の折曲部７ａ方向に傾き、
ヒータ７のスイッチングが行われる。このスイッチング
温度は半導体チップ４の電気特性あるいはパッケージや
半導体チップ４の変化を考慮して設定され、例えば−２
０℃ないし、−３０℃の範囲内で選択される。According to this, a ceramic base 1 whose sealing surface is metallized and a ceramic lid 2 are joined by a brazing material 3 to form a package having an internal space. A semiconductor chip 4 is mounted on the lower ceramic substrate 1a, and outer leads 5 are led out of the package from the joint between the ceramic base 1 and the ceramic lid 2, and the inner ends of each outer lead and the electrodes on the semiconductor chip 4 are connected to each other. are connected by bonding wires 6 such as gold wires to form a semiconductor device. A heater 4 is provided on the inner lower surface of the ceramic lid 2 in the internal space of the package at a position facing the semiconductor chip 4, and is turned on and off according to temperature changes so that the heater 7 is connected to the power supply line below a certain temperature. A switching element is provided. When the environmental temperature drops and the heater 4 is connected to the power line, the heater 4 heats the package, the semiconductor chip 4, the bonding wire V6, the outer lead 5, etc. inside the package, and keeps these from falling below a certain temperature. It is. Further, the switching element 8 detects the temperature inside the package, and performs a switching operation of connecting the heater 7 to the power supply when the temperature is below a certain temperature and disconnecting it when the temperature exceeds a certain temperature. It is connected to a supply outer lead to supply external current to the heater 7. As the switching element 8, a bimetal formed by bonding two metal plates having different coefficients of thermal expansion, a shape memory alloy that deforms below a certain temperature, or the like can be used. Figure 2 shows a bimetal 8' as a switching element.
2 is an enlarged cross-sectional view showing a heater 7 in which the right end 7a of the heater 7 is bent downward, and the upper part of the bimetal faces the bent part 7a. When the temperature drops below a certain level, the bimetal 8' tilts toward the bent portion 7a of the heater 7.
Switching of the heater 7 is performed. This switching temperature is set in consideration of the electrical characteristics of the semiconductor chip 4 or changes in the package or the semiconductor chip 4, and is, for example, -2
The temperature is selected within the range of 0°C to -30°C.
従って、この半導体装置は一定温度以下ではヒータ７が
作動して過剰な温度降下が防止されるから低温環境下で
も電気特性が異常となったり、クララ゛りを生じること
がない。Therefore, in this semiconductor device, since the heater 7 is activated to prevent an excessive temperature drop below a certain temperature, the electrical characteristics do not become abnormal or blur even in a low-temperature environment.
第３図は本発明にかかる半導体装置用基板の−・実施例
の断面図を示している。この基板は所定厚さのエポキシ
あるいはポリイミドの板体１１からなり、板体１１上面
に印刷配線層１２がパターン形成されており、図中でフ
ラットパッケージとして描かれている半導体装置１３は
そのアウタリード１３ａがはんだ１４によって印刷配線
層１２と接合されている。そして、この板体１１内には
ステンレス箔等のヒータ１５が例えば積層法により埋設
されており、ヒータ１５の端部が板体１１上に取っ付番
ブられたスイッチング要素１６に接続されている。この
スイッチング要素１６も一定温度以下でヒータ１５を作
動させるものであり、ヒータ１５の熱は板体１１を介し
であるいは印刷配線層１２、はんだ１４、アウタ″リー
ド１３ａを介して半導体装置１３に伝達されて、基板１
１および半導体装に１３の過剰な温度降下が防止されて
いる。なお、ヒータ１５は加熱時以外の場合、ヒートシ
ンクとしての役割をも担うものである。またヒータは箔
の他二りＯム等の抵抗線を用いてもよい。FIG. 3 shows a sectional view of an embodiment of a semiconductor device substrate according to the present invention. This board consists of an epoxy or polyimide plate 11 with a predetermined thickness, and a printed wiring layer 12 is patterned on the upper surface of the plate 11. The semiconductor device 13, which is depicted as a flat package in the figure, has its outer leads 13a. is bonded to the printed wiring layer 12 by solder 14. A heater 15 made of stainless steel foil or the like is embedded in this plate 11 by, for example, a lamination method, and an end of the heater 15 is connected to a switching element 16 whose mounting number is marked on the plate 11. . This switching element 16 also operates the heater 15 at a temperature below a certain temperature, and the heat of the heater 15 is transmitted to the semiconductor device 13 via the plate 11 or via the printed wiring layer 12, the solder 14, and the outer lead 13a. substrate 1
1 and the semiconductor device 13 are prevented from excessively dropping in temperature. Note that the heater 15 also plays the role of a heat sink when not heating. Further, the heater may be made of a resistance wire such as a 2-wire wire instead of a foil.
本発明は上記実施例に限らず、種々の変更が可能であり
、例えば、半導体装置のパッケージ内および基板内の双
方にヒータを設けてもよく、スイッチング要素としては
低温においてヒータへの電流供給を直接オンオフできる
ものであれば何れも使用することができる。The present invention is not limited to the embodiments described above, and various modifications are possible. For example, a heater may be provided both in the package and the board of the semiconductor device, and the switching element may be used to supply current to the heater at low temperatures. Any device that can be turned on and off directly can be used.
また、低温によるストレスを防止するため、低温環境下
では半導体装置の動作いかんにかかわらずヒータ加熱が
行われるように、ヒータ電源回路を独立の回路にしてお
くことも可能である。Furthermore, in order to prevent stress due to low temperatures, the heater power supply circuit may be an independent circuit so that the heater heats up in a low temperature environment regardless of whether the semiconductor device is operating.
（発明の効果）
以上のとおり本発明によれば、所定温度以下で作動する
スイッチング要素により電流を供給されるヒータを半導
体装置のパッケージ内又は半導体装置用基板中に設けた
ので、半導体装置の過剰な温度低下を防止することがで
き、低温下でも電気特性が異常となったり、クラック等
の欠陥が発生 “することがなくなり、安定した特
性と信頼性を維持することができる。(Effects of the Invention) As described above, according to the present invention, a heater that is supplied with current by a switching element that operates at a temperature below a predetermined temperature is provided in a package of a semiconductor device or a substrate for a semiconductor device. This prevents the electrical properties from becoming abnormal or causing defects such as cracks even at low temperatures, and it is possible to maintain stable characteristics and reliability.
第１図および第２図は本発明による半導体装置の一実施
例の断面図および要部の断面図、第３図は本発明による
半導体装置用基板の断面図である。
１・・・ベース、２・・・蓋体、４・・・半導体チップ
、７゜１５・・・ヒータ、８，１６・・・スイッチング
要素、１１・・・板体、１３・・・半導体装置。
出願人代理人 猪 股 清口
６２ に
６３ 図1 and 2 are a cross-sectional view of an embodiment of a semiconductor device according to the present invention and a cross-sectional view of essential parts thereof, and FIG. 3 is a cross-sectional view of a substrate for a semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1...Base, 2...Lid, 4...Semiconductor chip, 7゜15...Heater, 8, 16...Switching element, 11...Plate, 13...Semiconductor device . Applicant's agent Inomata Kiyokuchi 62 and 63 Figure
Claims (1)
ケージ内に設けられ前記半導体チップを加熱するヒータ
と、 一定温度以下でヒータを電源に接続するスイッチング要
素とを具備してなる半導体装置。 ２、スイッチング要素がバイメタルである特許請求の範
囲第１項記載の半導体装置。 ３、スイッチング要素が−２０℃ないし−３０℃でスイ
ッチングする特許請求の範囲第１項記載の半導体装置。 ４、半導体装置が実装される板体からなり、この板体内
に埋設されるヒータと、一定温度以下でヒータを電源に
接続するスイッチング要素とを具備してなる半導体装置
用基板。 ５、スイッチング要素がバイメタルである特許請求の範
囲第４項記載の半導体装置用基板。 ６、スイッチング要素が−２０℃ないし −３０℃でスイッチングする特許請求の範囲第４項記載
の半導体装置用基板。[Claims] 1. A semiconductor chip, a package in which the semiconductor chip is housed, a heater provided in the package to heat the semiconductor chip, and a switching element that connects the heater to a power source at a temperature below a certain temperature. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the switching element is a bimetal. 3. The semiconductor device according to claim 1, wherein the switching element switches at -20°C to -30°C. 4. A semiconductor device substrate comprising a plate on which a semiconductor device is mounted, a heater embedded in the plate, and a switching element that connects the heater to a power source at a temperature below a certain temperature. 5. The substrate for a semiconductor device according to claim 4, wherein the switching element is a bimetal. 6. The substrate for a semiconductor device according to claim 4, wherein the switching element switches at -20°C to -30°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10566685A JPS61264744A (en) | 1985-05-17 | 1985-05-17 | Semiconductor device and substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10566685A JPS61264744A (en) | 1985-05-17 | 1985-05-17 | Semiconductor device and substrate for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61264744A true JPS61264744A (en) | 1986-11-22 |
Family
ID=14413758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10566685A Pending JPS61264744A (en) | 1985-05-17 | 1985-05-17 | Semiconductor device and substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61264744A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01138742A (en) * | 1987-11-26 | 1989-05-31 | Hitachi Ltd | Semiconductor integrated circuit module |
| GB2440416A (en) * | 2006-07-21 | 2008-01-30 | Denso Corp | Resin case with resin seal and temperature consideration for multiple circuit devices |
-
1985
- 1985-05-17 JP JP10566685A patent/JPS61264744A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01138742A (en) * | 1987-11-26 | 1989-05-31 | Hitachi Ltd | Semiconductor integrated circuit module |
| GB2440416A (en) * | 2006-07-21 | 2008-01-30 | Denso Corp | Resin case with resin seal and temperature consideration for multiple circuit devices |
| US7473118B2 (en) | 2006-07-21 | 2009-01-06 | Denso Corporation | Resin sealing type circuit device |
| GB2440416B (en) * | 2006-07-21 | 2011-08-17 | Denso Corp | Resin sealing type circuit device |
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