JPH0787229B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0787229B2 JPH0787229B2 JP63111245A JP11124588A JPH0787229B2 JP H0787229 B2 JPH0787229 B2 JP H0787229B2 JP 63111245 A JP63111245 A JP 63111245A JP 11124588 A JP11124588 A JP 11124588A JP H0787229 B2 JPH0787229 B2 JP H0787229B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- heat dissipation
- resin
- external electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、放熱基板上に設けられた半導体チップと、
この半導体チップに内部リード線を介して電気的に接続
された外部電極端子とを樹脂で封止した半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a semiconductor chip provided on a heat dissipation substrate,
The present invention relates to a semiconductor device in which an external electrode terminal electrically connected to this semiconductor chip via an internal lead wire is sealed with a resin.
第２図は、この種の半導体装置の従来例の１つである電
力用半導体モジュールを一部切り欠いて示す斜視図であ
る。図において、金属材料からなる放熱基板１上には絶
縁基板２が半田付けされており、その絶縁基板２上には
外部電極端子の１つである概形Ｌ字状の三相入力端子３
が３つ、その下辺部3aを半田付けされている。そして、
各三相入力端子３の下辺部3a上には、銅やモリブデンな
どの熱緩衝材11を介して、ダイオードなどの整流用素子
の形成された半導体チップ４が各々２個宛、都合６個半
田付けされている。また、別の外部電極端子である概形
逆Ｔ字状の直流出力端子５が２つ、半導体チップ４の上
方に配置され、各直流出力端子５に対してそれぞれ３つ
の半導体チップ４が内部リード線６を介して半田付けさ
れ、以上の結線によって三相ブリッジが構成されてい
る。FIG. 2 is a perspective view showing a power semiconductor module, which is one of conventional examples of this type of semiconductor device, with a part thereof cut away. In the figure, an insulating substrate 2 is soldered on a heat dissipation substrate 1 made of a metal material, and a substantially L-shaped three-phase input terminal 3 which is one of external electrode terminals is provided on the insulating substrate 2.
3 and their lower side portions 3a are soldered. And
On the lower side portion 3a of each three-phase input terminal 3, two semiconductor chips 4 each having a rectifying element such as a diode formed thereon are provided with a thermal buffer material 11 such as copper or molybdenum, for a total of 6 pieces. It is attached. In addition, two external inverted T-shaped DC output terminals 5 which are other external electrode terminals are arranged above the semiconductor chip 4, and three semiconductor chips 4 are internally lead to each DC output terminal 5. Soldered via the wire 6, the three-phase bridge is constituted by the above connection.
放熱基板１上に設けられた上記の各部材は、放熱基板１
上に別に接着固定されるケース７によって全体を囲ま
れ、そのケース７内にシリコンゲルなどのゲル状樹脂８
を注入されたあと、エポキシ系樹脂９で封止されて整流
用６素子入りの電力用半導体モジュールとされる。The above-mentioned members provided on the heat dissipation board 1 are
The entire case is surrounded by a case 7 which is separately adhered and fixed on the top, and a gel-like resin 8 such as silicon gel is placed in the case 7.
After being injected, it is sealed with an epoxy resin 9 to form a power semiconductor module containing 6 elements for rectification.
しかしながら、上記構成の半導体装置では、ケース７内
に注入されたゲル状樹脂が半導体チップ４の発熱や周囲
温度の変化によって熱膨張を起すと、ゲル状樹脂内に浮
いた状態で配置されている直流出力端子５にゲル状樹脂
による熱応力が生じ、その力が内部リード線６を介して
半導体チップ４に及び、故障の原因になるという問題点
があった。特に、図示例のようにゲル状樹脂８とエポキ
シ系樹脂９とによる二層封止の場合、半導体装置が通常
使用される（−40℃）〜（＋150℃）の温度範囲では、
後者の熱膨張係数が前者のそれよりも大きいため、ゲル
状樹脂８の熱膨張が妨げられて、この熱応力は特に大き
くなり、上記の問題の発生が顕著となる。However, in the semiconductor device having the above configuration, when the gel-like resin injected into the case 7 causes thermal expansion due to heat generation of the semiconductor chip 4 or a change in ambient temperature, the gel-like resin is placed in a state of floating in the gel-like resin. There is a problem that thermal stress due to the gel-like resin is generated in the DC output terminal 5, and the force is applied to the semiconductor chip 4 via the internal lead wire 6 and causes a failure. In particular, in the case of the two-layer sealing with the gel-like resin 8 and the epoxy resin 9 as shown in the example, in the temperature range (-40 ° C) to (+ 150 ° C) where the semiconductor device is normally used
Since the thermal expansion coefficient of the latter is larger than that of the former, the thermal expansion of the gel-like resin 8 is hindered, the thermal stress becomes particularly large, and the above-mentioned problem becomes remarkable.
この発明は、このような問題点を解消するためになされ
たもので、熱応力が半導体チップに及ぶのを軽減した半
導体装置を得ることを目的とする。The present invention has been made in order to solve such a problem, and an object thereof is to obtain a semiconductor device in which thermal stress is prevented from reaching a semiconductor chip.
この発明に係る半導体装置は、放熱基板上に設けられた
半導体チップと、この半導体チップに内部リード線を介
して電気的に接続された外部電極端子とを樹脂で封止し
た半導体装置である。そして、放熱基板は絶縁材料によ
って形成され、外部電極は主部と、一対の下端部とを有
する。ここで主部は半導体チップの上方に形成され、一
対の下端部は半導体チップに対して互いに反対側で放熱
基板上に固着されている。A semiconductor device according to the present invention is a semiconductor device in which a semiconductor chip provided on a heat dissipation substrate and an external electrode terminal electrically connected to the semiconductor chip via an internal lead wire are sealed with resin. The heat dissipation substrate is made of an insulating material, and the external electrode has a main portion and a pair of lower end portions. Here, the main portion is formed above the semiconductor chip, and the pair of lower end portions are fixed on the heat dissipation substrate on opposite sides of the semiconductor chip.
この発明においては、封止に用いられる樹脂が熱膨張し
て、外部電極端子に熱応力が生じても、外部電極端子の
一対の下端部が放熱基板上に直接固着されているため変
位が少なく、しかも主部が半導体チップの上方に形成さ
れている。したがってその熱応力が内部リード線を介し
て半導体チップに及ぶのが軽減される。In the present invention, even if the resin used for sealing thermally expands and thermal stress is generated in the external electrode terminals, the pair of lower end portions of the external electrode terminals are directly fixed on the heat dissipation board, so that the displacement is small. Moreover, the main part is formed above the semiconductor chip. Therefore, the thermal stress on the semiconductor chip via the internal lead wires is reduced.
第１図はこの発明による半導体装置の一実施例である整
流用６素子入りの電力用半導体モジュールを一部切り欠
いて示す斜視図であり、3,4,6〜9,11は上記従来装置と
全く同一のものである。このモジュールでは、放熱基板
10は（たとえばビット基板（商品名）などの）絶縁材料
によって形成されており、したがって放熱基板10上には
別に絶縁基板は設けられない。すなわち、外部電極端子
の１つである三相入力端子３の下辺部3aは直接放熱基板
10上に半田付けされている。また、別の外部電極端子で
ある２つの直流出力端子５は概形逆Ｔ字状で、その下辺
部5aの両端に取付脚5bが形成されており、この取付脚5b
を放熱基板10上に半田付けすることによって、放熱基板
10上に固着されている。そして下辺部5aは半導体チップ
４の上方に形成されているので、直流出力端子５は半導
体チップ４を跨いで形成されている。放熱基板10が絶縁
材料で形成されているため、２つの直流出力端子５の間
の電気的絶縁性も確保されている。各直流出力端子５に
対してそれぞれ３つの半導体チップ４が内部リード線６
を介して半田付けされ、以上の結線によって三相ブリッ
ジが構成されること、およびこれらの部材が放熱基板10
上に別に接着固定されるケース７によって全体を囲ま
れ、そのケース７内にシリコンゲルなどのゲル状樹脂８
が注入され、エポキシ系樹脂９で封止されて整流用６素
子入りの電力用半導体モジュールとされることは従来装
置の場合と同様である。FIG. 1 is a perspective view showing a power semiconductor module containing 6 elements for rectification, which is an embodiment of a semiconductor device according to the present invention, with a part cut away, and 3, 4, 6, 9 and 11 are the conventional devices. Is exactly the same as. In this module, the heat dissipation board
Since 10 is formed of an insulating material (for example, a bit board (trade name)), a separate insulating board is not provided on the heat dissipation board 10. That is, the lower side 3a of the three-phase input terminal 3, which is one of the external electrode terminals, is directly connected to the heat dissipation board.
10 is soldered on. The two DC output terminals 5, which are the other external electrode terminals, are generally inverted T-shaped, and mounting legs 5b are formed at both ends of the lower side 5a thereof.
By soldering the
Sticked on 10. Since the lower side portion 5a is formed above the semiconductor chip 4, the DC output terminal 5 is formed so as to straddle the semiconductor chip 4. Since the heat dissipation board 10 is made of an insulating material, electrical insulation between the two DC output terminals 5 is also ensured. Three semiconductor chips 4 are provided for each DC output terminal 5 and an internal lead wire 6 is provided.
That the three-phase bridge is configured by the above wiring, and these members are connected to the heat dissipation board 10.
The entire case is surrounded by a case 7 which is separately adhered and fixed on the top, and a gel-like resin 8 such as silicon gel is placed in the case 7.
Is injected and sealed with epoxy resin 9 to form a power semiconductor module containing 6 rectifying elements, as in the case of the conventional device.
上記構成のモジュールでは、ケース７内に注入されたゲ
ル状樹脂が半導体チップ４の発熱や周囲温度の変化によ
って熱膨張を起すのに伴って、直流出力端子５に熱応力
が生じても、直流出力端子５の一対の下端部つまり取付
脚5bが放熱基板10上に直接固着されているため、熱応力
による変位は小さく抑えられる。特に下辺部5aは一対の
下端部5bによって固定されるので、その熱応力が内部リ
ード線６を介して下辺部5aの下方に位置する半導体チッ
プ４に作用することはほとんどなく、熱応力に起因する
半導体チップ４の故障が確実に回避される。In the module having the above-mentioned configuration, even if the gel-like resin injected into the case 7 causes thermal expansion of the semiconductor chip 4 due to the heat generation of the semiconductor chip 4 or the change of the ambient temperature, thermal stress is generated in the DC output terminal 5, Since the pair of lower end portions of the output terminal 5, that is, the mounting legs 5b are directly fixed on the heat dissipation board 10, the displacement due to thermal stress can be suppressed to be small. In particular, since the lower side portion 5a is fixed by the pair of lower end portions 5b, its thermal stress hardly acts on the semiconductor chip 4 located below the lower side portion 5a via the internal lead wires 6, and The failure of the semiconductor chip 4 is surely avoided.
なお、上記実施例においては整流用６素子入りの電力用
半導体モジュールの場合について説明したが、これに限
らずサイリスタ・モジュールやトランジスタ・モジュー
ルなどにも同様に適用することができる。樹脂封止が一
層によってなされている場合も、この発明を利用可能で
ある。In the above embodiments, the case of the power semiconductor module containing 6 rectifying elements has been described, but the present invention is not limited to this, and can be similarly applied to a thyristor module or a transistor module. The present invention can be used even when the resin sealing is performed by one layer.
以上のように、この発明によれば、封止に用いられる樹
脂が熱膨張して、外部電極端子に熱応力が生じても、外
部電極端子の一対の下端部が放熱基板上に直接固着され
ていてその変位が少なく、主部が半導体チップの上方に
形成されているため、熱応力が内部リード線を介して半
導体チップに及ぶ作用が緩和され、熱応力に起因する断
線や半導体チップの故障が回避されて半導体装置の信頼
性が向上する。As described above, according to the present invention, even if the resin used for sealing is thermally expanded and thermal stress is generated in the external electrode terminals, the pair of lower end portions of the external electrode terminals are directly fixed onto the heat dissipation board. Since the displacement is small and the main part is formed above the semiconductor chip, the effect of thermal stress exerted on the semiconductor chip via the internal lead wires is mitigated, and disconnection or semiconductor chip failure due to thermal stress occurs. Is avoided and the reliability of the semiconductor device is improved.
第１図は、この発明による半導体装置の一実施例を示す
一部切欠き斜視図、第２図は従来の半導体装置を示す一
部切欠き斜視図である。 図において、1,10は放熱基板、４は半導体チップ、５は
外部電極端子の１つである直流出力端子、5bは直流出力
端子の取付脚、６は内部リード線、８はゲル状樹脂、９
はエポキシ系樹脂である。 なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a partially cutaway perspective view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a partially cutaway perspective view showing a conventional semiconductor device. In the figure, 1 and 10 are heat dissipation boards, 4 is a semiconductor chip, 5 is a DC output terminal which is one of external electrode terminals, 5b is a mounting leg of the DC output terminal, 6 is an internal lead wire, 8 is a gel resin, 9
Is an epoxy resin. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
この半導体チップに内部リード線を介して電気的に接続
された外部電極端子とを樹脂で封止した半導体装置にお
いて、 前記放熱基板は絶縁材料によって形成され、 前記外部電極は主部と、一対の下端部とを有し、 前記主部は前記半導体チップの上方に形成され、前記一
対の下端部な前記半導体チップに対して互いに反対側で
前記放熱基板上に固着されたことを特徴とする半導体装
置。1. A semiconductor chip provided on a heat dissipation substrate,
In a semiconductor device in which an external electrode terminal electrically connected to this semiconductor chip via an internal lead wire is sealed with a resin, the heat dissipation substrate is formed of an insulating material, and the external electrode includes a main portion and a pair of external electrodes. A lower end portion, the main portion is formed above the semiconductor chip, and is fixed on the heat dissipation substrate on opposite sides of the pair of lower end portions of the semiconductor chip. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63111245A JPH0787229B2 (en) | 1988-05-06 | 1988-05-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63111245A JPH0787229B2 (en) | 1988-05-06 | 1988-05-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01281759A JPH01281759A (en) | 1989-11-13 |
| JPH0787229B2 true JPH0787229B2 (en) | 1995-09-20 |
Family
ID=14556268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63111245A Expired - Fee Related JPH0787229B2 (en) | 1988-05-06 | 1988-05-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787229B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5339800B2 (en) | 2008-07-10 | 2013-11-13 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
| CN102366839B (en) * | 2011-09-28 | 2014-04-02 | 哈尔滨电机厂有限责任公司 | Method for preparing rod-like ferrocobalt alloy powder without adopting template |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6346754A (en) * | 1986-08-15 | 1988-02-27 | Hitachi Ltd | Mold type electronic device |
-
1988
- 1988-05-06 JP JP63111245A patent/JPH0787229B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01281759A (en) | 1989-11-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |