JPS62104058A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62104058A JPS62104058A JP60121120A JP12112085A JPS62104058A JP S62104058 A JPS62104058 A JP S62104058A JP 60121120 A JP60121120 A JP 60121120A JP 12112085 A JP12112085 A JP 12112085A JP S62104058 A JPS62104058 A JP S62104058A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- shape
- semiconductor device
- electrode plates
- resin
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関し、とりわけ樹脂封止形半
導体装置の□電極形状に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a square electrode shape of a resin-sealed semiconductor device.
第７図は従来の半導体装置を示す斜視図であり、ここで
はインバータ用６素子入り電力用半導体モジュールを例
にして示している。図において、１は絶縁性放熱基板、
２は該絶縁性放熱基板１上に設けられた導電層、３は直
流入力端子のプラス側、４は直流入力端子のマイナス側
、５ａ〜５Ｃは三相交流出力端子、６ａ〜６Ｃはベース
信号端子、７ａ〜７Ｃはエミッタ信号端子であり、上記
直流入゛力端子３，４．上記三相交流出力端子５ａ〜５
Ｃ１上記ベース信号端子６ａ〜６Ｃ及び上記エミッタ信
号端子７ａ〜７Ｃは上記導電層２上にハンダ付けされて
いる。８は電力用半導体チップ、９は該電力用半導体チ
ップ８と上記導電層２とをつなぐアルミワイヤである。FIG. 7 is a perspective view showing a conventional semiconductor device, in which a power semiconductor module with six elements for an inverter is shown as an example. In the figure, 1 is an insulating heat dissipation board;
2 is a conductive layer provided on the insulating heat sink 1, 3 is the positive side of the DC input terminal, 4 is the negative side of the DC input terminal, 5a to 5C are three-phase AC output terminals, and 6a to 6C are base signals. Terminals 7a to 7C are emitter signal terminals, and the DC input terminals 3, 4 . The above three-phase AC output terminals 5a to 5
C1 The base signal terminals 6a to 6C and the emitter signal terminals 7a to 7C are soldered onto the conductive layer 2. 8 is a power semiconductor chip, and 9 is an aluminum wire connecting the power semiconductor chip 8 and the conductive layer 2.
この種の半導体装置においては、放熱基板１上に導電層
２を設け、さらにその上に直流入力端子３．４．三相交
流出力端子５ａ〜５ ｃ ＋ ベース信号端子６ａ〜５
ｃ、エミッタ信号端子７ａ〜７ｃ＋及び半導体チップ８
をハンダ付けし、該チップ８と導電層２をアルミワイヤ
９でつなぐ。その後基板１にケースを接着しシリコーン
ゲルの注入を行い、最後にエポキシ樹脂にて封止するよ
うにしている。In this type of semiconductor device, a conductive layer 2 is provided on a heat dissipation substrate 1, and DC input terminals 3, 4, . Three-phase AC output terminals 5a-5c + base signal terminals 6a-5
c, emitter signal terminals 7a to 7c+ and semiconductor chip 8
is soldered, and the chip 8 and the conductive layer 2 are connected with an aluminum wire 9. Thereafter, the case is bonded to the substrate 1, silicone gel is injected, and finally the case is sealed with epoxy resin.
従来の半導体装置は、以上のように構成されており、電
極類が樹脂に固定されてしまうため、温度変動時に生じ
る熱ひずみ、熱疲労などによって絶縁性放熱基板の絶縁
層や導電層が上記電極類のハンダ付部から剥がれたり、
ひび割れたりし、これが絶縁不良、導通不良、短絡など
を引き起こす原因となっていた。Conventional semiconductor devices are constructed as described above, and since the electrodes are fixed to the resin, the insulating layer and conductive layer of the insulating heat dissipating substrate may be damaged due to thermal strain, thermal fatigue, etc. that occur during temperature fluctuations. It may peel off from the soldered part of the
This caused cracks, which caused poor insulation, poor continuity, and short circuits.
この発明は上記のような問題点を解消するためになされ
たもので、温度変動時に樹脂に固定された電極類と絶縁
性放熱基板との間に生じるひずみを吸収することができ
る半導体装置を提供することを目的とする。This invention was made to solve the above-mentioned problems, and provides a semiconductor device that can absorb the strain that occurs between electrodes fixed to resin and an insulating heat-dissipating substrate during temperature fluctuations. The purpose is to
この発明に係る半導体装置は、電極の一部分を「Ｓ」字
形、または「コ」字形に加工するか、もしくはその両者
併用の加工を行ったものである。In the semiconductor device according to the present invention, a portion of the electrode is processed into an "S" shape, a "U" shape, or a combination of both.
この発明においては、電極の一部に「Ｓ」字形または「
コ」字形、もしくはその両者併用の加工がなされたこと
から、該加工部で樹脂に固定された電極と絶縁性放熱基
板との間のひずみが吸収され、絶縁不良、導電不良、短
絡などの不具合はほとんど発生しない。In this invention, a part of the electrode has an "S" shape or "
Because the U-shape or a combination of both is processed, the strain between the electrode fixed to the resin and the insulating heat dissipation board is absorbed by the processed part, resulting in problems such as poor insulation, poor conductivity, and short circuits. rarely occurs.
以下、この発明の一実施例を第１図〜第３図を用いて説
明する。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
第１図は、本発明の一実施例による半導体装置を示す斜
視図、第２図はエミッタ信号端子の詳細、第３図はベー
ス信号端子の詳細を各々三角法で描いた図である０図中
、第７図と同一符号は同一部分を示す０図において、１
１は導電層２の上にハンダ付けされその一部分に電極の
厚さ方向に「コ」字形加工がなされた直流入力端子のプ
ラス側、１２は該プラス側直流入力端子１１と同様の加
工がなされた直流入力端子のマイナス側、１３８〜１３
ｃは上記プラス側直流入力端子１１と同様の加工がなさ
れた三相交流出力端子、１４ａ−１４Ｃは上記導電層２
上にハンダ付けされその一部分が電極の厚みの垂直方向
に「Ｓ」字形抜き加工がなされたベース信号端子、１５
２〜１５Ｃは該ベース信号端子１４３〜１４Ｃと同様の
加工がなされたエミッタ信号端子である。FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing details of an emitter signal terminal, and FIG. 3 is a diagram showing details of a base signal terminal using trigonometry. In Figure 0, the same reference numerals as in Figure 7 indicate the same parts.
Reference numeral 1 denotes the positive side of a DC input terminal soldered onto the conductive layer 2 and a part thereof is processed into a "U" shape in the thickness direction of the electrode, and 12 is a positive side DC input terminal which is processed in the same way as the positive side DC input terminal 11. Negative side of DC input terminal, 138 to 13
c is a three-phase AC output terminal processed in the same way as the positive side DC input terminal 11, and 14a-14C are the conductive layers 2
A base signal terminal soldered on top and a part of which has an "S"-shaped cutout in the direction perpendicular to the thickness of the electrode, 15
2 to 15C are emitter signal terminals processed in the same manner as the base signal terminals 143 to 14C.
次に作用効果について第４図、第５図を用いて説明する
。第４図は電極を「コ」字形加工した場合の電力用半導
体モジュールの一部断面図であり図において、２１はエ
ポキシ樹脂、２２はシリコーンゲル、３１はシリコーン
ゲル膨張時の力を概念的に示した矢印、３２は電極の上
方向へ引張られる力を概念的に示した矢印である。Next, the functions and effects will be explained using FIGS. 4 and 5. Figure 4 is a partial cross-sectional view of a power semiconductor module in which the electrodes are processed into a U-shape. The arrow 32 shown conceptually indicates the force that pulls the electrode upward.
温度変動時にシリコーンゲル２２が熱膨張などを起こし
電極１２に上方向の引張り力３２がかかった場合、電極
１２の板厚方向に「コ」字形加工された部分が第４図（
ｂｌに示すように上方に伸びるので、電極１２と絶縁性
放熱基板１との接合部に過大な力がかかることが無くな
る。When the silicone gel 22 thermally expands during temperature fluctuations and an upward tensile force 32 is applied to the electrode 12, the U-shaped portion of the electrode 12 in the thickness direction becomes
Since it extends upward as shown in bl, excessive force is not applied to the joint between the electrode 12 and the insulating heat dissipating substrate 1.
また第５図は電極を「Ｓ」字形加工した場合の電力用半
導体モジュールの一部断面図であるが、この場合も温度
変動時には上述の場合と同様に、電極１４ａの板厚垂直
方向にｒｓＪ字形加工された部分が第５回申）に示す様
に伸び、電極１４ａ上方向への引張り力を吸収して、電
極１４ａと絶縁性放熱基板１との間の接合部に過大な力
がかかることをなくする。よって電極のハンダ付部での
絶縁不良、導電不良、短絡などの不具合を防ぐことがで
きる。FIG. 5 is a partial cross-sectional view of a power semiconductor module in which the electrodes are processed into an "S" shape. In this case as well, when the temperature fluctuates, rsJ The shaped part expands as shown in the fifth report) and absorbs the upward tensile force of the electrode 14a, and excessive force is applied to the joint between the electrode 14a and the insulating heat dissipation substrate 1. Eliminate things. Therefore, problems such as poor insulation, poor conductivity, and short circuits at the soldered portions of the electrodes can be prevented.
今、上方向への引張り力のみに対する作用について説明
したが、絶縁性放熱基板１とエポキシ樹脂２１との間に
ひずみが起り、横方向の力が電極にかかったり、また上
方向、横方向などの合成力が電極にかかった場合も第４
図、第５図に示したと同様に電極の「コ」字形またはｒ
ｓＪ字形加工部が変形して、その力を吸収するので放熱
基板１と電極との接合部に過大な力がかかることは無い
。Although we have just explained the effect on the upward tensile force, strain occurs between the insulating heat dissipating substrate 1 and the epoxy resin 21, and a lateral force is applied to the electrode, and the upward, lateral, etc. When the resultant force of is applied to the electrode, the fourth
The “U” shape or r shape of the electrode as shown in FIG.
Since the sJ-shaped processed portion deforms and absorbs the force, no excessive force is applied to the joint between the heat dissipation substrate 1 and the electrode.
次に、第６図を用いて本発明の他の実施例について説明
する。第６図はこの発明の他の実施例による半導体装置
を示し、１本の電極にｒｓＪ字形加工と「コ」字形加工
とを併用したものを三角法で描いた図である。このｒｓ
Ｊ、ｒコ」字形併用加工の場合においても、上記実施例
と同様もしくはそれ以上の効果が得られることは明白で
ある。Next, another embodiment of the present invention will be described using FIG. 6. FIG. 6 shows a semiconductor device according to another embodiment of the present invention, and is a trigonometric diagram showing a semiconductor device in which both rsJ-shaped processing and "U"-shaped processing are applied to one electrode. This rs
It is clear that effects similar to or better than those of the above embodiments can be obtained even in the case of J and R-shaped combination processing.
なお第６図においては、電極の板厚方向への「コ」字形
加工と電極の板厚と垂直方向へのｒＳＪ字形加工との併
用例を示したが、これは電極の板厚方向へのｒｓＪ字形
加工と、電極の板厚と垂直方向への「コ」字形加工との
併用を行なっても同様の効果があることは明白である。Note that Fig. 6 shows an example of a combination of "U"-shaped processing in the direction of the electrode plate thickness and rSJ-shaped processing in the direction perpendicular to the electrode plate thickness. It is clear that the same effect can be obtained by combining the rsJ-shaped processing and the "U"-shaped processing in the direction perpendicular to the plate thickness of the electrode.
また本実施例においては、絶縁性放熱基板を使用した場
合について説明したが、これは金属ベース板上に絶縁基
板を載置した場合でも同様の効果を奏する。Further, in this embodiment, a case has been described in which an insulating heat dissipation substrate is used, but the same effect can be obtained even when an insulating substrate is placed on a metal base plate.
以上の様に、この発明によれば、電極の一部を−「Ｓ」
字形又は「コ」字形加工もしくはその併用加工をしたの
で、電極と絶縁形成熱基板との間の接合部に過大な力が
かかからず、絶縁不良、導通不良、短絡などの不具合を
防ぐことができる効果がある。As described above, according to the present invention, a part of the electrode is
Because it is processed into a letter or "U" shape or a combination thereof, excessive force is not applied to the joint between the electrode and the insulated thermal board, preventing problems such as poor insulation, poor continuity, and short circuits. It has the effect of
第１図はこの発明の一実施例による半導体装置を示す斜
視図、第２図（ａ）〜（Ｃ）は各々第１図に示した半導
体装置においてその一部が電極の厚みと垂直方向に「Ｓ
」字形加工された電極の正面図、側面図及び平面図、第
３図（ａ）〜（Ｃ）は各々第２図同様電極の厚み方向に
「コ」字形加工された電極の正面図、側面図及び平面図
、第４図（ａ）、 （ｂ）は各々第１図に示した半導体
装置において電極の厚み方向に「コ」字形加工された電
極がどの様に作用するかを示した一部断面図、第５図＋
８）、 （ｂ）は各々第４図同様電極の厚みと垂直方向
にｒｓＪ字形加工された電極がどの様に作用するかを示
した一部断面図、第６図（ａ）〜（Ｃ）は各々この発明
の他の実施例による半導体装置の電極の正面図、側面図
及び平面図、第７図は従来の半導体装置を示す斜視図で
ある。
１・・・絶縁性放熱基板、１１，１２，１３ａ＝１３ｃ
、１４ａ 〜１４ｃ、１５ａ 〜１５ｃ・・・電極、８
・・・半導体チップ、２１−・・・樹脂。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to (C) each show a part of the semiconductor device shown in FIG. 1 in a direction perpendicular to the thickness of an electrode. “S.
Figures 3 (a) to (C) are a front view, a side view, and a plan view of an electrode processed into a "U" shape in the thickness direction of the electrode, respectively, similar to Figure 2. The figure, plan view, and FIGS. 4(a) and 4(b) each show how the electrodes, which are shaped like a "U" in the thickness direction of the electrodes, act in the semiconductor device shown in FIG. Partial sectional view, Figure 5+
8) and (b) are partial cross-sectional views showing how the rsJ-shaped electrode works in the direction perpendicular to the thickness of the electrode, similar to Fig. 4, and Fig. 6 (a) to (C). 7 are a front view, a side view, and a plan view of electrodes of a semiconductor device according to other embodiments of the present invention, respectively, and FIG. 7 is a perspective view showing a conventional semiconductor device. 1... Insulating heat dissipation board, 11, 12, 13a=13c
, 14a to 14c, 15a to 15c... electrode, 8
...Semiconductor chip, 21-...Resin. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (4)
その上に電極板、半導体チップをハンダ付けし樹脂封止
を行う半導体装置において、その電極の一部分をＳ字形
またはコ字形に加工したことを特徴とする半導体装置。(1) Providing an insulating layer or an insulating substrate on a metal base plate,
1. A semiconductor device on which an electrode plate and a semiconductor chip are soldered and sealed with resin, characterized in that a part of the electrode is processed into an S-shape or a U-shape.
電極の板厚方向にされていることを特徴とする特許請求
の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the electrode is processed into an S-shape or a U-shape in the thickness direction of the electrode.
電極の板厚と垂直方向に抜き加工で行なわれていること
を特徴とする特許請求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the electrode is formed into an S-shape or a U-shape by punching in a direction perpendicular to the plate thickness of the electrode.
加工が行なわれていることを特徴とする特許請求の範囲
第１項記載の半導体装置。(4) The semiconductor device according to claim 1, wherein each of the electrodes is processed into an S-shape and a U-shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60121120A JPS62104058A (en) | 1985-06-04 | 1985-06-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60121120A JPS62104058A (en) | 1985-06-04 | 1985-06-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62104058A true JPS62104058A (en) | 1987-05-14 |
Family
ID=14803375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60121120A Pending JPS62104058A (en) | 1985-06-04 | 1985-06-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62104058A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01153647U (en) * | 1988-04-05 | 1989-10-23 | ||
| JPH0432256A (en) * | 1990-05-29 | 1992-02-04 | Sansha Electric Mfg Co Ltd | Semiconductor device |
| JPH062714U (en) * | 1992-06-03 | 1994-01-14 | 株式会社三社電機製作所 | Power semiconductor module |
| JP2006245362A (en) * | 2005-03-04 | 2006-09-14 | Mitsubishi Electric Corp | Semiconductor apparatus and electrode terminal used for the same |
| JP2011018933A (en) * | 2010-09-16 | 2011-01-27 | Mitsubishi Electric Corp | Semiconductor device, and method of manufacturing the same |
| CN107622978A (en) * | 2017-10-13 | 2018-01-23 | 中国电子科技集团公司第十三研究所 | A kind of ceramic package shell |
-
1985
- 1985-06-04 JP JP60121120A patent/JPS62104058A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01153647U (en) * | 1988-04-05 | 1989-10-23 | ||
| JPH0432256A (en) * | 1990-05-29 | 1992-02-04 | Sansha Electric Mfg Co Ltd | Semiconductor device |
| JPH062714U (en) * | 1992-06-03 | 1994-01-14 | 株式会社三社電機製作所 | Power semiconductor module |
| JP2006245362A (en) * | 2005-03-04 | 2006-09-14 | Mitsubishi Electric Corp | Semiconductor apparatus and electrode terminal used for the same |
| JP2011018933A (en) * | 2010-09-16 | 2011-01-27 | Mitsubishi Electric Corp | Semiconductor device, and method of manufacturing the same |
| CN107622978A (en) * | 2017-10-13 | 2018-01-23 | 中国电子科技集团公司第十三研究所 | A kind of ceramic package shell |
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