JPH0766239A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0766239A
JPH0766239A JP21056993A JP21056993A JPH0766239A JP H0766239 A JPH0766239 A JP H0766239A JP 21056993 A JP21056993 A JP 21056993A JP 21056993 A JP21056993 A JP 21056993A JP H0766239 A JPH0766239 A JP H0766239A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor chip
conductive particles
conductive adhesive
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21056993A
Other languages
Japanese (ja)
Inventor
Masakazu Yamazoe
正和 山添
Kazuhide Ota
和秀 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP21056993A priority Critical patent/JPH0766239A/en
Publication of JPH0766239A publication Critical patent/JPH0766239A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the heat radiating characteristics of a semiconductor device, and to prevent generation of stress by thermal expansion. CONSTITUTION:In the semiconductor device in which the surface 21, where the electrodes 22 and 23 of a semiconductor chip 20 are formed, is adhered to a substrate 11 and the wiring conductor layer fixed to the substrate 11 using a conductive bonding agent, an anisotropic conductive bonding agent 40, having conductive particles 42 and the particles of the diameter smaller than the conductive particles 42, is used as the conductive bonding agent. Besides, the thermal expansion coefficient of the substrate 11 is almost equalized to that of the semiconductor chip 20 in the semiconductor device.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に、放熱特性を良くした半導体装置に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having improved heat dissipation characteristics.

【0002】[0002]

【従来の技術】従来の半導体装置における半導体チップ
の接着構造が特開昭51−115773号公報に開示さ
れている。図4はこの従来例の断面構造を示す。図4に
おいて、ヒートシンクを兼ねたハイブリッドIC用基板
51上に外部リード端子52a、52b、52cが固定
されている。半導体チップ60の電極用パッド62a、
62b、62cが形成された面61が異方性導電接着剤
70によって外部リード端子52a、52b、52c及
び基板51に接着されている。ここで、異方性導電接着
剤70は、ポリマー・バインダー71中に金属粒子72
(直径が10〜20μm)を分散させたものである。こ
の場合、異方性導電接着剤70は、電極用パッド62a
と外部リード端子52a、電極用パッド62bと外部リ
ード端子52b、電極用パッド62cと外部リード端子
52cをそれぞれ電気的に接続する。なお、異方性導電
接着剤70の性質のため、電極用パッド62a、62
b、62c相互間、外部リード端子52a、52b、5
2c相互間及び前記各電極用パッドと前記各外部リード
端子の前記以外の組み合わせの間の電気的絶縁が確保さ
れている。
2. Description of the Related Art An adhesive structure for a semiconductor chip in a conventional semiconductor device is disclosed in JP-A-51-115773. FIG. 4 shows a cross-sectional structure of this conventional example. In FIG. 4, external lead terminals 52a, 52b, 52c are fixed on a hybrid IC substrate 51 that also serves as a heat sink. Electrode pads 62a of the semiconductor chip 60,
The surface 61 on which 62b and 62c are formed is adhered to the external lead terminals 52a, 52b and 52c and the substrate 51 by the anisotropic conductive adhesive 70. Here, the anisotropic conductive adhesive 70 is composed of metal particles 72 in a polymer binder 71.
(Diameter is 10 to 20 μm). In this case, the anisotropic conductive adhesive 70 is applied to the electrode pad 62a.
The external lead terminal 52a, the electrode pad 62b and the external lead terminal 52b, and the electrode pad 62c and the external lead terminal 52c are electrically connected to each other. Due to the nature of the anisotropic conductive adhesive 70, the electrode pads 62a, 62
b, 62c, external lead terminals 52a, 52b, 5
Electrical insulation is secured between 2c and between the electrode pads and the combinations of the external lead terminals other than the above.

【0003】[0003]

【発明が解決しようとする課題】上述の従来例におい
て、異方性導電接着剤70は、電気的特性は良好である
が、熱抵抗が十分に小さくなかった。このため、半導体
チップ60の許容電力損失を大きくすることができなか
った。また、半導体チップ60の発熱による温度上昇に
よって、半導体チップ60と基板51との熱膨張の差が
発生するために、半導体チップ60と基板51との間に
応力が発生し、この応力が半導体装置の劣化の原因とな
った。従って、本発明の課題は、上述の従来例の欠点を
なくし、半導体チップの発熱を良好に基板に伝えること
ができるとともに、熱膨張による応力が発生しないよう
にする半導体装置を提供することである。
In the above-mentioned conventional example, the anisotropic conductive adhesive 70 has good electrical characteristics, but the thermal resistance is not sufficiently small. Therefore, the allowable power loss of the semiconductor chip 60 cannot be increased. Further, a temperature rise due to heat generation of the semiconductor chip 60 causes a difference in thermal expansion between the semiconductor chip 60 and the substrate 51, so that stress is generated between the semiconductor chip 60 and the substrate 51, and this stress is applied to the semiconductor device. Caused the deterioration of. Therefore, an object of the present invention is to provide a semiconductor device which eliminates the above-mentioned drawbacks of the conventional example, can well transmit the heat generation of the semiconductor chip to the substrate, and prevents stress due to thermal expansion from occurring. .

【0004】[0004]

【課題を解決するための手段】上記課題を解決するた
め、本発明の第1の構成は、半導体チップの電極が形成
された面を基板上に固定された配線用導電体層及び前記
基板に導電性接着剤で接着する半導体装置において、前
記導電性接着剤を導電性粒子及びこの導電性粒子よりも
小径の熱伝導性粒子を有する異方性導電接着剤としたこ
とである。更に、第2の構成は、半導体チップの電極が
形成された面を基板上に固定された配線用導電体層及び
前記基板に導電性接着剤で接着する半導体装置におい
て、前記導電性接着剤を導電性粒子及びこの導電性粒子
よりも小径の熱伝導性粒子を有する異方性導電接着剤と
し、前記基板の熱膨張係数と前記半導体チップの熱膨張
係数とをほぼ等しくしたことである。
In order to solve the above-mentioned problems, a first structure of the present invention provides a wiring conductor layer having a surface on which electrodes of a semiconductor chip are formed fixed on a substrate and the substrate. In the semiconductor device adhered with a conductive adhesive, the conductive adhesive is an anisotropic conductive adhesive having conductive particles and heat conductive particles having a diameter smaller than that of the conductive particles. Further, a second configuration is a semiconductor device in which a surface of a semiconductor chip on which electrodes are formed is adhered to a wiring conductor layer fixed on a substrate and the substrate with a conductive adhesive, and the conductive adhesive is used. An anisotropic conductive adhesive having conductive particles and heat conductive particles having a diameter smaller than that of the conductive particles is used, and the coefficient of thermal expansion of the substrate and the coefficient of thermal expansion of the semiconductor chip are made substantially equal.

【0005】[0005]

【作用】上記第1の構成によって、異方性導電接着剤中
の熱伝導性粒子が、異方性導電接着剤の熱抵抗を小さく
する。また、異方性導電接着剤中の導電性粒子が半導体
チップの電極と配線用導電体層との間の電気的接続をす
る。このとき、異方性導電接着剤中の熱伝導性粒子の径
が導電性粒子の径よりも小さいので、熱伝導性粒子の存
在が、導電性粒子による半導体チップの電極と配線用導
電体層との間の電気的接続の妨げにならない。更に、上
記第2の構成によって、上述の第1の構成と同様に異方
性導電接着剤中の熱伝導性粒子が、異方性導電接着剤の
熱抵抗を小さくするとともに、基板と半導体チップの熱
膨張係数をほぼ等しくしているので、半導体チップの発
熱による半導体チップの熱膨張と基板の熱膨張をほぼ等
しくすることができるため、この熱膨張によって、半導
体チップと基板との間において応力がほとんど発生しな
いようにすることができる。
With the first structure, the heat conductive particles in the anisotropic conductive adhesive reduce the thermal resistance of the anisotropic conductive adhesive. In addition, the conductive particles in the anisotropic conductive adhesive make electrical connection between the electrodes of the semiconductor chip and the wiring conductor layer. At this time, since the diameter of the heat conductive particles in the anisotropic conductive adhesive is smaller than the diameter of the conductive particles, the presence of the heat conductive particles means that the conductive particles cause the electrodes of the semiconductor chip and the conductive layer for wiring. Does not interfere with the electrical connection between and. Further, according to the second configuration, the thermally conductive particles in the anisotropic conductive adhesive reduce the thermal resistance of the anisotropic conductive adhesive as in the first configuration described above, and at the same time, the substrate and the semiconductor chip. Since the coefficients of thermal expansion of the semiconductor chips are almost equal to each other, the thermal expansion of the semiconductor chip and the thermal expansion of the substrate due to the heat generation of the semiconductor chip can be almost equal to each other, and this thermal expansion causes stress between the semiconductor chip and the substrate. Can rarely occur.

【0006】[0006]

【実施例】次に、本発明の一実施例を図面を参照して説
明する。図1は本発明の一実施例の断面構造を示し、図
2はこの一実施例の平面を示し、図3は図2のA−A断
面構造を示す。図1〜図3において、ヒートシンクを兼
ねた窒化アルミニウム(AlN)基板11の上に配線用
導電体層12a〜12dが固定されている。この窒化ア
ルミニウム基板11の熱膨張係数は、パワー半導体チッ
プ20の熱膨張係数にほぼ等しい。パワー半導体チップ
20には、パワートランジスタが組み込まれているの
で、このパワートランジスタのエミッタ電極22、ベー
ス電極23及びコレクタ電極24が形成されている。こ
のうち、エミッタ電極22及びベース電極23が形成さ
れている側の面21が配線用導電体層12b、12c及
び基板11に異方性導電接着剤40で接着されている。
コレクタ電極24は、アルミニウムボンディングワイヤ
13によって配線用導電体層12aに接続されている。
また、制御用ICチップ30の電極32、33等が形成
された面31が異方性導電接着剤40によって配線用導
電体層12c、12d及び基板11に接着されている。
異方性導電接着剤40は、バインダー41中に導電性粒
子42及び熱伝導性粒子43を混在させたものである。
このうち、熱伝導性粒子43の径は導電性粒子42の径
よりも小さく形成されている。このため、導電性粒子4
2の径は10〜20μm、熱伝導性粒子43の径は10
μm未満である。また、熱伝導性粒子43の材質はAl
Nであり、導電性粒子42の材質は金属である。更に、
異方性導電接着剤40中には、熱伝導性粒子43が導電
性粒子42よりも多く含まれている。なお、バインダー
41の材質はポリマー等である。
An embodiment of the present invention will be described with reference to the drawings. 1 shows a sectional structure of an embodiment of the present invention, FIG. 2 shows a plane of the embodiment, and FIG. 3 shows an AA sectional structure of FIG. 1 to 3, wiring conductor layers 12a to 12d are fixed on an aluminum nitride (AlN) substrate 11 that also serves as a heat sink. The coefficient of thermal expansion of the aluminum nitride substrate 11 is substantially equal to the coefficient of thermal expansion of the power semiconductor chip 20. Since the power semiconductor chip 20 incorporates a power transistor, an emitter electrode 22, a base electrode 23 and a collector electrode 24 of this power transistor are formed. Of these, the surface 21 on the side where the emitter electrode 22 and the base electrode 23 are formed is bonded to the wiring conductor layers 12b and 12c and the substrate 11 with an anisotropic conductive adhesive 40.
The collector electrode 24 is connected to the wiring conductor layer 12a by the aluminum bonding wire 13.
The surface 31 of the control IC chip 30 on which the electrodes 32, 33, etc. are formed is adhered to the wiring conductor layers 12c, 12d and the substrate 11 by an anisotropic conductive adhesive 40.
The anisotropic conductive adhesive 40 is a mixture of conductive particles 42 and heat conductive particles 43 in a binder 41.
Of these, the diameter of the heat conductive particles 43 is formed smaller than the diameter of the conductive particles 42. Therefore, the conductive particles 4
2 has a diameter of 10 to 20 μm, and the thermally conductive particles 43 have a diameter of 10
It is less than μm. The material of the heat conductive particles 43 is Al
N, and the material of the conductive particles 42 is metal. Furthermore,
The anisotropic conductive adhesive 40 contains more heat conductive particles 43 than the conductive particles 42. The material of the binder 41 is polymer or the like.

【0007】以上の構成によって、本実施例において
は、図1に示すように、導電性粒子42が図示横方向に
一列に並んでいるが、導電性粒子42相互間に隙間が生
じるため、異方性導電接着剤40は、図示縦方向に導電
性を有し、図示横方向には導電性を有しない。また、熱
伝導性粒子43は、その径が導電性粒子42の径よりも
小さいので、導電性粒子42の間に入り込むように分散
されることになる。このため、熱伝導の異方性は生じな
い。なお、本実施例においては、異方性導電接着剤40
の熱伝導の異方性がない方が、パワー半導体チップ20
で発生した熱を異方性導電接着剤40を通じて基板11
へ放熱しやすくなる。なお、図1において、異方性導電
接着剤40は、基板11のうちパワー半導体チップ20
の図示下方に相当する部分の全面に塗布されているが、
異方性導電接着剤40の塗布範囲は、配線用導電体層1
2b、12cのある部分のみでもよい。また、制御用I
Cチップ30と基板11との接着においても、上述のパ
ワー半導体チップ20と基板11との接着と同様の効果
がある。更に、基板11とパワー半導体チップ20の熱
膨張係数をほぼ等しくしているので、パワー半導体チッ
プ20の発熱によるパワー半導体チップ20の熱膨張と
基板11の熱膨張をほぼ等しくすることができるため、
この熱膨張によって、半導体チップ20と基板11との
間において応力がほとんど発生しない。なお、上述の本
実施例において、窒化アルミニウム(AlN)の代わり
に酸化ベリリウム(BeO)を用いることもできる。
With the above structure, in this embodiment, as shown in FIG. 1, the conductive particles 42 are arranged in a row in the lateral direction in the drawing, but since a gap is generated between the conductive particles 42, a difference occurs. The anisotropic conductive adhesive 40 has conductivity in the vertical direction in the drawing, but does not have conductivity in the horizontal direction in the drawing. Further, since the diameter of the heat conductive particles 43 is smaller than the diameter of the conductive particles 42, the heat conductive particles 43 are dispersed so as to enter between the conductive particles 42. Therefore, anisotropy of heat conduction does not occur. In this embodiment, the anisotropic conductive adhesive 40
If there is no anisotropy in heat conduction of the power semiconductor chip 20
The heat generated in the substrate 11 is transferred to the substrate 11 through the anisotropic conductive adhesive 40.
It becomes easy to radiate heat to. In FIG. 1, the anisotropic conductive adhesive 40 is used for the power semiconductor chip 20 of the substrate 11.
Although it is applied to the entire surface of the part corresponding to the lower part of the figure,
The application range of the anisotropic conductive adhesive 40 is the conductor layer 1 for wiring.
Only the portion having 2b and 12c may be used. Also, for control I
Adhesion between the C chip 30 and the substrate 11 also has the same effect as adhesion between the power semiconductor chip 20 and the substrate 11 described above. Furthermore, since the thermal expansion coefficients of the substrate 11 and the power semiconductor chip 20 are made substantially equal, the thermal expansion of the power semiconductor chip 20 and the thermal expansion of the substrate 11 due to the heat generation of the power semiconductor chip 20 can be made substantially equal.
Due to this thermal expansion, stress is hardly generated between the semiconductor chip 20 and the substrate 11. In the above-described embodiment, beryllium oxide (BeO) may be used instead of aluminum nitride (AlN).

【0008】[0008]

【発明の効果】以上詳細に説明したように、本発明の半
導体装置によれば、半導体チップと基板上の配線用導電
体層及び前記基板との接着に異方性導電接着剤を使用し
た半導体装置の放熱特性を著しく向上させることができ
る。このため、半導体チップの許容電力損失を大きくす
ることができる。更に、基板と半導体チップの熱膨張係
数をほぼ等しくすることによって熱膨張による応力の発
生を防ぐことができるので、この応力による半導体装置
の劣化を防ぐことができる。
As described in detail above, according to the semiconductor device of the present invention, a semiconductor using an anisotropic conductive adhesive for bonding the semiconductor chip to the wiring conductor layer on the substrate and the substrate. The heat dissipation characteristics of the device can be significantly improved. Therefore, the allowable power loss of the semiconductor chip can be increased. Further, since the thermal expansion coefficient of the substrate and that of the semiconductor chip are made substantially equal to each other, the stress due to the thermal expansion can be prevented from being generated, so that the deterioration of the semiconductor device due to the stress can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

【図2】本発明の一実施例の平面図である。FIG. 2 is a plan view of an embodiment of the present invention.

【図3】図2のA−A断面図である。3 is a cross-sectional view taken along the line AA of FIG.

【図4】従来例の断面図である。FIG. 4 is a sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

11 基板 12a〜12d 配線用導電体層 20 パワー半導体チップ 21 パワー半導体チップの面 22 エミッタ電極 23 ベース電極 40 異方性導電接着剤 42 導電性粒子 43 熱伝導性粒子 11 Substrate 12a-12d Wiring Conductor Layer 20 Power Semiconductor Chip 21 Surface of Power Semiconductor Chip 22 Emitter Electrode 23 Base Electrode 40 Anisotropic Conductive Adhesive 42 Conductive Particle 43 Thermal Conductive Particle

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップの電極が形成された面を基
板上に固定された配線用導電体層及び前記基板に導電性
接着剤で接着する半導体装置において、 前記導電性接着剤を導電性粒子及びこの導電性粒子より
も小径の熱伝導性粒子を有する異方性導電接着剤とした
ことを特徴とする半導体装置。
1. A semiconductor device in which a surface of a semiconductor chip on which an electrode is formed is adhered to a wiring conductor layer fixed on a substrate and a conductive adhesive, and the conductive adhesive is conductive particles. And a semiconductor device comprising an anisotropic conductive adhesive having heat conductive particles having a diameter smaller than that of the conductive particles.
【請求項2】 半導体チップの電極が形成された面を基
板上に固定された配線用導電体層及び前記基板に導電性
接着剤で接着する半導体装置において、 前記導電性接着剤を導電性粒子及びこの導電性粒子より
も小径の熱伝導性粒子を有する異方性導電接着剤とし、
前記基板の熱膨張係数と前記半導体チップの熱膨張係数
とをほぼ等しくしたことを特徴とする半導体装置。
2. A semiconductor device in which a surface of a semiconductor chip on which electrodes are formed is fixed on a substrate by a wiring conductor layer and the substrate is bonded by a conductive adhesive, wherein the conductive adhesive is conductive particles. And an anisotropic conductive adhesive having heat conductive particles having a smaller diameter than the conductive particles,
A semiconductor device, wherein the coefficient of thermal expansion of the substrate and the coefficient of thermal expansion of the semiconductor chip are made substantially equal.
JP21056993A 1993-08-25 1993-08-25 Semiconductor device Pending JPH0766239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21056993A JPH0766239A (en) 1993-08-25 1993-08-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21056993A JPH0766239A (en) 1993-08-25 1993-08-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0766239A true JPH0766239A (en) 1995-03-10

Family

ID=16591495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21056993A Pending JPH0766239A (en) 1993-08-25 1993-08-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0766239A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006148105A (en) * 2004-11-15 2006-06-08 Samsung Electronics Co Ltd Semiconductor module and its manufacturing method
JP2009289729A (en) * 2008-04-28 2009-12-10 Hitachi Chem Co Ltd Anisotropic conductive film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006148105A (en) * 2004-11-15 2006-06-08 Samsung Electronics Co Ltd Semiconductor module and its manufacturing method
JP2009289729A (en) * 2008-04-28 2009-12-10 Hitachi Chem Co Ltd Anisotropic conductive film

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