JPH0786469A - Electronic part - Google Patents

Electronic part

Info

Publication number
JPH0786469A
JPH0786469A JP5232643A JP23264393A JPH0786469A JP H0786469 A JPH0786469 A JP H0786469A JP 5232643 A JP5232643 A JP 5232643A JP 23264393 A JP23264393 A JP 23264393A JP H0786469 A JPH0786469 A JP H0786469A
Authority
JP
Japan
Prior art keywords
semiconductor element
heat
thermal
wiring layer
conductive member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5232643A
Other languages
Japanese (ja)
Inventor
Katsumi Kuno
勝美 久野
Tomiya Sasaki
富也 佐々木
Hideo Iwasaki
秀夫 岩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5232643A priority Critical patent/JPH0786469A/en
Publication of JPH0786469A publication Critical patent/JPH0786469A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73257Bump and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PURPOSE:To provide an electronic part capable of avoiding degrading the radiation power by reducing the thermal resistance in a connecting member for connecting a semiconductor chip to a wiring layer. CONSTITUTION:It comprises an Si or ceramic substrate 5, wiring layer 4 composed of an insulator and conductor formed on the substrate, thermal-conductor- made columnar members (thermal via-holes) 7 piercing the layer 4, and semiconductor chip 1 secured through a mounting member 2 to the layer 4. Thermally conductive members 8 are disposed near the ends of the thermal via-holes 7 in the member 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、冷却機能を備えたマル
チチップモジュール等の電子部品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component such as a multi-chip module having a cooling function.

【0002】[0002]

【従来の技術】高速高密度回路モジュールを得る手法の
一つに、マルチチップモジュールがある。図8は、マル
チチップモジュールの一例を示す概略図である。このモ
ジュールは、シリコンあるいはセラミックの基板5を主
構造とするパッケージに、複数の半導体素子1を搭載
し、各素子間の配線を絶縁体と導体とからなる配線層4
により行うようにしたものである。基板5の半導体素子
1を搭載した面はキャップ15により封止され、これと
対向する側の面には放熱フィン12が設けられている。
2. Description of the Related Art A multi-chip module is one of the methods for obtaining a high-speed and high-density circuit module. FIG. 8 is a schematic diagram showing an example of a multi-chip module. In this module, a plurality of semiconductor elements 1 are mounted in a package having a silicon or ceramic substrate 5 as a main structure, and wiring between each element is a wiring layer 4 including an insulator and a conductor.
This is done by A surface of the substrate 5 on which the semiconductor element 1 is mounted is sealed by a cap 15, and a heat radiation fin 12 is provided on a surface facing the cap 15.

【0003】熱的な立場からみると、配線層4の大部分
を占める絶縁体にポリイミド等の低熱伝導性材料を使用
すると、半導体素子1から基板5への熱移動に対する抵
抗が大きくなり、何らかの放熱対策を施さなければなら
なくなる。
From a thermal standpoint, when a low thermal conductivity material such as polyimide is used for the insulator that occupies most of the wiring layer 4, the resistance against heat transfer from the semiconductor element 1 to the substrate 5 increases, and It becomes necessary to take heat dissipation measures.

【0004】かかる放熱対策としては、図9に示すよう
に、熱伝導性の高い材料でつくられた微細な柱状部材7
(以下サーマルビア7という)を配線層4の内部を貫通
するように設け、半導体素子1から基板5への熱通路を
構成する試みがなされている。
As a measure against such heat radiation, as shown in FIG. 9, a fine columnar member 7 made of a material having high thermal conductivity is used.
Attempts have been made to form a heat passage from the semiconductor element 1 to the substrate 5 by providing a thermal via 7 (hereinafter referred to as a thermal via) so as to penetrate the inside of the wiring layer 4.

【0005】しかし、半導体素子1で発生した熱の流れ
は、図10に示すように、サーマルビア7の前後で縮小
拡大するため、これにともなう熱抵抗の増加により放熱
性能が低下する。特に、半導体素子1で発生した熱の流
れが縮小してサーマルビア7へ至る過程においては、半
導体素子1を配線層4の表面に接合するための接合部材
であるマウント材2の熱伝導率が小さいため、マウント
材2の内部における熱の流れの縮小により発生する熱抵
抗が大きくなるという問題がある。また、半導体素子1
を実装する際に、マウント材2の内部に気泡が発生する
と、放熱性能の低下はさらに大きくなる。
However, as shown in FIG. 10, the heat flow generated in the semiconductor element 1 contracts and expands before and after the thermal via 7, so that the heat resistance accompanying this increases the heat dissipation performance. In particular, in the process in which the heat flow generated in the semiconductor element 1 is reduced to reach the thermal via 7, the thermal conductivity of the mount material 2 which is a joining member for joining the semiconductor element 1 to the surface of the wiring layer 4 is Since it is small, there is a problem that the thermal resistance generated by the reduction of the heat flow inside the mount material 2 becomes large. In addition, the semiconductor device 1
When air bubbles are generated inside the mount material 2 when mounting, the heat radiation performance is further deteriorated.

【0006】[0006]

【発明が解決しようとする課題】以上述べたように、配
線層の内部を貫通するサーマルビアを有する従来のマル
チチップモジュール等の電子部品においては、各半導体
素子を配線層に接合するためのマウント材の内部におい
て、半導体素子1で発生した熱の流れが縮小してサーマ
ルビア7へ至る過程での熱抵抗が大きくなり放熱性能が
低下するとともに、半導体素子を実装する際、マウント
材の内部に気泡が発生すると放熱性能がさらに低下する
という問題があった。
As described above, in a conventional electronic component such as a multi-chip module having a thermal via penetrating the inside of a wiring layer, a mount for joining each semiconductor element to the wiring layer. Inside the material, the heat flow generated in the semiconductor element 1 is reduced to increase the thermal resistance in the process of reaching the thermal via 7 and the heat radiation performance is deteriorated. There is a problem that the heat dissipation performance is further deteriorated when bubbles are generated.

【0007】本発明は、かかる問題を解決するためにな
されたものであり、マウント材の内部における熱抵抗を
低減することにより、放熱性能の低下を防止することが
可能な電子部品を提供することを目的とする。
The present invention has been made in order to solve such a problem, and provides an electronic component capable of preventing the deterioration of the heat radiation performance by reducing the thermal resistance inside the mount material. With the goal.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明では、基板と、この基板上に形成される絶縁
体及び導体からなる配線層と、この配線層を貫通して設
けられる熱伝導性材料からなる柱状部材と、前記配線層
上に接合部材を介して接合される半導体素子とを有して
なる電子部品であって、前記接合部材内部の前記柱状部
材近傍に熱伝導性部材が設けられていることを特徴とす
る電子部品を提供する。
To achieve the above object, in the present invention, a substrate, a wiring layer made of an insulator and a conductor formed on the substrate, and a wiring layer penetrating the wiring layer are provided. An electronic component comprising a columnar member made of a heat conductive material and a semiconductor element bonded on the wiring layer via a bonding member, wherein the thermal conductivity is provided near the columnar member inside the bonding member. Provided is an electronic component, which is provided with a member.

【0009】[0009]

【作用】上記した構成を有する本発明によれば、接合部
材内部のサーマルビア端部近傍に熱伝導性部材を設ける
ことにより、半導体素子を接合した際、熱伝導性部材と
半導体素子との間に介在する接合部材の厚さを小さくす
ることができるため、半導体素子において発生した熱の
流れの縮小が、接合部材の内部ではなく、半導体素子1
の内部で生ずるようになるため、上記した熱抵抗の低減
を図ることが可能となる。また、上記したような構成に
よれば、接合部材の内部に気泡が発生した場合にも、そ
の気泡による熱通過への影響を小さくすることができ
る。
According to the present invention having the above-described structure, by providing the heat conductive member in the vicinity of the end of the thermal via inside the bonding member, when the semiconductor element is bonded, the heat conductive member and the semiconductor element are separated from each other. Since it is possible to reduce the thickness of the joining member interposed in the semiconductor element, the reduction of the heat flow generated in the semiconductor element does not occur inside the joining member but in the semiconductor element 1
Since it occurs in the inside of the, it is possible to reduce the above-mentioned thermal resistance. Further, according to the above-mentioned configuration, even when bubbles are generated inside the joining member, the influence of the bubbles on heat passage can be reduced.

【0010】[0010]

【実施例】以下、本発明の実施例について、図面を参照
しつつ詳細に説明する。図1は、本発明に係る電子部品
の第1実施例を示す要部断面図である。シリコンあるい
はセラミックの基板5上に形成された配線層4の表面の
ダイパッド3上に、発熱する半導体素子1が接合部材で
あるマウント材2により接合されている。ここで、配線
層4は絶縁体と導体(図示省略)とから構成される。配
線層の大部分を占める絶縁体には、ポリイミド等の熱伝
導性の低い材料が用いられるため、半導体素子1におい
て発生した熱が基板5に伝わる際の障害となる。そこ
で、半導体素子1と基板5との間の伝熱を促進すべく、
配線層4を貫通する微細な柱状部材であるサーマルビア
7が設けられている。サーマルビア7は、熱伝導性の高
い材料で形成する必要があり、配線層4内の導体(例え
ば銅)と同一の材料でつくられることも多い。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of an essential part showing a first embodiment of an electronic component according to the present invention. A semiconductor element 1 that generates heat is bonded to a die pad 3 on the surface of a wiring layer 4 formed on a silicon or ceramic substrate 5 by a mount material 2 that is a bonding member. Here, the wiring layer 4 is composed of an insulator and a conductor (not shown). Since a material having low thermal conductivity such as polyimide is used for the insulator that occupies most of the wiring layer, it becomes an obstacle when the heat generated in the semiconductor element 1 is transferred to the substrate 5. Therefore, in order to promote heat transfer between the semiconductor element 1 and the substrate 5,
A thermal via 7 which is a fine columnar member penetrating the wiring layer 4 is provided. The thermal via 7 needs to be formed of a material having high thermal conductivity, and is often made of the same material as the conductor (for example, copper) in the wiring layer 4.

【0011】サーマルビア7を設けることにより、配線
層4には、熱の通過しやすい場所と、通過しにくい場所
とができる。このため、配線層4の上下では、図10に
示したように、熱の流れの縮小拡大が発生し、それに伴
って熱抵抗が生ずる。この熱抵抗は上記した熱の縮小拡
大が生ずる部分の材料の熱伝達率が高いほど小さくな
る。したがって、シリコンあるいはセラミックにより形
成された基板5においては、比較的熱抵抗は小さい。一
方、マウント材2は、エポキシ系あるいはポリイミド系
の樹脂材料でつくられるため、一般に半導体素子1より
も二桁近く熱伝導率の低い材料が用いられる。このた
め、マウント材2において生ずる熱の流れの縮小の際の
熱抵抗が大きくなる。
By providing the thermal vias 7, the wiring layer 4 can be provided with a place where heat easily passes and a place where heat does not easily pass. Therefore, above and below the wiring layer 4, as shown in FIG. 10, the heat flow contracts and expands, which causes thermal resistance. This thermal resistance becomes smaller as the heat transfer coefficient of the material in the portion where the above-mentioned contraction and expansion of heat occurs becomes higher. Therefore, the substrate 5 made of silicon or ceramic has a relatively small thermal resistance. On the other hand, since the mount material 2 is made of an epoxy-based or polyimide-based resin material, a material having a thermal conductivity that is nearly two orders of magnitude lower than that of the semiconductor element 1 is generally used. Therefore, the thermal resistance when the heat flow generated in the mount material 2 is reduced is increased.

【0012】かかる熱抵抗の低減を図るべく、本発明で
は、サーマルビア7の各端部近傍のダイパッド3上に熱
伝導性の高い材料で形成された熱伝導性部材8を設ける
こととした。図2は、熱伝導性部材8の近傍を拡大した
要部断面図である。図に示すように、熱伝導性部材8を
マウント材2の内部に突出させて設けることにより、半
導体素子1を接合した際、熱伝導性部材8と半導体素子
1との間に介在するマウント材2の厚さを小さくするこ
とができるため、半導体素子1において発生した熱の流
れの縮小が、マウント材2の内部ではなく、半導体素子
1の内部で生ずるようになるため、上記した熱抵抗の低
減を図ることが可能となる。また、上記したような構成
によれば、マウント材2の内部に気泡が発生した場合に
も、その気泡による熱通過への影響を小さくすることが
できる。
In order to reduce the thermal resistance, in the present invention, the thermal conductive member 8 made of a material having high thermal conductivity is provided on the die pad 3 near each end of the thermal via 7. FIG. 2 is an enlarged cross-sectional view of an essential part of the vicinity of the heat conductive member 8. As shown in the figure, the thermally conductive member 8 is provided so as to project inside the mount material 2, so that when the semiconductor element 1 is bonded, the mount material interposed between the thermally conductive member 8 and the semiconductor element 1 is provided. Since the thickness of 2 can be reduced, the reduction of the heat flow generated in the semiconductor element 1 occurs not inside the mount material 2 but inside the semiconductor element 1. It is possible to reduce the amount. Further, according to the above-described configuration, even when bubbles are generated inside the mount material 2, the influence of the bubbles on the heat passage can be reduced.

【0013】図3は、上記した熱伝導性部材の他の実施
例を示したものである。本実施例においては、熱伝導部
8を構成するための熱伝導性部材9を直接サーマルビア
7上に配設し、その上からシート状のダイパッド3が設
けられている。ここで、熱伝導性部材9は、サーマルビ
ア7と一体に形成されても良い。
FIG. 3 shows another embodiment of the above-mentioned heat conductive member. In this embodiment, the heat conductive member 9 for forming the heat conductive portion 8 is arranged directly on the thermal via 7, and the sheet-shaped die pad 3 is provided thereon. Here, the heat conductive member 9 may be formed integrally with the thermal via 7.

【0014】上記した第1実施例においては、熱伝導性
部材は、半導体素子1との間のマウント材2の厚さを小
さくすることができればよく、その形状は特に問わな
い。ただし、熱の流れの縮小による熱抵抗を小さくする
ためには、半導体素子1と対向する熱伝導性部材8の面
が広ければ広いほど良い。しかし、あまり広すぎると、
マウント材2が介在する領域が小さくなり、半導体素子
1の接合に不具合を生ずる場合もある。図4は、熱伝導
性部材の形状に関する他の実施例を示したものである。
本実施例における熱伝導性部材8は、半導体素子1と対
向する面が広く、サーマルビア7側の面が狭い形状を有
する。かかる形状によれば、熱伝導性部材8同士の間に
マウント材2が流入する領域が確保されるため、半導体
素子1と対向する熱伝導性部材8の面が広い場合でも半
導体素子1の接合を十分に行うことが可能となる。
In the first embodiment described above, the heat conductive member may be of any shape as long as it can reduce the thickness of the mount material 2 between the heat conductive member and the semiconductor element 1. However, in order to reduce the thermal resistance due to the reduction of the heat flow, the wider the surface of the heat conductive member 8 facing the semiconductor element 1, the better. However, if it is too wide,
The area where the mount material 2 intervenes becomes small, which may cause a problem in the bonding of the semiconductor element 1. FIG. 4 shows another embodiment relating to the shape of the heat conductive member.
The heat conductive member 8 in this embodiment has a shape in which the surface facing the semiconductor element 1 is wide and the surface on the thermal via 7 side is narrow. With such a shape, a region into which the mount material 2 flows is secured between the heat conductive members 8, so that even if the surface of the heat conductive member 8 facing the semiconductor element 1 is wide, the semiconductor element 1 is bonded. Can be sufficiently performed.

【0015】なお、図示しないが、上記した熱伝導性部
材8のうち少なくとも一つが、半導体素子1及びサーマ
ルビア7の双方と連接されるようにしても良い。この場
合、双方に連接された熱伝導性部材8は、半導体素子1
と熱的に接続されるだけでなく、電気的に接続されても
良い。
Although not shown, at least one of the heat conductive members 8 may be connected to both the semiconductor element 1 and the thermal via 7. In this case, the heat conductive member 8 connected to both sides is the semiconductor element 1
It may be electrically connected as well as thermally connected to.

【0016】図5は、本発明に係る電子部品の第2実施
例を示す要部断面図である。本実施例においては、マウ
ント材2の内部に突出する熱伝導性部材8が半導体素子
1側に設けられている。かかる構成でも、第1実施例と
同様の効果が得られる。
FIG. 5 is a sectional view of the essential parts showing a second embodiment of the electronic component according to the present invention. In this embodiment, the thermally conductive member 8 protruding inside the mount material 2 is provided on the semiconductor element 1 side. With this configuration, the same effect as that of the first embodiment can be obtained.

【0017】図6は、本発明に係る電子部品の第3実施
例を示す要部断面図である。本実施例においては、マウ
ント材2の内部のサーマルビア7近傍に、銅、アルミ
ナ、窒化アルミ等の熱伝導性が高い材料で形成された粒
子状の熱伝導性部材10が設けられている。ここで、熱
伝導性部材10は、半導体素子1あるいはダイパッド3
と接触しても良い。このような構成においても、上記し
た第1及び第2実施例と同様の効果を得ることができ
る。
FIG. 6 is a sectional view of the essential parts showing a third embodiment of the electronic component according to the present invention. In this embodiment, a particulate thermal conductive member 10 made of a material having high thermal conductivity such as copper, alumina, and aluminum nitride is provided near the thermal via 7 inside the mount material 2. Here, the heat conductive member 10 is the semiconductor element 1 or the die pad 3
You may contact with. Even with such a configuration, it is possible to obtain the same effects as those of the first and second embodiments described above.

【0018】図7は、第3実施例にかかる構成を実現す
る方法の一例を示したものである。熱可塑性樹脂11に
粒子状の熱伝導部材10がサーマルビア7のピッチと同
一あるいはその整数分の一のピッチで配置されたシート
を、半導体素子1とダイパッド3との間に挟み込み、熱
を加えることにより接合する。かかる方法によれば、熱
伝導性部材10をサーマルビア7の端部近傍に位置決め
することができる。以上、本発明の実施例について述べ
たが、本発明はこれらの場合に限られず、その要旨を変
更しない範囲で種々変形が可能である。また、実施例で
は、配線層4とマウント材2との間にダイパッド3を設
けているが、かかるダイパッド3は、使用しなくても良
い。
FIG. 7 shows an example of a method for realizing the configuration according to the third embodiment. A sheet in which the particulate heat conducting members 10 are arranged in the thermoplastic resin 11 at the same pitch as the thermal vias 7 or at a pitch that is an integer fraction thereof is sandwiched between the semiconductor element 1 and the die pad 3 and heat is applied. By joining. According to this method, the heat conductive member 10 can be positioned near the end of the thermal via 7. Although the embodiments of the present invention have been described above, the present invention is not limited to these cases, and various modifications can be made without departing from the scope of the invention. Further, in the embodiment, the die pad 3 is provided between the wiring layer 4 and the mount material 2, but the die pad 3 need not be used.

【0019】[0019]

【発明の効果】以上説明したように、本発明によれば、
半導体素子を基板の表面に設けられた配線層上に接合す
る接合部材であるマウント材の内部における熱抵抗を低
減することにより、放熱性能の低下を防止することが可
能な電子部品の提供が可能となる。
As described above, according to the present invention,
By reducing the thermal resistance inside the mount material, which is a joining member that joins the semiconductor element onto the wiring layer provided on the surface of the substrate, it is possible to provide an electronic component that can prevent deterioration of heat dissipation performance. Becomes

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る電子部品の第1実施例を示す要部
断面図。
FIG. 1 is a sectional view of an essential part showing a first embodiment of an electronic component according to the present invention.

【図2】本発明に係る電子部品の熱伝導性部材の近傍を
拡大した要部断面図。
FIG. 2 is an enlarged cross-sectional view of an essential part of the vicinity of the heat conductive member of the electronic component according to the present invention.

【図3】本発明に係る電子部品の熱伝導性部材の他の実
施例を示した要部断面図。
FIG. 3 is a sectional view of an essential part showing another embodiment of the heat conductive member of the electronic component according to the present invention.

【図4】本発明に係る電子部品の熱伝導性部材の形状に
関する他の実施例を示した要部断面図。
FIG. 4 is a cross-sectional view of essential parts showing another embodiment of the shape of the heat conductive member of the electronic component according to the present invention.

【図5】本発明に係る電子部品の第2実施例を示す要部
断面図。
FIG. 5 is a cross-sectional view of essential parts showing a second embodiment of the electronic component according to the present invention.

【図6】本発明に係る電子部品の第3実施例を示す要部
断面図。
FIG. 6 is a cross-sectional view of essential parts showing a third embodiment of the electronic component according to the present invention.

【図7】本発明の第3実施例にかかる構成を実現する方
法の一例を示した図
FIG. 7 is a diagram showing an example of a method for realizing the configuration according to the third exemplary embodiment of the present invention.

【図8】従来の電子部品(マルチチップモジュール)の
一例を示す概略図。
FIG. 8 is a schematic diagram showing an example of a conventional electronic component (multichip module).

【図9】従来の電子部品(マルチチップモジュール)の
一例を示す要部断面図。
FIG. 9 is a main-portion cross-sectional view showing an example of a conventional electronic component (multichip module).

【図10】サーマルビア前後における熱の流れの縮小拡
大に関する説明図。
FIG. 10 is an explanatory diagram related to reduction and expansion of heat flow before and after a thermal via.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 マウント材(接合部材) 3 ダイパッド 4 配線層 5 基板 7 サールビア 8,9,10 熱伝導性部材 11 熱可塑性樹脂 12 放熱フィン 15 キャップ 1 Semiconductor Element 2 Mounting Material (Joining Member) 3 Die Pad 4 Wiring Layer 5 Substrate 7 Sar Via 8, 9, 10 Thermal Conductive Member 11 Thermoplastic Resin 12 Radiating Fin 15 Cap

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板と、この基板上に形成される絶縁体
及び導体からなる配線層と、この配線層を貫通して設け
られる熱伝導性材料からなる柱状部材と、前記配線層上
に接合部材を介して接合される半導体素子とを有してな
る電子部品であって、前記接合部材内部の前記柱状部材
近傍に熱伝導性部材が設けられていることを特徴とする
電子部品。
1. A substrate, a wiring layer made of an insulator and a conductor formed on the substrate, a columnar member made of a heat conductive material and penetrating the wiring layer, and bonded on the wiring layer. An electronic component comprising a semiconductor element bonded via a member, wherein a heat conductive member is provided near the columnar member inside the bonding member.
JP5232643A 1993-09-20 1993-09-20 Electronic part Pending JPH0786469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5232643A JPH0786469A (en) 1993-09-20 1993-09-20 Electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5232643A JPH0786469A (en) 1993-09-20 1993-09-20 Electronic part

Publications (1)

Publication Number Publication Date
JPH0786469A true JPH0786469A (en) 1995-03-31

Family

ID=16942515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5232643A Pending JPH0786469A (en) 1993-09-20 1993-09-20 Electronic part

Country Status (1)

Country Link
JP (1) JPH0786469A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026152A1 (en) * 1999-09-30 2001-04-12 Hitachi, Ltd. Semiconductor device
CN108293293A (en) * 2015-11-30 2018-07-17 日本精工株式会社 Heat-radiating substrate and electric power-assisted steering apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026152A1 (en) * 1999-09-30 2001-04-12 Hitachi, Ltd. Semiconductor device
JP2001102483A (en) * 1999-09-30 2001-04-13 Hitachi Ltd Semiconductor device
CN108293293A (en) * 2015-11-30 2018-07-17 日本精工株式会社 Heat-radiating substrate and electric power-assisted steering apparatus

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