WO2001026152A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2001026152A1
WO2001026152A1 PCT/JP2000/005785 JP0005785W WO0126152A1 WO 2001026152 A1 WO2001026152 A1 WO 2001026152A1 JP 0005785 W JP0005785 W JP 0005785W WO 0126152 A1 WO0126152 A1 WO 0126152A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
heat
semiconductor element
thermal
semiconductor
Prior art date
Application number
PCT/JP2000/005785
Other languages
French (fr)
Japanese (ja)
Inventor
Yasuo Osone
Norio Nakazato
Yasunari Umemoto
Chushiro Kusano
Kiichi Yamashita
Shizuo Kondou
Sakae Kikuchi
Satoshi Sasaki
Mitsuaki Hibino
Masaki Nakanishi
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO2001026152A1 publication Critical patent/WO2001026152A1/en

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Definitions

  • the present invention relates to a semiconductor device used for a high-frequency power amplifier for a mobile communication terminal and the like.
  • the power amplifier itself in addition to the efficiency improvement described above, it is essential that the power amplifier itself be densely mounted and miniaturized.
  • high-density mounting and miniaturization are not necessarily technical issues limited to power amplifiers, the local temperature inside the device is higher than conventional products even if the amount of heat generated can be reduced by consolidating heat generation spots. In some cases, it is necessary to develop a technology for lowering the thermal resistance in accordance with higher densities.
  • a semiconductor element in a high-frequency power amplifier generates heat when transmitting an electric wave through the antenna. Since the efficiency of a high-frequency power amplifier is not 100% and most of the difference between the power consumption and the output power is released as heat, the heat released from the semiconductor element in the power amplifier is generally It is transmitted from the board to the motherboard via the wiring board, and is transmitted from the housing that forms the outer shape of the mobile phone to radiation, heat to the air, or to the outside through the hand of the person holding the mobile phone Designed to let you.
  • This semiconductor device includes a semiconductor element and a wiring board on which the semiconductor element is mounted. W
  • the multilayer wiring board 2 is mounted on the motherboard 8.
  • the semiconductor element 1 is mounted on the multilayer wiring board 2 via a brazing material 9.
  • the semiconductor element 1 includes a semiconductor substrate la and a circuit such as a transistor formed on a surface of the semiconductor substrate 1a. A part of this circuit includes a heating part 1b (for example, a transistor emitter-base region).
  • Reference numeral 3 denotes a columnar member (hereinafter, referred to as a thermal via) penetrating the multilayer wiring board 2 in the thickness direction, and electrically and thermally connects the semiconductor substrate 1a and the motherboard 8 to each other.
  • Reference numeral 5 denotes a wiring element of the multilayer wiring board 2, which is connected to the motherboard 8.
  • a plurality of components 12 such as a chip capacitor and a resistor are mounted on the multilayer wiring board 2 in addition to the semiconductor element 1.
  • a ceramic-based material such as glass-ceramic, glass-epoxy, or alumina having high electrical insulation is used as the material of the multilayer wiring board 2.
  • the materials of the above-mentioned wiring board have the property of having a high electrical insulation property but a low thermal conductivity. Therefore, if these materials are used as they are as the material of the multilayer wiring board 2, the thermal resistance of the entire semiconductor device becomes large. And the temperature of the heat generating portion 1b of the semiconductor element 1 rises above the target upper limit.
  • thermal vias 3 On a multilayer wiring board 2 as shown in the semiconductor device of FIG. There is one that implements 1.
  • the semiconductor element 1 is electrically connected to the common ground electrode on the mother board 8 via the back surface of the multilayer wiring board 2, and at the same time, the semiconductor substrate 1a is connected to the mother board 1a. Since the board 8 can be thermally connected, the thermal resistance between the heating part 1 b of the semiconductor element 1 and the backside of the multilayer wiring board 2 is reduced, and the temperature of the heating part 1 b is lower than a certain reference value. It is possible to use
  • a Si single crystal substrate has conventionally been used as a material of the semiconductor substrate 1a, and a high frequency power amplifier has been formed by forming a MO SFET circuit on the single crystal substrate.
  • the thermal conductivity of this Si-based material is Since it is relatively high, the thermal resistance between the heat generating portion 1b on the element surface and the rear surface of the multilayer wiring board 2 does not become as large as when a GaAs-based compound semiconductor substrate described later is used.
  • Si-based MOS FETs are not enough to improve the efficiency of high-frequency power amplifiers. For this reason, there is a semiconductor substrate formed of a GaAs-based compound semiconductor substrate for the purpose of improving the output of a high-frequency power amplifier and improving the efficiency.
  • this GaAs-based material has a characteristic of low thermal conductivity and high electrical insulation, a through hole called a via hole is formed in a part of the semiconductor substrate 1a, and a back surface of the semiconductor element is formed on the back surface of the semiconductor element.
  • a plating layer such as a gold plating is provided and a specific wiring on the front surface side of the semiconductor substrate 1a is electrically connected to the rear surface of the semiconductor substrate via the via hole.
  • the wiring inductance can be reduced.
  • the plating layer functions as a heat diffusion plate, and the thermal resistance between the heat generating portion 1b on the element surface and the back surface of the multilayer wiring board 2 decreases, resulting in low thermal conductivity. Even with GaAs-based materials, it is possible to reduce the thermal resistance of the entire power amplifier.
  • FIG. 6 shows a semiconductor device in which a heat diffusion plate 13 is interposed between a semiconductor substrate 1 a constituting a semiconductor element 1 and a wiring substrate 2.
  • a semiconductor device having a heat diffusion plate attached thereto for example, there are Japanese Patent Application Laid-Open Nos. 11-191603 and 10-247704.
  • FIG. 7 shows a semiconductor device in which the thermal via 3 penetrating through the wiring board 2 is substantially the same as or larger than the semiconductor substrate 1a and has a single shape.
  • 7 indicates PHS.
  • the PHS 7 is made of a gold plating layer or the like, and transfers heat from the semiconductor element 1 to the thermal via 3.
  • PHS is provided on the back of a semiconductor substrate made of a GaAs-based material with low thermal conductivity, and this PHS is directly fixed to the multilayer wiring board using If the thickness is not extremely large, the thermal resistance from the heating part on the element surface to the multilayer wiring board cannot be reduced as much as the Si-based semiconductor element. However, forming such a thick PHS with gold plating is extremely expensive in terms of cost.
  • the difference in the linear expansion coefficient between G a s and gold may cause thermal stress generated in the reflow process in the manufacturing process, During the heat generation cycle, cracks may occur in the semiconductor substrate 1a or peeling may occur between the semiconductor substrate 1a and the PHS due to thermal stress generated at the interface between the gold plating layer and the semiconductor substrate.
  • a wiring board, a first brazing material, a heat diffusion plate, a second brazing material, and a semiconductor element are mounted in this order from below.
  • the thermal resistance is reduced by reducing the thickness of the semiconductor substrate, the spread of heat to the thermal vias is reduced due to insufficient spread of the three-dimensional heat within the semiconductor substrate. Thermal vias that do not contribute to transmission are generated, making it impossible to use thermal vias effectively. For this reason, the thermal resistance in the multilayer wiring board cannot be sufficiently reduced, and the thermal resistance of the entire device may not always be small.
  • the thickness of the semiconductor substrate is increased, the thicker the substrate is, the more the heat is diffused and the thermal vias can be effectively used without waste. There are problems that it becomes difficult and that the cost cannot be compromised. Also, since the thermal resistance in the semiconductor substrate increases as the thickness increases, the thermal resistance of the entire device does not necessarily decrease.
  • the base material of the multilayer wiring board is a highly insulating glass-ceramic or glass epoxy material means that the multilayer wiring board is essentially a heat insulating layer. There will be no part to escape.
  • a single thermal via 3 having a cross-sectional area that is equal to or larger than the cross-sectional area of the semiconductor substrate 1a, sufficient thermal resistance can be obtained. However, if a single large thermal via is formed, nests will be formed inside the thermal via, and as a result, the thermal resistance will likely increase.
  • the thermal via 3 when forming a device by press-fitting a thermal via 3 made of a plate-like member with a through hole provided in the multilayer wiring board 2, even if a material having no problem in terms of thermal resistance is selected, the thermal via If the coefficient of linear expansion of 3 and the multilayer wiring board 2 are not matched within a certain error range, the element may be broken by thermal stress during heat generation. If the dimensions of the thermal vias 3 are made considerably smaller than the through-holes of the multilayer wiring board 2 in order to avoid this problem, it will be necessary to consider a different method of fixing the thermal vias 3 and this will contribute to an increase in cost. I will.
  • An object of the present invention is to provide a low-cost semiconductor device capable of efficiently transmitting heat from a semiconductor element to the outside from a multilayer wiring board without increasing the thickness of the semiconductor substrate.
  • the object is to provide a semiconductor element mounted on a wiring board, a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction, and the semiconductor element. And a second heat conductive member for thermally connecting the first heat conductive member and the first heat conductive member.
  • a semiconductor element mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction; This is achieved by providing a heat diffusion plate provided between a member and the semiconductor element, and a second heat conduction member for thermally connecting the heat diffusion plate and the first heat conduction member.
  • the semiconductor element is a single crystal semiconductor substrate such as Si or a compound semiconductor substrate such as GaAs, and a multi-finger element including a plurality of transistors or diodes is formed. It is achieved by doing.
  • the second heat conductive member disposed between the semiconductor element and the wiring board is achieved by using a material having higher thermal conductivity than the semiconductor element.
  • both the second heat conductive member disposed between the semiconductor element and the wiring board, and the heat diffusion plate disposed between the semiconductor element and the second heat conductive member are the same as those of the semiconductor device. This is achieved by using a material having higher thermal conductivity than the element.
  • the thickness of the semiconductor element, the second heat conductive member, and the heat diffusion plate is achieved by the thinnest heat diffusion plate and the thickest second heat conductive member.
  • FIG. 1 is a sectional view of a semiconductor device having a basic embodiment according to the present invention.
  • FIG. 2 is a cross-sectional view of a semiconductor device having a thermal via that does not penetrate a wiring board according to the present invention.
  • FIG. 3 is a cross-sectional view of a semiconductor device having PHS according to the present invention.
  • FIG. 4 is a cross-sectional view of a semiconductor device provided with a heat conducting member between PHS and a thermal via according to the present invention.
  • FIG. 5 is a cross-sectional view illustrating an example of a conventional semiconductor device.
  • FIG. 6 is a cross-sectional view illustrating an example of a conventional semiconductor device.
  • FIG. 7 is a cross-sectional view illustrating an example of a conventional semiconductor device.
  • FIG. 8 is a cross-sectional view of a semiconductor device according to the present invention in which a plurality of types of semiconductor elements are mixedly mounted on one wiring board.
  • FIG. 9 is a perspective view of a part of a semiconductor device to which the present invention is applied.
  • FIG. 10 is a diagram showing a top surface and a bottom surface of a semiconductor device according to the present invention in which a plurality of types of semiconductor elements are mixedly mounted on one wiring board.
  • FIG. 11 is a diagram showing an example of a process step in which a semiconductor element according to the present invention is mounted on a wiring board.
  • FIG. 12 is a cross-sectional view of a semiconductor device showing the vicinity of a typical emitter electrode when the semiconductor element in the present invention is an HBT element.
  • FIG. 13 is a simulated top view showing an example of the arrangement of heat generating regions according to the present invention.
  • FIG. 14 is a graph showing the effect of the thickness of the heat conductive member on the module thermal resistance in the present invention.
  • FIG. 15 is a graph showing the effect of the area of the heat conducting member on the module thermal resistance in the present invention.
  • FIG. 16 is a graph showing the effect of the thickness of PHS on the thermal resistance of the module when no heat conducting member is used in the present invention.
  • FIG. 17 is a graph showing the effect of the thickness of the heat conducting member on module thermal resistance in the absence of PHS in the present invention.
  • FIG. 18 is a graph showing the effect of the type of heat conducting member on the module thermal resistance in the present invention.
  • FIG. 1 is a sectional view of a semiconductor device provided with the present invention
  • FIG. 2 is a sectional view of a semiconductor device provided with a thermal via which does not penetrate a multilayer wiring board of the present invention.
  • a semiconductor substrate 1 a constituting a semiconductor element 1 is mounted on a wiring board 2. Inside the wiring board 2, a plurality of thermal vias 3 having conductivity and high thermal conductivity are provided so as to penetrate the wiring board 2. A heat conductive member 4 is interposed between each of the thermal vias 3 and the semiconductor substrate 1a, and is electrically and thermally connected.
  • the wiring board 2 is made of a glass-ceramic-based glass epoxy material having a high insulation property and a low thermal conductivity, the portions other than the thermal vias 3 are close to heat insulation, and are electrically and electrically connected within the wiring board 2. Only thermal via 3 has good thermal conductivity. For this reason, as many thermal vias 3 as possible are thermally connected to the semiconductor substrate 1 by using the heat conductive member 4 so that the heat generating portion 1 b on the surface of the semiconductor substrate 1 a and the wiring substrate 2 are connected. It is possible to reduce the thermal resistance between the back surface.
  • the semiconductor substrate 1a is made as thin as possible (about ⁇ ⁇ ⁇ or less, typically about 30 to 50 ⁇ ) in order to reduce the thermal resistance of this portion.
  • the thermally conductive member 4 is used to thermally and effectively connect the locally high temperature range and the thermal via 3 on the back surface of the conductive board 1a, thereby providing a heat transfer portion between the back surface of the wiring board 2 and the heat generating portion 1b. Thermal resistance can be reduced.
  • the space between the semiconductor substrate 1a where the heat conducting member 4 is located and the wiring board 2 can be sealed by using an insulating member without any problem. May be implemented.
  • the wiring element 5 on the back surface of the wiring board 2 is electrically connected to the thermal via 3, and is connected to the common ground wiring on the mother board 8 via the wiring element 5. By the way, the wiring element 5 does not need to cover the entire back surface of the wiring board 2. This point is common to all embodiments of the present invention described below.
  • FIG. 1 shows an example in which the thermal vias 3 are evenly arranged.
  • the number of thermal vias 3 and their intervals are not limited to the example shown in FIG.
  • the wiring board 2 when the wiring board 2 is a multilayer wiring board, if a wiring element 5 having high conductivity and high thermal conductivity is interposed between the layers, the wiring board 2 may not penetrate the wiring board 2 in the thickness direction. Alternatively, there is no problem even if there is a thermal via 6 that does not directly contact the heat conduction member 4. It is desirable that as many thermal vias 3 or 6 as possible are thermally connected to the semiconductor substrate 1a, and the thermal vias 6, which cannot be directly connected to the semiconductor substrate 1a due to the heat conducting member 4, are located between the layers. Element 5 makes it possible to effectively utilize the heat, and further reduces the thermal resistance.
  • Circuit elements 12 other than the semiconductor element 1 are mounted on the multilayer wiring board 2.
  • the circuit elements 12 and the independent wiring provided on the back surface of the multilayer wiring board 2 may be electrically connected to each other using through holes independent of the thermal via 3. It is important that the cross-sectional area of each heat conductive member 4 keeps a temperature difference generated when heat is transferred to the thermal via 3 connected to each heat conductive member 4 constant.
  • the thermal resistance can be adjusted by increasing the cross-sectional area of the heat conductive member 4 having the longest distance from 1 a to the thermal via 3.
  • FIG. 3 is a sectional view of a semiconductor device having another embodiment of the present invention.
  • a PHS 7 made of a plating layer such as gold is provided between a semiconductor substrate 1 a and a heat conducting member 4. If the semiconductor substrate 1a is not thick, The heat generated from the plurality of heat generating portions 1b located on the surface of the substrate 1a does not sufficiently diffuse inside the semiconductor element 1, and the temperature distribution on the back surface of the semiconductor element 1 is not uniform. For example, the temperature immediately below each heat generating portion 1b may be high, and the temperature between the portions may be low. Variations in the temperature distribution of a material that has no spatial distribution of thermal conductivity are equivalent to a distribution of the heat flux through that material. For this reason, the amount of heat transmitted to the thermal vias 3 through the individual heat conducting members 4 is not uniform, and some thermal vias 3 may not function effectively. Therefore, it is desirable that the temperature distribution on the back surface of the semiconductor substrate 1a be as uniform as possible.
  • Fig. 3 shows that PHS 7 is provided between the semiconductor substrate 1a and the heat conductive member 4 in order to equalize the amount of heat transmitted to the individual thermal vias 3 through the heat conductive member 4. is there.
  • the temperature distribution on the back surface of the PHS 7 is close to a concentric circle with the lowest temperature at the outer periphery and the highest temperature at the center.
  • the influence of the distribution of the plurality of heating regions 1b on one surface side can be offset. This is because the positive effect that heat is uniformly diffused by the PHS 7 is greater than the negative effect that the thermal resistance increases by the thickness of the PHS 7, and thus the thermal resistance can be reduced. Further, it is possible to almost no need to adjust the placement of the parts in contact with the semiconductor substrate 1 a heat conducting member 4 according to the arrangement of the heat generating portion 1 b.
  • FIG. 4 is a cross-sectional view of a semiconductor device having another embodiment of the present invention.
  • a PHS 7 having a cross-sectional area substantially equal to or larger than that of the semiconductor substrate 1a is provided on the back surface of the semiconductor substrate 1a.
  • a heat conducting member 10 is interposed between the PHS 7 and the multilayer wiring board 2.
  • a brazing material is provided on the upper and lower surfaces of the heat conducting member 10, a first filler material 9 is provided on the multilayer wiring board 2 side, and a second brazing material 11 is provided on the PHS side.
  • the multilayer wiring board 2 is provided with a thermal via 3 having high conductivity and high thermal conductivity so as to penetrate the multilayer wiring board 2.
  • the area of the thermal via 3 arranged in the multilayer wiring board 2 is equal to the area of the semiconductor element 1. If it is wider, the area of the heat conductive member 10 needs to be larger than the area of the semiconductor substrate 1a, and if possible, it is desirable to have an area that covers all the thermal vias 3.
  • PHS 7 it is possible to make the temperature distribution on the back surface of PHS 7, that is, the surface facing the heat conducting member 10 uniform, and to reduce the thermal resistance from the semiconductor element 1 to the heat conducting member 10. Can be. Further, by forming the heat conducting member 10 as a single plate-shaped member, the heat generating portion of the semiconductor element 1 can be manufactured at a lower cost as compared with the other embodiments of the present invention shown in FIGS. The heat generated in 1 b can be efficiently transmitted to the high-conductivity and high-thermal-conductivity thermal vias 3 arranged on the multilayer wiring board 2. Therefore, the thermal resistance between the heat conductive member 10 and the back surface of the wiring board 2 can be reduced, and a low cost and low heat resistance structure can be realized by combining the PHS 7 with the heat conductive member 10 and the thermal via 3. Can be.
  • the thickness of the heat conductive member 10 be larger than the thickness of the semiconductor substrate 1a and smaller than or equal to the thickness of the portion of the wiring substrate 2 through which the thermal via penetrates.
  • the thickness of the semiconductor substrate 1a and the thickness of the PHS 7 it is preferable that the thickness of the PHS 7 is thinner. That is, assuming that the thicknesses of the portions of the semiconductor substrate la, the PHS 7, the thermal conductive member 10, and the thermal via 3 of the wiring board 2 that penetrate are t1, t2, t3, and t4, respectively, In semiconductor devices,
  • t 1 30 to 50, up to about 100 m
  • ⁇ 4 about 300 to 450 ⁇ m
  • the present invention is not necessarily limited to the above range as long as the above relational expression is satisfied. If the thicknesses of the first and second brazing materials and the thermal vias are respectively t5, t6, and t7, the thicknesses are adjusted so that the following relationship is satisfied.
  • the thermal conductivity of the semiconductor substrate 1a, the PHS 7, the thermal conductive member 10, the base material of the wiring board 2, the first brazing material 9, the second brazing material 11, and the thermal conductivity of the thermal via 3 are respectively: , ⁇ 2, ⁇ 3, 44, 55, ⁇ 6, ⁇ 7, and the linear expansion coefficients are ⁇ 1, ⁇ 2, ⁇ 3, ⁇ 4, HI5, ⁇ 6, ⁇ 7, respectively.
  • the materials so that the following relationship is established.
  • the symbol means that the physical property values are almost the same order, and it means that the magnitude relation is not necessarily particular.
  • the base material of the wiring board 2 the various types of the opening material, the semiconductor substrate 1 a, and the various thermal conductive and heat diffusing members are arranged so that the thermal resistance increases in this order.
  • the semiconductor substrate 1a has a thermal conductivity equal to or higher than that of Si (at a temperature of 373K (100 ° C); about I1 ⁇ 100 [WZ (m ⁇ K)] or more)
  • ⁇ 5 ?, 6 ⁇ ⁇ ⁇
  • the coefficient of linear expansion of the second brazing material is the lowest, the semiconductor substrate 1a is comparable or higher, and the PHS 7 is very high.
  • the members below the second brazing material the base material of the wiring board 2 and the thermal vias 3 are almost equal, and the coefficient of thermal expansion of the heat conductive member 10 is high.
  • the material of the semiconductor substrate 1a may be a Si-based single crystal or a semiconductor substrate made of a GaAs-based compound or the like.
  • the material of the heat conducting member 10 may be a metal such as copper, aluminum, or molybdenum, or an alloy containing these as a main component. The material need not be.
  • the first brazing material 9 is desirably a material such as solder
  • the second brazing material 11 is a conductive silver paste material or the like, having conductivity, and having substantially the same thermal conductivity as the semiconductor substrate 1a. It is desirable that the material be a thermosetting material of a certain degree.
  • the melting point of the first brazing material 9 is higher than the curing temperature in the manufacturing process of the second brazing material 11, and the semiconductor element 1 is placed on the second brazing material 11 via the PHS 7.
  • Fix In this case, a material having physical properties such that the first brazing material 9 is not melted when the material is used is selected.
  • the base material of the paste is a thermosetting resin. The thermal stress generated at the interface between the heat conductive member 10 and the second brazing material 11 or the interface between the PHS 7 and the second brazing material generated during the manufacturing process can be reduced. The thermal stress at the interface between the PHS 7 and the semiconductor substrate 1a, which is generated by the heat generation operation after the second brazing material is cured, is relaxed by sufficiently thinning the PHS 7 by yielding and deforming the gold plating layer. can do.
  • FIG. 5 shows an embodiment in which the semiconductor substrate 1 a and the thermal via 3 are connected via the brazing material 9.
  • FIG. 6 shows an embodiment in which the semiconductor substrate 1 a and the wiring substrate 2 are connected via the heat diffusion plate 13.
  • FIG. 7 shows an embodiment in which the thermal via 3 has a size equal to or larger than the size of the semiconductor substrate 1a and is formed as an integrated product.
  • FIG. 8 is a sectional view of a semiconductor device provided with the present invention.
  • FIG. 9 is a perspective view of a part cut out
  • FIG. 10 is a top view (FIG. 10a) and a bottom view (FIG. 10b) of the wiring board 2 and a cross-sectional view including the semiconductor element 1 (FIG. 19c). It is.
  • the semiconductor device to which the present invention shown in FIG. 8 is applied has a plurality of types of semiconductor elements 16 and 17 mounted on a single wiring board 2.
  • the semiconductor element 16 has a heat generating portion 16b formed on a semiconductor substrate 16a having a relatively low thermal conductivity, such as a GaAs system, and has a relatively thin semiconductor substrate 16a on the back surface.
  • PHS 7 is formed by plating.
  • a heat generating portion 17 b is formed on a semiconductor substrate 17 a having a relatively high thermal conductivity such as an Si-based material.
  • the thickness of the semiconductor element 17a is reduced to about several ⁇ ⁇ ⁇ to make the semiconductor substrate 17a. Since the temperature distribution on the 17a back surface can be made substantially uniform, the target value of the thermal resistance may be achieved without using the PHS 7 or the heat conducting member 10 described above. In such a case, as shown in FIG. 8A, the semiconductor substrate 17 can be directly mounted on the wiring board 2 via the second brazing material 11 via the second brazing material 11, so that the cost is low. Can be reduced.
  • wiring elements 101 and circuit components 12 such as resistors and chip capacitors are mounted on the surface layer 2a of the multilayer wiring board.
  • the wiring element 101 or the circuit component 12 and the semiconductor elements 16 and 17 are electrically connected by, for example, a bonding wire 18.
  • the combination of the wiring elements and through holes in each layer of the multilayer wiring board 2 and the semiconductor elements 16 and 17 operates, for example, as a high-frequency power amplifier for a mobile communication terminal.
  • One semiconductor device hereinafter, referred to as a module
  • the GND of the semiconductor elements 16 and 17 is connected to the mother via the PHS 7, the heat conductive member 10, the thermal via 3, and the GND wiring layer 5 formed on the back surface 2b of the multilayer wiring board. It is electrically and thermally connected to the GND wiring layer 102 on the board 8.
  • Electrodes 103 for input / output signals are also formed on the back surface 2b of the multilayer wiring board, and the electrodes 103 and the wiring elements 101 on the surface layer 2a of the multilayer wiring board or between layers, and the circuit elements 1
  • the wiring 2 is electrically connected to the wiring board 2 by a wiring 104 formed as a through hole on the side surface or inside.
  • Wiring layers 105 corresponding to the electrodes 103 are formed on the motherboard 8, respectively, and the electrodes 103 and the wiring layers 105 are electrically connected.
  • a third brazing material 106 such as low-melting solder is used for connection between the wiring layers 5 and the electrodes 103 and the wiring layers 102 and 105.
  • the first brazing material 9 is a solder
  • the second brazing material is a thermosetting conductive paste material
  • the third brazing material is a solder.
  • the heat conductive member 10 and the semiconductor device 17 are mounted on the surface 2a of the multilayer wiring board, and then the semiconductor device 16 is mounted on the heat conductive member 10 to obtain a multilayer wiring board in the completed module. Considering the process of mounting back side 2 on motherboard 8
  • the heat generation amount of the heat generating portion 17b formed on the semiconductor substrate 17a is sufficiently small, and the semiconductor substrate 17a is made of a material having a high thermal conductivity such as Si.
  • the thermal resistance can be reduced to the target upper limit or less even without the PHS 7 or the heat conducting member 10. In such a case, there is no need to use the PHS 7 or the heat conducting member 10. Therefore, when a plurality of chips are mounted on one multilayer wiring board 2, it is necessary to select an optimal configuration thermally and cost-effectively from the physical property values and heat generation values of the semiconductor substrate constituting the chip. Can be. Assuming that the thickness of the semiconductor element 16 is t1 as it is, the thickness of 17 is t9, and the thickness of the circuit component 12 excluding the chip resistor formed by the microstrip line is t8, ,
  • the semiconductor element 16 or 17 may be configured to form a common circuit or may not be short-circuited. There is no particular problem as long as the functions of the entire device can be secured.
  • FIG. 8B shows a case where the semiconductor element 17 is mounted face-down (flip-chip mounting).
  • input / output signals to / from the semiconductor element 17 are supplied to the semiconductor element 17 via the through-holes 110 in the multilayer wiring board 2 and the wiring layer 111, or are output from the semiconductor element 17 .
  • a CCB connection is made between the circuit network on the surface layer of the semiconductor element and the multilayer wiring board 2 via solder bumps 112 and the like.
  • the GND of each heating element 17b is directly connected to the thermal via 3 via the solder bumps 112. That is, the solder bumps 112 serve as the heat conducting member 4 in the embodiment of the present invention in FIG. Therefore, the heat released from the heating element 17b is effectively transmitted to the thermal via 3, and the thermal resistance from the heating element 17b to the rear surface 2b of the multilayer wiring board can be reduced.
  • the wiring layers 5 and the electrodes 103 formed on the back surface 2 of the multilayer wiring board are solid wirings, respectively.
  • the third brazing material 106 is used to join the wiring layers 102 and 105 formed on the upper surface 8 with a third brazing material 106.
  • One embodiment of the present invention also includes a case where the members 113 are arranged in a grid and joined to the motherboard 8, that is, mounted by so-called BGA joining.
  • Figure 8c shows the above implementation
  • FIG. 4 is a cross-sectional view showing a case where the semiconductor device 17 is flip-chip mounted.
  • FIG. 9 is a perspective view in which a part of a semiconductor device to which the present invention is applied is cut out.
  • the mother board 8 is used.
  • the electrode 103 on the back is an independent electrode, and the electrode 108 is short-circuited with the thermal via 3.
  • the roles should be shared.
  • FIG. 10 is a top view (FIG. 10a) of the semiconductor device used in the embodiment of the present invention shown in FIG. 4 or FIG. 8a and FIG. 9 with the cap 107 removed
  • FIG. A cross-sectional view (FIG. 10b) passing through FIG. 10 is a bottom view (FIG. 10c) of the rear surface 2 of the multilayer wiring board viewed from below.
  • the circuit is formed only on a part of the surface layer 2a of the multilayer wiring board. However, even if the circuit is formed by effectively using the entire surface, the essence of the present invention is not spoiled.
  • FIG. 10b shows an example of a wiring pattern on the back surface 2b of the multilayer wiring board.
  • the GND wiring layer 5 directly connected to the thermal via 3 is a solid wiring, or a solder ball grid array ( (BGA) form of course.
  • BGA solder ball grid array
  • Each of the independent electrodes 103 constitutes a signal input / output electrode or the like.
  • the space inside the cap 107 may be filled with a protection member 109 such as resin.
  • FIG. 11 shows an example of a module manufacturing process of the semiconductor device according to the embodiment of the present invention shown in FIG. 4 or FIG.
  • high melting point solder is printed or applied as a first brazing material 9 at a predetermined position on the wiring board 2.
  • components 12 such as a chip capacitor and a resistor and a heat conductive member 10 are mounted on the position where the first brazing material 9 is printed or applied first, The components 12 and the heat conducting member 10 are mounted in the opening of the riff and in the cleaning step.
  • a second brazing material 11 such as a conductive silver paste is applied to a predetermined position, and a semiconductor element 1 or 16 having a PHS 7 or a semiconductor element 1 or 17 having no PHS structure 7 is formed.
  • the second brazing material 11 is baked and washed at a temperature lower than the melting point of the first brazing material 9 and at a temperature high enough to harden the second brazing material 11. Further, the semiconductor element 1 or 16 or 17 and the predetermined position of the wiring board 2 are connected by wiring 18 by wire bonding or the like, and a member 109 for protecting the semiconductor element is applied and fixed, and then the cap 1 is formed. 0 Add 7 Further, the wiring board 2 is divided for each unit semiconductor device, and a semiconductor device that has passed the inspection process is defined as a completed product. In this step, the first brazing material 9, the second brazing material 11, and the member 109 for protecting the semiconductor element are made of a material whose melting point or curing temperature gradually decreases in the order of the steps.
  • the mounting of the module on the mother board 8 may be performed in the following manufacturing process, or may be shipped to the customer in the state of the module and mounted on the customer side.
  • the magnitude relationship between the melting point of the third brazing material 106 in FIG. 8 and the melting point or the curing temperature of the other brazing material and the protective member must be as described above.
  • the value of T3 may be designated in advance, or conversely, other appropriate values for T1 and T2 may be selected according to T3.
  • Fig. 12 is a schematic cross-sectional view of the vicinity of the heating part 1b when the semiconductor substrate 1 or 16 is a GaAs-based substrate 21 and a hetero bipolar transistor (hereinafter, HBT) is formed on it. Show.
  • HBT hetero bipolar transistor
  • a semi-insulating GaAs substrate 21 is mounted on a heat conducting member 10 via a second port material 11 and a PHS 7.
  • sub-collector layer 22, collector layer 23, base layer 24, emitter layer 25, base electrode 26, cap layer 27, emitter electrode 28, collector electrode 29, interlayer insulating films 30 and 31 and emitter wiring layer 32 are formed.
  • a through hole called a via hole 33 is formed at a predetermined position of the GaAs substrate 21, and the PHS structure 7 and the emitter wiring layer 32 on the back surface of the GaAs substrate 21 are connected to the via hole 33.
  • 33 Electrically connected via PHS 7 flowing into 3.
  • a resistor 34 called a ballast resistor is arranged in a part of the wiring between the emitter wiring layer 32 and the via hole 33. May be.
  • the heat generating portions 1b or 16b and 17b shown in FIG. 4 or FIG. 8 are regions in which current flows intensively between the individual bases 24 and 25 in FIG. .
  • a structure in which there is only one heat-generating region is shown, but there may actually be a plurality of heat-generating regions.
  • the number of heating regions and the number of via holes 33 do not have to match. Generally, the number of via holes 33 is smaller than the number of heat generating regions.
  • the emitter wiring 32 is electrically connected to the PHS 7 via the via hole 33 and further to the back surface of the thermal via 3 in the wiring board 2.
  • the wiring board 2 is further mounted on the motherboard.At this time, the wiring electrically connected to the emitter wiring in the wiring board 2, for example, the back wiring 5 in FIG. 10 is connected to the common GND of the motherboard. By grounding, the potential can be kept constant.
  • the heat generation region (finger) 19 has a width of 2 ⁇ , a length of 20 ⁇ , and a number of 1 in the GaAs-based HBT element 1 or 16 as shown in FIG.
  • the dimensions of the semiconductor substrate 1 or 16 and the PHS 7 are squares each having a side length of 0.9 mm or 1.0 mm, and the dimensions of the heat conductive member 10 are each a side length of 1.4. mm or 1.3 mm square, or 2.4 mm long, horizontal:! It is assumed that each of the thermal vias 3 in the wiring board 2 has a diameter of 0.15 mm and is arranged at an equal pitch of 0.35 mm in the vertical and horizontal directions. For the thickness, material, dimensions, etc. of the heat conducting member 10 to be studied in the future from Fig. 14 onwards, the results when optimization is performed based on Figs. 4, 12, 13 and the above criteria are shown.
  • the size and number of the fingers 19 strongly affect the absolute value of the thermal resistance between the heat generating region 1b and the rear surface 2b of the wiring board. It has been clarified by heat conduction analysis that it does not significantly affect the optimization of the thermal resistance.
  • the effect of reducing the thermal resistance by the combination of the heat conductive member 10 and the wiring board 2 having the thermal vias 3 and the PHS structure 7 For the qualitative evaluation of the above, it is almost enough to consider the dimensions and arrangement of the heat generating area in one case.
  • the material of the heat conductive member 10 is copper
  • the PHS structure 7 is a gold plated layer.
  • PHS structure 7 The thickness was 15 ⁇ unless otherwise specified, and the thermal conductivity of the first brazing material 9 and the second brazing material 11 were the same, and the thickness was 3 ⁇ ⁇ ⁇ ⁇ ⁇ , respectively. The results are shown.
  • Figure 14 shows the thickness of the heat-conducting member 10 and the overall device obtained by using steady-state heat conduction analysis for the case where the GaAs substrate 21 or the SiAs system was used instead of the GaAs system. (Module) Indicates the relationship with the thermal resistance.
  • the horizontal axis represents the thickness of the heat conducting member 10 and the vertical axis represents the module thermal resistance.
  • the optimal value of the thickness of the member 10 is about 300 ⁇ within the range of consideration.
  • the reason for using the Si substrate to have a smaller module thermal resistance is that the thermal conductivity of Si is higher than the thermal conductivity of GaAs.
  • the use of G a As -HBT is for the above-mentioned high-frequency device power amplifier in order to improve the output and the high rate, and is separate from the problem of thermal resistance.
  • Figure 15 shows the steady-state heat conduction to determine how much the module thermal resistance changes due to the combination of the dimensions of the GaAs substrate 21 or semiconductor element 1 or 16 and the PHS structure 7 and the dimensions of the heat conducting member. The results examined by analysis are shown.
  • the horizontal axis of the figure is the thickness of the heat conducting member 10 and the vertical axis is the module thermal resistance. From this figure, it can be seen that the size of the semiconductor element 16 has little or no effect on the thermal resistance, and the size of the heat conductive member 10 is large and affects the module thermal resistance. This is because when the thermal via 3 in the wiring board 2 is arranged in a wider area than the area of the semiconductor element 16, the area of the heat conductive member 10 is made larger than that of the semiconductor element 16, and the semiconductor element 16 This shows that the thermal resistance of the entire module can be reduced by adopting a structure that allows the heat generated in the heat generating area 8 to escape to the thermal via 3 not directly below.
  • the thickness of the heat conducting member 10 is at least about 100 ⁇ and about 300 / m, and its area is larger than that of the semiconductor element 16. By setting the dimensions so as to extend over as many thermal vias 3 as possible, the module thermal resistance can be reduced. Also in the present invention, the heat conducting member 10 has the above-described structure. It is desirable to make it.
  • Figure 16 shows the thickness and module heat of the PHS structure 7 when the semiconductor element 1 or 16 is directly mounted on the wiring board 2 using the second brazing material 11 without the heat conducting member 10 The result of examining the relationship of resistance by steady heat conduction analysis is shown.
  • the horizontal axis is the thickness of the PHS structure 7, and the vertical axis is the module thermal resistance.
  • the thickness of the PHS structure 7 must be 50 to 60 ⁇ or more to achieve almost the same reduction in thermal resistance without using the heat conducting member 10. I understand. It is difficult to make a thick gold plating film as described above, both in terms of process and cost. However, if conditions permit, the above structure may be used.
  • Figure 17 shows the results of examining the results when trying to reduce the thermal resistance by the effect of only the heat conducting member 10 without the PHS structure 7.
  • the horizontal axis represents the thickness of the heat conducting member 10 and the vertical axis represents the module thermal resistance.
  • the optimum value of the thickness of the heat conducting member 10 is about 300 ⁇ m, as in Figs. 12 and 13, but when the GaAs substrate 21 is used, the heat It turns out that the resistance is not small enough. Therefore, the PHS structure 7 is essential for the GaAs substrate 21.
  • the module thermal resistance hardly changes with or without the PHS structure 7. Therefore, as in the embodiment of the present invention shown in FIGS. 8 and 11, there is no particular problem even without the PHS structure 7 for the Si-based control IC.
  • a substrate 21 having a thermal conductivity of about 50 W / (mK) or less such as a GaAs substrate
  • a PHS structure 7 is provided, and a Si substrate is provided.
  • a configuration without the PHS structure 7 may be employed.
  • the thermal conductivity of the substrate 21 is about 50 to about 148, whether or not to use the PHS 7 and the heat conductive member 10 can be selected according to the thickness and the calorific value.
  • FIG. 18 shows the results of an examination of the relationship between the module thermal resistance and the thickness of the heat conducting member 10 when the material of the heat conducting member 10 is changed from copper to aluminum or molybdenum.
  • aluminum and molybdenum have lower thermal conductivity than copper, so they cannot achieve the same thermal resistance reduction effect as copper.
  • the thickness has an optimum value in the range of about 200 to 300 ⁇ , and a slight thermal resistance reduction effect can be obtained.
  • a semiconductor device capable of efficiently transmitting heat from a semiconductor element to the outside from a multilayer wiring board without increasing the thickness of a semiconductor substrate can be provided at low cost.

Abstract

A semiconductor device comprises a semiconductor element (1) mounted on a wiring substrate (2), cylindrical conductors (3) extending through the wiring substrate (2) between the two opposite sides, and a thermal conductor (10) for thermal and electrical connection between the semiconductor element (1) and cylindrical conductors (3). Since the semiconductor element (1) and the cylindrical conductors (3) in the wiring substrate (2) are effectively connected thermally and electrically, thermal resistance decreases.

Description

明 細 書 半導体装置 技術分野  Description Semiconductor device technology
本発明は、 携帯通信端末用高周波パワーアンプ等に用いられる半導体装置に関 するものである。  The present invention relates to a semiconductor device used for a high-frequency power amplifier for a mobile communication terminal and the like.
背景技術 Background art
携帯通信端末、 例えば携帯電話機は、 近年小型 ·軽量化が急ピッチで進行中で あり、 これと並行して低コスト化が重要な課題である。 この小型 ·軽量 ·低コス トの 3条件を実現する上で、 高周波パワーアンプの効率 （消費電力に対する出力 電力の比率） 改善が必須である。 高周波パワーアンプの効率は、 通話時の消費電 力にほぼ比例するため， 同じ連続通話時間を基準に考えると、 高効率、 即ち消費 電力の少ない高周波パワーアンプを用いることにより， その分だけ電池の容量を 低減することができ、 軽量化が可能である。  In recent years, miniaturization and weight reduction of mobile communication terminals, for example, mobile phones, are progressing at a rapid pace, and at the same time, cost reduction is an important issue. In order to achieve these three conditions: small size, light weight, and low cost, it is essential to improve the efficiency of the high-frequency power amplifier (the ratio of output power to power consumption). Since the efficiency of a high-frequency power amplifier is almost proportional to the power consumption during a call, when using the same continuous talk time as a reference, the use of a high-efficiency, low-power-consumption high-frequency power amplifier reduces the battery power by that much. The capacity can be reduced, and the weight can be reduced.
一方、 パワーアンプ自体の低コスト化の観点からは、 上記のような効率改善の 他に、 パワーアンプそのものの高密度実装化、 小型化が必須である。 この高密度 実装化、 小型化は必ずしもパワーアンプに限った技術的課題ではないが、 発熱ス ポッ卜の集約化により、 発熱量が低減できても装置内部の局所的な温度は従来品 より高くなつてしまう場合があり、 高密度化に合わせた低熱抵抗化技術の開発が 必要とされている。  On the other hand, from the viewpoint of reducing the cost of the power amplifier itself, in addition to the efficiency improvement described above, it is essential that the power amplifier itself be densely mounted and miniaturized. Although high-density mounting and miniaturization are not necessarily technical issues limited to power amplifiers, the local temperature inside the device is higher than conventional products even if the amount of heat generated can be reduced by consolidating heat generation spots. In some cases, it is necessary to develop a technology for lowering the thermal resistance in accordance with higher densities.
さて、 携帯電話のように、 アンテナを有する通信機器は、 アンテナを介して電 波の送信を行った時に高周波パワーアンプ内の半導体素子が発熱する。 高周波パ ヮーアンプの効率は 1 0 0 %ではなく、 消費電力と出力電力との差の大半が熱と なって放出するので、 一般的に、 パワーアンプ内の半導体素子から放出された熱 は、 半導体基板から配線基板を経由してマザ一ボードに伝達されて、 携帯電話の 外形を形成する筐体から、 輻射、 空気への熱伝達、 あるいは携帯電話を握った人 の手を伝わって外部に伝達させるように設計されている。 この半導体装置は、 半 導体素子と、 この半導体素子を搭載する配線基板とから構成されており、 この配 W By the way, in a communication device having an antenna, such as a mobile phone, a semiconductor element in a high-frequency power amplifier generates heat when transmitting an electric wave through the antenna. Since the efficiency of a high-frequency power amplifier is not 100% and most of the difference between the power consumption and the output power is released as heat, the heat released from the semiconductor element in the power amplifier is generally It is transmitted from the board to the motherboard via the wiring board, and is transmitted from the housing that forms the outer shape of the mobile phone to radiation, heat to the air, or to the outside through the hand of the person holding the mobile phone Designed to let you. This semiconductor device includes a semiconductor element and a wiring board on which the semiconductor element is mounted. W
2 線基板を半導体素子から生じた熱が通過する。 従って、 配線基板は、 熱伝導率が 高いほど半導体素子の温度を一定の基準値以下にするためには好適と言える。 パワーアンプ等に用いられるこの半導体装置を図 5にて説明する。 マザ一ボー ド 8上に多層配線基板 2が搭載されている。 多層配線基板 2上には、 ロウ材 9を 介して半導体素子 1が搭載されている。 この半導体素子 1は、 半導体基板 l aと、 この半導体基板 1 aの表層面に形成されたトランジスタ等の回路から構成されて いる。 この回路の一部には、 発熱部 1 b (例えば、 トランジスタのェミッタ 'ベ ース間領域など） が存在する。 3は、 多層配線基板 2を板厚方向に貫通した柱状 部材 （以下、 サーマルビアという） であり、 半導体基板 1 aとマザ一ボード 8と を電気的、 熱的に接続するものである。 5は、 多層配線基板 2の配線要素であり、 マザ一ボード 8と接続される。 上記多層配線基板 2上には上記半導体素子 1以外 に、 チップコンデンサや抵抗などの複数の部品 1 2が実装されている。  Heat generated from the semiconductor element passes through the two-wire substrate. Therefore, it can be said that the higher the thermal conductivity of the wiring board is, the more suitable it is to keep the temperature of the semiconductor element below a certain reference value. This semiconductor device used for a power amplifier and the like will be described with reference to FIG. The multilayer wiring board 2 is mounted on the motherboard 8. The semiconductor element 1 is mounted on the multilayer wiring board 2 via a brazing material 9. The semiconductor element 1 includes a semiconductor substrate la and a circuit such as a transistor formed on a surface of the semiconductor substrate 1a. A part of this circuit includes a heating part 1b (for example, a transistor emitter-base region). Reference numeral 3 denotes a columnar member (hereinafter, referred to as a thermal via) penetrating the multilayer wiring board 2 in the thickness direction, and electrically and thermally connects the semiconductor substrate 1a and the motherboard 8 to each other. Reference numeral 5 denotes a wiring element of the multilayer wiring board 2, which is connected to the motherboard 8. A plurality of components 12 such as a chip capacitor and a resistor are mounted on the multilayer wiring board 2 in addition to the semiconductor element 1.
—般的に、 多層配線基板 2の材料として電気絶縁性が高いガラスセラミック系 やガラスエポキシ系、 あるいはアルミナ等のセラミック系の材料が使用されてい る。 上記のような配線基板の材料は、 電気絶縁性が高い反面、 熱伝導率が低いと いう特性があるので、 これらの材料をそのまま多層配線基板 2の材料として使用 すると、 半導体装置全体の熱抵抗が高くなり、 半導体素子 1の発熱部 1 bの温度 が目標とする上限値を超えて上昇してしまうという問題がある。  Generally, a ceramic-based material such as glass-ceramic, glass-epoxy, or alumina having high electrical insulation is used as the material of the multilayer wiring board 2. The materials of the above-mentioned wiring board have the property of having a high electrical insulation property but a low thermal conductivity. Therefore, if these materials are used as they are as the material of the multilayer wiring board 2, the thermal resistance of the entire semiconductor device becomes large. And the temperature of the heat generating portion 1b of the semiconductor element 1 rises above the target upper limit.
このような問題を解決する一手段として、 図 5の半導体装置のように、 多層配 線基板 2にサーマルビア 3を複数配置し、 その上にハンダ等の導電性ロウ材 9を 用いて半導体素子 1を実装したものがある。 このサーマルビア 3を設けることに より、 半導体素子 1から多層配線基板 2の裏面を経てマザ一ボード 8上の共通接 地電極に至るまでを電気的に接続すると同時に、 半導体基板 1 aとマザ一ボード 8とを熱的に接続することができるので、 半導体素子 1の発熱部 1 bと多層配線 基板 2裏面との間の熱抵抗が低減し、 発熱部 1 bの温度を一定の基準値以下にす ることが可能である。  One solution to such a problem is to arrange a plurality of thermal vias 3 on a multilayer wiring board 2 as shown in the semiconductor device of FIG. There is one that implements 1. By providing the thermal vias 3, the semiconductor element 1 is electrically connected to the common ground electrode on the mother board 8 via the back surface of the multilayer wiring board 2, and at the same time, the semiconductor substrate 1a is connected to the mother board 1a. Since the board 8 can be thermally connected, the thermal resistance between the heating part 1 b of the semiconductor element 1 and the backside of the multilayer wiring board 2 is reduced, and the temperature of the heating part 1 b is lower than a certain reference value. It is possible to use
一方、 半導体装置については、 半導体基板 1 aの材料として、 従来、 例えば S i単結晶基板が用いられ、 この単結晶基板上に MO S F E Tの回路を形成する などして高周波パワーアンプを構成してきた。 この S i系の材料は熱伝導率が比 較的高いため、 素子表面の発熱部 1 bと多層配線基板 2裏面との間の熱抵抗は、 後述する G a A s系などの化合物半導体基板を用いた場合ほど大きくならない。 ところが、 高周波パワーアンプの効率を改善するためには、 S i系の MO S F E Tでは十分ではないという問題がある。 このため、 高周波パワーアンプの出力向 上及び高率改善を図る目的から、 半導体基板を G a A s系の化合物半導体基板で 形成したものがある。 On the other hand, in semiconductor devices, for example, a Si single crystal substrate has conventionally been used as a material of the semiconductor substrate 1a, and a high frequency power amplifier has been formed by forming a MO SFET circuit on the single crystal substrate. . The thermal conductivity of this Si-based material is Since it is relatively high, the thermal resistance between the heat generating portion 1b on the element surface and the rear surface of the multilayer wiring board 2 does not become as large as when a GaAs-based compound semiconductor substrate described later is used. However, there is a problem that Si-based MOS FETs are not enough to improve the efficiency of high-frequency power amplifiers. For this reason, there is a semiconductor substrate formed of a GaAs-based compound semiconductor substrate for the purpose of improving the output of a high-frequency power amplifier and improving the efficiency.
この G a A s系材料は、 熱伝導率が低く電気絶縁性が高いという特性があるた め、 半導体基板 1 aの一部にバイァホールと呼ばれる貫通孔を穿設し、 半導体素 子裏面には金メツキ等のメツキ層を設け、 上記バイァホールを経由して半導体基 板 1 aの表面側の特定の配線と半導体基板の裏面との間を電気的に接続する場合 がある。 これにより配線インダクタンスを低減できる。 この場合、 前記メツキ層 が熱拡散板としての機能を果たし、 素子表面の発熱部 1 bと多層配線基板 2の裏 面との間の熱抵抗が小さくなり、 結果的に、 熱伝導率が低い G a A s系材であつ てもパワーアンプ全体の熱抵抗を低減することが可能である。  Since this GaAs-based material has a characteristic of low thermal conductivity and high electrical insulation, a through hole called a via hole is formed in a part of the semiconductor substrate 1a, and a back surface of the semiconductor element is formed on the back surface of the semiconductor element. There is a case where a plating layer such as a gold plating is provided and a specific wiring on the front surface side of the semiconductor substrate 1a is electrically connected to the rear surface of the semiconductor substrate via the via hole. Thereby, the wiring inductance can be reduced. In this case, the plating layer functions as a heat diffusion plate, and the thermal resistance between the heat generating portion 1b on the element surface and the back surface of the multilayer wiring board 2 decreases, resulting in low thermal conductivity. Even with GaAs-based materials, it is possible to reduce the thermal resistance of the entire power amplifier.
上記の熱拡散板として用いられるメツキ層は、 一般的にプレーテッドヒートシ ンク （以下、 P H Sという） と呼ばれ、 この P H Sとバイァホールとを組合わせ た半導体装置の例として、 例えば特開平 5— 1 5 2 3 4 0号公報などがある。 図 6は、 半導体素子 1を構成する半導体基板 1 aと配線基板 2との間に熱拡散 板 1 3を介在させた半導体装置を示す。 図 6によれば、 携帯通信機のパワーアン プに限らず、 半導体素子を配線基板上に実装する場合、 サーマルビアを配線基板 2に設けない構造のものが考えられる。 このように、 熱拡散板を取付けた半導体 装置の例として、 例えば特開平 1 1— 1 9 1 6 0 3号公報ゃ特開平 1 0— 2 4 7 7 0 4号公報等がある。  The plating layer used as the above-mentioned heat diffusion plate is generally called a plated heat sink (hereinafter, referred to as PHS). As an example of a semiconductor device combining this PHS and via holes, see, for example, Japanese Patent Publication No. 52340/1990. FIG. 6 shows a semiconductor device in which a heat diffusion plate 13 is interposed between a semiconductor substrate 1 a constituting a semiconductor element 1 and a wiring substrate 2. According to FIG. 6, not only the power amplifier of the portable communication device but also a structure in which a thermal via is not provided in the wiring board 2 when a semiconductor element is mounted on the wiring board is conceivable. As an example of a semiconductor device having a heat diffusion plate attached thereto, for example, there are Japanese Patent Application Laid-Open Nos. 11-191603 and 10-247704.
図 7は、 配線基板 2を貫通するサーマルビア 3を半導体基板 1 aとほぼ同等若 しくはそれ以上の大きさで、 単一形状とした半導体装置を示したものである。 図 中、 7は P H Sを示す。 この P H S 7は、 上述したように、 金メッキ層などから なり、 半導体素子 1からの熱をサーマルビア 3に伝えるものである。  FIG. 7 shows a semiconductor device in which the thermal via 3 penetrating through the wiring board 2 is substantially the same as or larger than the semiconductor substrate 1a and has a single shape. In the figure, 7 indicates PHS. As described above, the PHS 7 is made of a gold plating layer or the like, and transfers heat from the semiconductor element 1 to the thermal via 3.
熱伝導率の低い G a A s系材料からなる半導体基板の裏面に P H Sを備え、 こ の P H Sを直接多層配線基板にハンダ等の口ゥ材を用いて固定した場合、 P H S を極端に厚く しないと S i系の半導体素子ほどには素子表面の発熱部から多層配 線基板に至るまでの熱抵抗を小さくすることができない。 ところが、 このように 厚い P H Sを金メツキで形成すると、 コスト的に極めて高価なものになってしま ラ。 If PHS is provided on the back of a semiconductor substrate made of a GaAs-based material with low thermal conductivity, and this PHS is directly fixed to the multilayer wiring board using If the thickness is not extremely large, the thermal resistance from the heating part on the element surface to the multilayer wiring board cannot be reduced as much as the Si-based semiconductor element. However, forming such a thick PHS with gold plating is extremely expensive in terms of cost.
また、 金メッキ層による P H Sの厚さが厚すぎると、 G a A sと金の線膨^ 数の差により、 例えば、 製造工程におけるリフロー工程で発生する熱応力や、 あ るいは素子動作時の発熱サイクルで、 金メツキ層と半導体基板の界面に発生する 熱応力によって半導体基板 1 aにクラックが発生したり、 半導体基板 1 aと P H Sとの間に剥離が生じてしまう恐れがある。  Also, if the thickness of the PHS due to the gold plating layer is too large, the difference in the linear expansion coefficient between G a s and gold may cause thermal stress generated in the reflow process in the manufacturing process, During the heat generation cycle, cracks may occur in the semiconductor substrate 1a or peeling may occur between the semiconductor substrate 1a and the PHS due to thermal stress generated at the interface between the gold plating layer and the semiconductor substrate.
また、 特開平 1 0— 2 4 7 7 0 4号公報で開示されているように、 下から配線 基板、 第一のロウ材、 熱拡散板、 第二のロウ材、 半導体素子の順に実装し、 半導 体基板の厚さを薄くして熱抵抗を小さくしょうとすると、 半導体基板内での三次 元の熱の広がりが不十分なため、 サーマルビアへの熱の伝達範囲が狭くなり、 熱 伝達に貢献しないサーマルビアが発生し、 サーマルビアの有効な利用が図れない。 このため、 多層配線基板内の熱抵抗を十分低減することができなくなり、 装置全 体の熱抵抗は必ずしも小さくならなレ、場合がある。  Also, as disclosed in Japanese Patent Application Laid-Open No. 10-247704, a wiring board, a first brazing material, a heat diffusion plate, a second brazing material, and a semiconductor element are mounted in this order from below. However, if the thermal resistance is reduced by reducing the thickness of the semiconductor substrate, the spread of heat to the thermal vias is reduced due to insufficient spread of the three-dimensional heat within the semiconductor substrate. Thermal vias that do not contribute to transmission are generated, making it impossible to use thermal vias effectively. For this reason, the thermal resistance in the multilayer wiring board cannot be sufficiently reduced, and the thermal resistance of the entire device may not always be small.
逆に、 半導体基板の厚さを厚くすると、 基板が厚いほど熱が広い範囲に拡散さ れてサ一マルビアを無駄なく有効に利用することが可能であるが、 半導体基板を 厚くするとバイァホールの加工が困難になったり、 コスト的に折合わないという 問題がある。 また、 半導体基板内の熱抵抗は厚いほど高くなるため、 装置全体の 熱抵抗は必ずしも小さくならなレ、。  Conversely, if the thickness of the semiconductor substrate is increased, the thicker the substrate is, the more the heat is diffused and the thermal vias can be effectively used without waste. There are problems that it becomes difficult and that the cost cannot be compromised. Also, since the thermal resistance in the semiconductor substrate increases as the thickness increases, the thermal resistance of the entire device does not necessarily decrease.
結局、 半導体基板表面の発熱部から多層配線基板裏面までの熱抵抗の合計で考 えると、 半導体基板の厚さが薄くても厚くても、 それだけではあまり有効な熱抵 抗低減策にはならない。  After all, considering the total thermal resistance from the heat-generating portion on the front surface of the semiconductor substrate to the back surface of the multilayer wiring substrate, whether the thickness of the semiconductor substrate is thin or thick does not alone provide a very effective thermal resistance reduction measure. .
ところで、 多層配線基板の母材が絶縁 の高いガラスセラミック系やガラスェ ポキシ系の材料であることは、 実質的に多層配線基板が断熱層となるので、 サー マルビア以外に熱を多層配線基板裏面に逃がす部分が存在しないことになる。 図 7に記載したように、 半導体基板 1 aの断面積と等しいか、 あるいはそれ以 上に大きレ、断面積の単一のサーマルビア 3を形成することによつて熱抵抗を十分 に低減させることができるものと考えられるが、 単一の巨大なサーマルビアを形 成すると、 サーマルビアの内部に巣ができてしまい、 結果的に熱抵抗を上昇させ てしまう可能性が高い。 By the way, the fact that the base material of the multilayer wiring board is a highly insulating glass-ceramic or glass epoxy material means that the multilayer wiring board is essentially a heat insulating layer. There will be no part to escape. As shown in FIG. 7, by forming a single thermal via 3 having a cross-sectional area that is equal to or larger than the cross-sectional area of the semiconductor substrate 1a, sufficient thermal resistance can be obtained. However, if a single large thermal via is formed, nests will be formed inside the thermal via, and as a result, the thermal resistance will likely increase.
—方、 多層配線基板 2に貫通孔を設けて板状部材で作ったサーマルビア 3を圧 入して装置を形成する場合、 熱抵抗の点では問題のない材料を選択しても、 サー マルビア 3と多層配線基板 2の線膨張係数を一定の誤差範囲内で一致させないと 素子発熱時に熱応力で破壊してしまう可能性がある。 この問題を回避するために サーマルビア 3の寸法を多層配線基板 2の貫通孔ょりかなり小さくしてしまうと 今度はサーマルビア 3の固定方法を別途考える必要が生じ、 コスト増の一因とな つてしまう。  On the other hand, when forming a device by press-fitting a thermal via 3 made of a plate-like member with a through hole provided in the multilayer wiring board 2, even if a material having no problem in terms of thermal resistance is selected, the thermal via If the coefficient of linear expansion of 3 and the multilayer wiring board 2 are not matched within a certain error range, the element may be broken by thermal stress during heat generation. If the dimensions of the thermal vias 3 are made considerably smaller than the through-holes of the multilayer wiring board 2 in order to avoid this problem, it will be necessary to consider a different method of fixing the thermal vias 3 and this will contribute to an increase in cost. I will.
本発明の目的は、 半導体基板を厚くすることなく、 半導体素子からの熱を多層 配線基板から外部に効率良く伝達させることが可能な半導体装置を低コストで提 供することにある。  An object of the present invention is to provide a low-cost semiconductor device capable of efficiently transmitting heat from a semiconductor element to the outside from a multilayer wiring board without increasing the thickness of the semiconductor substrate.
発明の開示 Disclosure of the invention
上記目的は、 配線基板上に実装される半導体素子と、 前記配線基板内に配置さ れ、 この配線基板を厚さ方向に貫通して設けられた第 1の熱伝導部材と、 前記半 導体素子と第 1の熱伝導部材とを熱的に接続する第 2の熱伝導部材とを備えたこ とにより達成される。  The object is to provide a semiconductor element mounted on a wiring board, a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction, and the semiconductor element. And a second heat conductive member for thermally connecting the first heat conductive member and the first heat conductive member.
また、 配線基板上に実装される半導体素子と、 前記配線基板内に配置され、 こ の配線基板を厚さ方向に貫通して設けられた第 1の熱伝導部材と、 この第 1の熱 伝導部材と前記半導体素子との間に設けられた熱拡散板と、 この熱拡散板と前記 第 1の熱伝導部材とを熱的に接続する第 2の熱伝導部材を設けたことにより達成 される。  A semiconductor element mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction; This is achieved by providing a heat diffusion plate provided between a member and the semiconductor element, and a second heat conduction member for thermally connecting the heat diffusion plate and the first heat conduction member. .
また、 配線基板上に実装される半導体素子と、 前記配線基板内に配置され、 こ の配線基板を厚さ方向に貫通して設けられた第 1の熱伝導部材と、 この第 1の熱 伝導部材と前記半導体素子との間に設けられ、 前記半導体素子の面積と同一若し くはそれ以上の面積を有する熱拡散板と、 この熱拡散板と前記第 1の熱伝導部材 とを熱的に接続し、 前記半導体素子の面積と同一若しくはそれ以上の面積を有す る第 2の熱伝導部材を設けたことにより達成される。 また、 請求項 1記載の半導体装置において、 前記半導体素子が S i等の単結晶 半導体基板または G a A s等の化合物半導体基板上に、 複数のトランジスタまた はダイォード等からなる多フィンガー素子が形成されたことにより達成される。 また、 前記半導体素子と配線基板との間に配置される第 2の熱伝導部材は、 上 記半導体素子よりも熱伝導率の高い材料であることにより達成される。 A semiconductor element mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction; A heat diffusion plate provided between the member and the semiconductor element and having an area equal to or larger than the area of the semiconductor element; and thermally connecting the heat diffusion plate and the first heat conductive member to each other. This is achieved by providing a second heat conductive member having an area equal to or larger than the area of the semiconductor element. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a single crystal semiconductor substrate such as Si or a compound semiconductor substrate such as GaAs, and a multi-finger element including a plurality of transistors or diodes is formed. It is achieved by doing. Further, the second heat conductive member disposed between the semiconductor element and the wiring board is achieved by using a material having higher thermal conductivity than the semiconductor element.
また、 前記半導体素子と配線基板との間に配置される第 2の熱伝導部材と、 上 記半導体素子と第 2の熱伝導部材との間に配置される熱拡散板のいずれもが上記 半導体素子よりも熱伝導率の高レ、材料であることにより達成される。  Further, both the second heat conductive member disposed between the semiconductor element and the wiring board, and the heat diffusion plate disposed between the semiconductor element and the second heat conductive member are the same as those of the semiconductor device. This is achieved by using a material having higher thermal conductivity than the element.
また、 前記半導体素子、 第 2の熱伝導部材、 熱拡散板の厚さが、 熱拡散板が最 も薄く、 第 2の熱伝導部材が最も厚い構成であることにより達成される。  The thickness of the semiconductor element, the second heat conductive member, and the heat diffusion plate is achieved by the thinnest heat diffusion plate and the thickest second heat conductive member.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明における基本的な実施形態を備えた半導体装置の断面図。 FIG. 1 is a sectional view of a semiconductor device having a basic embodiment according to the present invention.
図 2は、 本発明における配線基板を貫通しないサーマルビアを備えた半導体装置 の断面図。 FIG. 2 is a cross-sectional view of a semiconductor device having a thermal via that does not penetrate a wiring board according to the present invention.
図 3は、 本発明における P H Sを備えた半導体装置の断面図。 FIG. 3 is a cross-sectional view of a semiconductor device having PHS according to the present invention.
図 4は、 本発明における P H Sとサーマルビアとの間の熱伝導部材を備えた半導 体装置の断面図。 FIG. 4 is a cross-sectional view of a semiconductor device provided with a heat conducting member between PHS and a thermal via according to the present invention.
図 5は、 従来の半導体装置の一例を示す断面図。 FIG. 5 is a cross-sectional view illustrating an example of a conventional semiconductor device.
図 6は、 従来の半導体装置の一例を示す断面図。 FIG. 6 is a cross-sectional view illustrating an example of a conventional semiconductor device.
図 7は、 従来の半導体装置の一例を示す断面図。 FIG. 7 is a cross-sectional view illustrating an example of a conventional semiconductor device.
図 8は、 本発明における複数の種類の半導体素子が一つの配線基板上に混載した 半導体装置の断面図。 FIG. 8 is a cross-sectional view of a semiconductor device according to the present invention in which a plurality of types of semiconductor elements are mixedly mounted on one wiring board.
図 9は、 本発明を適用した半導体装置の一部を切り出した斜視図。 FIG. 9 is a perspective view of a part of a semiconductor device to which the present invention is applied.
図 1 0は、 本発明における複数の種類の半導体素子が一つの配線基板上に混載し た半導体装置の上面及び底面を示す図。 FIG. 10 is a diagram showing a top surface and a bottom surface of a semiconductor device according to the present invention in which a plurality of types of semiconductor elements are mixedly mounted on one wiring board.
図 1 1は、 本発明における半導体素子が配線基板上に実装されるプロセス工程の 一例を示す図。 FIG. 11 is a diagram showing an example of a process step in which a semiconductor element according to the present invention is mounted on a wiring board.
図 1 2は、 本発明における半導体素子が H B T素子である場合の代表的なェミツ タ電極周辺を示す半導体装置の断面図。 図 1 3は、 本発明における発熱領域の配置の一例を示す模擬的な上面図。 FIG. 12 is a cross-sectional view of a semiconductor device showing the vicinity of a typical emitter electrode when the semiconductor element in the present invention is an HBT element. FIG. 13 is a simulated top view showing an example of the arrangement of heat generating regions according to the present invention.
図 1 4は、 本発明における熱伝導部材の厚さがモジュール熱抵抗に与える影響を 示すグラフ。  FIG. 14 is a graph showing the effect of the thickness of the heat conductive member on the module thermal resistance in the present invention.
図 1 5は、 本発明における熱伝導部材の面積がモジュール熱抵抗に与える影響を 示すグラフ。 FIG. 15 is a graph showing the effect of the area of the heat conducting member on the module thermal resistance in the present invention.
図 1 6は、 本発明における、 熱伝導部材を用いない場合において、 P H Sの厚さ がモジュール熱抵抗に与える影響を示すグラフ。 FIG. 16 is a graph showing the effect of the thickness of PHS on the thermal resistance of the module when no heat conducting member is used in the present invention.
図 1 7は、 本発明における P H Sがない場合に熱伝導部材の厚さがモジュール熱 抵抗に与える影響を示すグラフ。 FIG. 17 is a graph showing the effect of the thickness of the heat conducting member on module thermal resistance in the absence of PHS in the present invention.
図 1 8は、 本発明における熱伝導部材の種類がモジュール熱抵抗に与える影響を 示すグラフ。 FIG. 18 is a graph showing the effect of the type of heat conducting member on the module thermal resistance in the present invention.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
本発明における一実施形態を図 1及び図 2を用いて説明する。 図 1は、 本発明 を備えた半導体装置の断面図、 図 2は、 本発明の多層配線基板を貫通しないサー マルビアを設けた半導体装置の断面図である。  One embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a semiconductor device provided with the present invention, and FIG. 2 is a sectional view of a semiconductor device provided with a thermal via which does not penetrate a multilayer wiring board of the present invention.
図 1において、 半導体素子 1を構成する半導体基板 1 aは、 配線基板 2上に実 装されている。 配線基板 2内部には、 導電性と高熱伝導性を有するサーマルビア 3が配線基板 2を貫通するように複数本設けられている。 個々のサーマルビア 3 と半導体基板 1 aとの間には、 熱伝導部材 4が介在され、 電気的かつ熱的に接続 させている。  In FIG. 1, a semiconductor substrate 1 a constituting a semiconductor element 1 is mounted on a wiring board 2. Inside the wiring board 2, a plurality of thermal vias 3 having conductivity and high thermal conductivity are provided so as to penetrate the wiring board 2. A heat conductive member 4 is interposed between each of the thermal vias 3 and the semiconductor substrate 1a, and is electrically and thermally connected.
前記配線基板 2は、 絶縁性が高く、 熱伝導率が小さいガラスセラミック系ゃガ ラスエポキシ系の材料であるため、 サーマルビア 3以外の部分は断熱に近く、 配 線基板 2内で電気的かつ熱的に良伝導性であるのはほぼサーマルビア 3のみであ る。 このため、 熱伝導部材 4を用いて、 できるだけ多くのサ一マルビア 3と半導 体基板 1とを熱的に接続することにより、 半導体基板 1 aの表層面の発熱部 1 b と配線基板 2裏面との間の熱抵抗を低減することが可能である。 半導体基板 1 a は、 この部分の熱抵抗を小さくするために極力薄く （Ι Ο Ο μ πι程度以下、 典型 的には 3 0〜5 0 μ πι程度） している。  Since the wiring board 2 is made of a glass-ceramic-based glass epoxy material having a high insulation property and a low thermal conductivity, the portions other than the thermal vias 3 are close to heat insulation, and are electrically and electrically connected within the wiring board 2. Only thermal via 3 has good thermal conductivity. For this reason, as many thermal vias 3 as possible are thermally connected to the semiconductor substrate 1 by using the heat conductive member 4 so that the heat generating portion 1 b on the surface of the semiconductor substrate 1 a and the wiring substrate 2 are connected. It is possible to reduce the thermal resistance between the back surface. The semiconductor substrate 1a is made as thin as possible (about 以下 Ο μπι or less, typically about 30 to 50 μπι) in order to reduce the thermal resistance of this portion.
薄くすることによって半導体基板 1 a内での熱の拡散が不十分となっても、 半 導体基板 1 a裏面で局所的に温度の高い範囲とサーマルビア 3とを熱伝導部材 4 を用いて熱的に効果的に接続することにより、 配線基板 2裏面と発熱部 1 bとの 間の熱抵抗を低減することができる。 Even if the heat diffusion inside the semiconductor substrate 1a becomes insufficient due to the thinning, The thermally conductive member 4 is used to thermally and effectively connect the locally high temperature range and the thermal via 3 on the back surface of the conductive board 1a, thereby providing a heat transfer portion between the back surface of the wiring board 2 and the heat generating portion 1b. Thermal resistance can be reduced.
前記熱伝導部材 4が位置する半導体基板 1 aと配線基板 2との間の空間は、 絶 縁性の部材を用いて封じていても問題なく、 図 1のように、 空間上に浮いた形で 実装させても良い。 また、 配線基板 2の裏面の配線要素 5は、 サーマルビア 3と 電気的に接続されており、 この配線要素 5を介してマザ一ボード 8上の共通接地 配線に接続している。 ところで、 配線要素 5は、 配線基板 2裏面全面を覆う必要 はない。 この点は、 以下に説明する本発明の全ての実施形態に共通する。  The space between the semiconductor substrate 1a where the heat conducting member 4 is located and the wiring board 2 can be sealed by using an insulating member without any problem. May be implemented. The wiring element 5 on the back surface of the wiring board 2 is electrically connected to the thermal via 3, and is connected to the common ground wiring on the mother board 8 via the wiring element 5. By the way, the wiring element 5 does not need to cover the entire back surface of the wiring board 2. This point is common to all embodiments of the present invention described below.
また、 図 1では、 サーマルビア 3を均等に配置した例を示したが、 サーマルビ ァ 3の本数や、 その間隔は図 1に示した例に限定されるものではない。  Further, FIG. 1 shows an example in which the thermal vias 3 are evenly arranged. However, the number of thermal vias 3 and their intervals are not limited to the example shown in FIG.
図 2において、 配線基板 2が多層配線基板である場合、 各層間に高導電性で、 かつ高熱伝導性の配線要素 5が介在されていれば、 配線基板 2を厚さ方向を貫通 しないか、 あるいは直接熱伝導部材 4と接しないサーマルビア 6があっても問題 ない。 極力多くのサーマルビア 3もしくは 6と半導体基板 1 aが熱的に接続され ることが望ましいのであり、 熱伝導部材 4により直接半導体基板 1 aと接続でき ないサーマルビア 6が、 層間に存在する配線要素 5によって熱的に有効に活用で きるようになり、 更に熱抵抗を低減できる。  In FIG. 2, when the wiring board 2 is a multilayer wiring board, if a wiring element 5 having high conductivity and high thermal conductivity is interposed between the layers, the wiring board 2 may not penetrate the wiring board 2 in the thickness direction. Alternatively, there is no problem even if there is a thermal via 6 that does not directly contact the heat conduction member 4. It is desirable that as many thermal vias 3 or 6 as possible are thermally connected to the semiconductor substrate 1a, and the thermal vias 6, which cannot be directly connected to the semiconductor substrate 1a due to the heat conducting member 4, are located between the layers. Element 5 makes it possible to effectively utilize the heat, and further reduces the thermal resistance.
多層配線基板 2上には、 半導体素子 1以外の回路要素 1 2が実装されている。 これらの回路要素 1 2と多層配線基板 2裏面に設けられた独立した配線間を上記 サーマルビア 3とは独立したスルーホールを用いて電気的に接続しても構わなレ、。 なお、 個々の熱伝導部材 4の断面積は、 それぞれの熱伝導部材 4と接続するサ 一マルビア 3まで熱が伝達される際に生じる温度差を一定にすることが重要であ り、 半導体基板 1 aからサーマルビア 3までの距離が最も長い熱伝導部材 4の断 面積を大きくすることによって熱抵抗を調整することが可能である。  Circuit elements 12 other than the semiconductor element 1 are mounted on the multilayer wiring board 2. The circuit elements 12 and the independent wiring provided on the back surface of the multilayer wiring board 2 may be electrically connected to each other using through holes independent of the thermal via 3. It is important that the cross-sectional area of each heat conductive member 4 keeps a temperature difference generated when heat is transferred to the thermal via 3 connected to each heat conductive member 4 constant. The thermal resistance can be adjusted by increasing the cross-sectional area of the heat conductive member 4 having the longest distance from 1 a to the thermal via 3.
本発明における他の一実施形態を図 3を用いて説明する。 図 3は、 本発明の他 の実施例を備えた半導体装置の断面図である。  Another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of a semiconductor device having another embodiment of the present invention.
図 3において、 半導体基板 1 aと熱伝導部材 4との間に金などのメツキ層から なる P H S 7を設けたものである。 半導体基板 1 aが厚くない場合には、 半導体 基板 1 aの表層面に位置する複数の発熱部 1 bから発生する熱が半導体素子 1内 部で十分横に拡散せず、 半導体素子 1裏面の温度分布が均一にならない。 例えば、 個々の発熱部 1 b直下の温度が高く、 その間の部分の温度は低い場合がある。 熱 伝導率に空間分布のない材料の温度分布に斑があるということは、 その材料を通 過する熱流束に分布があることと等しい。 このため、 個々の熱伝導部材 4を通過 してサーマルビア 3に伝えられる熱の量が均等にならず、 一部のサ一マルビア 3 は、 有効に機能しない可能性がある。 従って、 半導体基板 1 a裏面の温度分布は なるべく均一であることが望ましレ、。 In FIG. 3, a PHS 7 made of a plating layer such as gold is provided between a semiconductor substrate 1 a and a heat conducting member 4. If the semiconductor substrate 1a is not thick, The heat generated from the plurality of heat generating portions 1b located on the surface of the substrate 1a does not sufficiently diffuse inside the semiconductor element 1, and the temperature distribution on the back surface of the semiconductor element 1 is not uniform. For example, the temperature immediately below each heat generating portion 1b may be high, and the temperature between the portions may be low. Variations in the temperature distribution of a material that has no spatial distribution of thermal conductivity are equivalent to a distribution of the heat flux through that material. For this reason, the amount of heat transmitted to the thermal vias 3 through the individual heat conducting members 4 is not uniform, and some thermal vias 3 may not function effectively. Therefore, it is desirable that the temperature distribution on the back surface of the semiconductor substrate 1a be as uniform as possible.
図 3は、 熱伝導部材 4を通過して個々のサーマルビア 3に伝えられる熱の量を 均等にするために、 半導体基板 1 aと熱伝導部材 4との間に P H S 7を設けたも のである。 半導体基板 1 aを薄くした場合であっても、 P H S 7裏面の温度分布 は、 外周縁が最も温度が低く、 中心部が最も温度が高くなるような同心円状に近 い温度分布となり、 半導体素子 1表面側の複数の発熱領域 1 bの分布の影響を相 殺することができる。 これは、 P H S 7の厚さ分だけ熱抵抗が上昇するマイナス の影響よりも、 P H S 7によって熱が一様に拡散するプラスの影響の方が大きい ために熱抵抗を低減することができる。 また、 発熱部 1 bの配置に応じて熱伝導 部材 4の半導体基板 1 aと接する部分の配置を調整する必要もほとんどなくする ことができる。 Fig. 3 shows that PHS 7 is provided between the semiconductor substrate 1a and the heat conductive member 4 in order to equalize the amount of heat transmitted to the individual thermal vias 3 through the heat conductive member 4. is there. Even when the semiconductor substrate 1a is thinned, the temperature distribution on the back surface of the PHS 7 is close to a concentric circle with the lowest temperature at the outer periphery and the highest temperature at the center. The influence of the distribution of the plurality of heating regions 1b on one surface side can be offset. This is because the positive effect that heat is uniformly diffused by the PHS 7 is greater than the negative effect that the thermal resistance increases by the thickness of the PHS 7, and thus the thermal resistance can be reduced. Further, it is possible to almost no need to adjust the placement of the parts in contact with the semiconductor substrate 1 a heat conducting member 4 according to the arrangement of the heat generating portion 1 b.
本発明の他の一実施例を図 4を用いて説明する。 図 4は、 本発明の他の実施例 を備えた半導体装置の断面図である。  Another embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view of a semiconductor device having another embodiment of the present invention.
図 4において、 半導体基板 1 aの裏面に、 半導体基板 1 aとほぼ同等の断面積、 若しくはそれ以上の断面積を有する P H S 7を設けたものである。 一方、 P H S 7と多層配線基板 2との間には、 熱伝導部材 1 0が介在されている。 この熱伝導 部材 1 0の上下両面には、 ロウ材が設けられ、 多層配線基板 2側には、 第 1の口 ゥ材 9が、 P H S側には、 第 2のロウ材 1 1が設けられている。 多層配線基板 2 には、 高導電性かつ高熱伝導性のサーマルビア 3が多層配線基板 2を貫通するよ うに設けられている。 これらのロウ材 9、 1 1は、 半導体基板 1 aとサーマルビ ァ 3を電気的、 熱的に接続している。  In FIG. 4, a PHS 7 having a cross-sectional area substantially equal to or larger than that of the semiconductor substrate 1a is provided on the back surface of the semiconductor substrate 1a. On the other hand, a heat conducting member 10 is interposed between the PHS 7 and the multilayer wiring board 2. A brazing material is provided on the upper and lower surfaces of the heat conducting member 10, a first filler material 9 is provided on the multilayer wiring board 2 side, and a second brazing material 11 is provided on the PHS side. ing. The multilayer wiring board 2 is provided with a thermal via 3 having high conductivity and high thermal conductivity so as to penetrate the multilayer wiring board 2. These brazing materials 9 and 11 electrically and thermally connect the semiconductor substrate 1 a and the thermal via 3.
多層配線基板 2内に配置されたサーマルビア 3の領域が半導体素子 1の面積よ り広い場合は、 熱伝導部材 10の面積が半導体基板 1 aの面積より大きいことが 必要であり、 可能であれば全てのサーマルビア 3にまたがる面積を有することが 望ましい。 The area of the thermal via 3 arranged in the multilayer wiring board 2 is equal to the area of the semiconductor element 1. If it is wider, the area of the heat conductive member 10 needs to be larger than the area of the semiconductor substrate 1a, and if possible, it is desirable to have an area that covers all the thermal vias 3.
PHS 7を用いることにより、 PHS 7裏面、 即ち熱伝導部材 1 0と向い合う 面の温度分布を均一化することが可能であり、 半導体素子 1から熱伝導部材 10 までの熱抵抗を低減することができる。 また、 熱伝導部材 1 0を単一の板状部材 とすることで、 図 1、 2または 3に示した本発明の他の実施形態と比較して低コ ス トで半導体素子 1の発熱部 1 bで発生する熱を多層配線基板 2に配置された高 導電性かつ高熱伝導性のサーマルビア 3に効率良く伝達することができる。 この ため、 熱伝導部材 10と配線基板 2裏面との間の熱抵抗を低減でき、 P H S 7と 熱伝導部材 1 0、 及びサーマルビア 3の組み合わせにより、 低コス トで低熱抵抗 構造を実現することができる。  By using PHS 7, it is possible to make the temperature distribution on the back surface of PHS 7, that is, the surface facing the heat conducting member 10 uniform, and to reduce the thermal resistance from the semiconductor element 1 to the heat conducting member 10. Can be. Further, by forming the heat conducting member 10 as a single plate-shaped member, the heat generating portion of the semiconductor element 1 can be manufactured at a lower cost as compared with the other embodiments of the present invention shown in FIGS. The heat generated in 1 b can be efficiently transmitted to the high-conductivity and high-thermal-conductivity thermal vias 3 arranged on the multilayer wiring board 2. Therefore, the thermal resistance between the heat conductive member 10 and the back surface of the wiring board 2 can be reduced, and a low cost and low heat resistance structure can be realized by combining the PHS 7 with the heat conductive member 10 and the thermal via 3. Can be.
なお、 熱伝導部材 1 0の厚さは、 半導体基板 1 aの厚さよりも厚く、 配線基板 2のサーマルビアの貫通する部分の厚さより薄いか、 同程度であることが望まし レ、。 また、 半導体基板 1 aと PHS 7の厚さについては、 PHS7の方が薄い方 が望ましい。 即ち、 半導体基板 l a、 PHS 7、 熱伝導部材 10、 配線基板 2の サーマルビア 3が貫通する部分の厚さをそれぞれ t 1、 t 2、 t 3、 t 4とする と、 本一実施形態における半導体装置では、  It is desirable that the thickness of the heat conductive member 10 be larger than the thickness of the semiconductor substrate 1a and smaller than or equal to the thickness of the portion of the wiring substrate 2 through which the thermal via penetrates. As for the thickness of the semiconductor substrate 1a and the thickness of the PHS 7, it is preferable that the thickness of the PHS 7 is thinner. That is, assuming that the thicknesses of the portions of the semiconductor substrate la, the PHS 7, the thermal conductive member 10, and the thermal via 3 of the wiring board 2 that penetrate are t1, t2, t3, and t4, respectively, In semiconductor devices,
t 2< t l < t 3≤ t 4  t 2 <t l <t 3 ≤ t 4
という関係が成立する。 一例としては、 Is established. As an example,
t 2=5〜20 μπι程度  t 2 = About 5 to 20 μπι
t 1 = 30〜 50、 最大 100 m程度  t 1 = 30 to 50, up to about 100 m
t 3= 1 50〜300 ju m程度  t 3 = 1 About 50-300 ju m
ΐ 4 = 300〜450 μ m程度  ΐ 4 = about 300 to 450 μm
とする場合があるが、 上記関係式を満たせば必ずしも上記の範囲に限定されない ことは言うまでもない。 また、 第 1及び第 2のロウ材、 サーマルビアの厚さをそ れぞれ t 5、 t 6、 t 7とすると以下の関係が成り立つよう、 厚さを調整する。 However, it goes without saying that the present invention is not necessarily limited to the above range as long as the above relational expression is satisfied. If the thicknesses of the first and second brazing materials and the thermal vias are respectively t5, t6, and t7, the thicknesses are adjusted so that the following relationship is satisfied.
t 2≤ t 5= t 6≤ t l  t 2≤ t 5 = t 6≤ t l
t 4 = t 7 一方、 半導体基板 1 a、 PHS 7、 熱伝導部材 1 0、 配線基板 2の母材、 第 1 のロウ材 9、 第 2のロウ材 1 1、 サーマルビア 3の熱伝導率をそれぞれ、 え 1、 ぇ 2、 ぇ 3、 え 4、 え 5、 ぇ 6、 ぇ 7とし、 線膨張係数をそれぞれ α 1、 α2、 α 3、 α 4、 ひ 5、 α6、 α 7とすれば、 本一実施形態においては次の関係が成 り立つように材料を選択する。 t 4 = t 7 On the other hand, the thermal conductivity of the semiconductor substrate 1a, the PHS 7, the thermal conductive member 10, the base material of the wiring board 2, the first brazing material 9, the second brazing material 11, and the thermal conductivity of the thermal via 3 are respectively: , ぇ 2, ぇ 3, 44, 55, ぇ 6, ぇ 7, and the linear expansion coefficients are α1, α2, α3, α4, HI5, α6, α7, respectively. In the form, select the materials so that the following relationship is established.
え 4ぐえ 5 = λ 6 = λ 1ぐ又 2 =ぇ 3 =ぇ 7  4 4 5 = λ 6 = λ 1 cross 2 = ぇ 3 = ぇ 7
α ο α 上 、 α 2、 α 4±?α 7 <^ α 3^ α 6 <^ α 3 α ο α, α 2, α 4 ± ? α 7 <^ α 3 ^ α 6 <^ α 3
ここで、 記号 は、 物性値がほぼ同じオーダ一であるという程度の意味であり、 大小関係については必ずしもこだわらないことを意味する。 即ち、 配線基板 2の 母材、 各種口ゥ材と半導体基板 1 a、 各種熱伝導 ·熱拡散部材の順に熱抵抗が高 くなつていく構成である。 なお、 半導体基板 1 aが S i と同程度以上の熱伝導率 を有する場合 （温度 3 73K (1 00°C) で； I 1 ^ 1 00 [WZ (m · K) ] 程 度かそれ以上） 、 半導体基板 1 aとロウ材 9、 1 1の熱伝導率の関係に関しては λ 5 =? , 6 ^ λ 丄  Here, the symbol means that the physical property values are almost the same order, and it means that the magnitude relation is not necessarily particular. In other words, the base material of the wiring board 2, the various types of the opening material, the semiconductor substrate 1 a, and the various thermal conductive and heat diffusing members are arranged so that the thermal resistance increases in this order. In the case where the semiconductor substrate 1a has a thermal conductivity equal to or higher than that of Si (at a temperature of 373K (100 ° C); about I1 ^ 100 [WZ (m · K)] or more) ) Regarding the relationship between the thermal conductivity of the semiconductor substrate 1a and the thermal conductivity of the brazing materials 9 and 11, λ5 = ?, 6 ^ λ 丄
となっても構わない。  It does not matter.
線膨張係数については、 第 2のロウ材の線膨張係数が最も低く、 半導体基板 1 aが同程度かそれ以上、 PHS 7が非常に高い。 第 2のロウ材より下の部材につ いては、 配線基板 2の母材とサーマルビア 3がほぼ等しく、 熱伝導部材 1 0の線 膨張係数が高い。  Regarding the coefficient of linear expansion, the coefficient of linear expansion of the second brazing material is the lowest, the semiconductor substrate 1a is comparable or higher, and the PHS 7 is very high. As for the members below the second brazing material, the base material of the wiring board 2 and the thermal vias 3 are almost equal, and the coefficient of thermal expansion of the heat conductive member 10 is high.
図 4に示した一実施例においては、 半導体基板 1 aの材料を S i系単結晶、 も しくは G a A s系等の化合物からなる半導体基板とすることが考えられる。 また、 熱伝導部材 1 0の材質としては銅、 アルミニウム、 モリブデン等の金属、 もしく はそれらを主成分とする合金が考えられるが、 熱抵抗を目標値以下にできるもの であれば、 必ずしも上記の材料でなくても良い。 一方、 第 1のロウ材 9は半田等 の材料が望ましく、 第二のロウ材 1 1は導電性銀ペース ト材などで、 導電性を有 し、 熱伝導率が半導体基板 1 aとほぼ同じ程度である熱硬化性の材料であること が望ましい。  In the embodiment shown in FIG. 4, the material of the semiconductor substrate 1a may be a Si-based single crystal or a semiconductor substrate made of a GaAs-based compound or the like. The material of the heat conducting member 10 may be a metal such as copper, aluminum, or molybdenum, or an alloy containing these as a main component. The material need not be. On the other hand, the first brazing material 9 is desirably a material such as solder, and the second brazing material 11 is a conductive silver paste material or the like, having conductivity, and having substantially the same thermal conductivity as the semiconductor substrate 1a. It is desirable that the material be a thermosetting material of a certain degree.
本実施形態では、 第一のロウ材 9の融点は第二のロウ材 1 1の製造工程上の硬 化温度より高く、 第二のロウ材 1 1上に PHS 7を介して半導体素子 1を固定す る際に第一のロウ材 9が溶けてしまわないような物性値を有する材料を選択して いる。 導電性銀ペース ト材を採用する理由の一つは、 このペース ト材の母材が熱 硬化性樹脂であるためで、 ペースト材が硬化する時に微小なクラックが無数に入 ることなどにより、 製造プロセス中で発生する熱伝導部材 1 0と第 2のロウ材 1 1、 もしくは P H S 7と第 2のロウ材との界面で発生する熱応力を緩和すること ができる。 また、 第 2のロウ材硬化後の発熱動作で生じた P H S 7と半導体基板 1 aとの界面における熱応力は、 P H S 7を十分薄くすることにより、 金メツキ 層が降伏、 変形することにより緩和することができる。 In the present embodiment, the melting point of the first brazing material 9 is higher than the curing temperature in the manufacturing process of the second brazing material 11, and the semiconductor element 1 is placed on the second brazing material 11 via the PHS 7. Fix In this case, a material having physical properties such that the first brazing material 9 is not melted when the material is used is selected. One of the reasons for using conductive silver paste is that the base material of the paste is a thermosetting resin. The thermal stress generated at the interface between the heat conductive member 10 and the second brazing material 11 or the interface between the PHS 7 and the second brazing material generated during the manufacturing process can be reduced. The thermal stress at the interface between the PHS 7 and the semiconductor substrate 1a, which is generated by the heat generation operation after the second brazing material is cured, is relaxed by sufficiently thinning the PHS 7 by yielding and deforming the gold plating layer. can do.
図 5は、 半導体基板 1 aとサーマルビア 3がロウ材 9を介して接続された実施 例を示す。  FIG. 5 shows an embodiment in which the semiconductor substrate 1 a and the thermal via 3 are connected via the brazing material 9.
図 6は、 半導体基板 1 a配線基板 2が熱拡散板 1 3を介して接続されている実 施例を示す。  FIG. 6 shows an embodiment in which the semiconductor substrate 1 a and the wiring substrate 2 are connected via the heat diffusion plate 13.
図 7は、 サーマルビア 3が半導体基板 1 aの大きさと同等若しくはそれ以上の 大きさで、 一体成形品で形成された実施例を示す。  FIG. 7 shows an embodiment in which the thermal via 3 has a size equal to or larger than the size of the semiconductor substrate 1a and is formed as an integrated product.
本発明における他の一実施形態を図 8、 図 9、 1 0を用いて説明する。 図 8は、 本発明を備えた半導体装置の断面図である。 図 9はその一部を切り出した斜視図、 図 1 0は配線基板 2の上面 （図 1 0 a ) 及び底面図 （図 1 0 b ) と半導体素子 1 を含む断面図 （図 1 9 c ) である。  Another embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a sectional view of a semiconductor device provided with the present invention. FIG. 9 is a perspective view of a part cut out, and FIG. 10 is a top view (FIG. 10a) and a bottom view (FIG. 10b) of the wiring board 2 and a cross-sectional view including the semiconductor element 1 (FIG. 19c). It is.
図 8に示す本発明を適用した半導体装置は、 単一の配線基板 2に複数の種類の 半導体素子 1 6、 1 7を実装したものである。 半導体素子 1 6は G a A s系等の 比較的熱伝導率の低い半導体基板 1 6 a上に発熱部 1 6 bが形成され、 比較的厚 さの薄い半導体基板 1 6 aの裏面には P H S 7をメツキ等により形成している。 一方、 半導体素子 1 7では S i系等の比較的熱伝導率の高い半導体基板 1 7 a上 に発熱部 1 7 bが形成される。 半導体基板 1 7 aの熱伝導率が S i系材料の熱伝 導率とほぼ同等かそれ以上の場合、 半導体素子 1 7 aの厚さを数 1 Ο Ο μ πι程度 にすることで半導体基板 1 7 a裏面の温度分布をほぼ均一化できるため、 P H S 7や前述した熱伝導部材 1 0を用いなくても熱抵抗の目標値を達成できる場合が ある。 このような場合は、 図 8 aのように、 半導体基板 1 7は、 配線基板 2に第 二のロウ材 1 1を介して配線基板 2に直接実装することができるので、 コス ト低 減を図ることができる。 The semiconductor device to which the present invention shown in FIG. 8 is applied has a plurality of types of semiconductor elements 16 and 17 mounted on a single wiring board 2. The semiconductor element 16 has a heat generating portion 16b formed on a semiconductor substrate 16a having a relatively low thermal conductivity, such as a GaAs system, and has a relatively thin semiconductor substrate 16a on the back surface. PHS 7 is formed by plating. On the other hand, in the semiconductor element 17, a heat generating portion 17 b is formed on a semiconductor substrate 17 a having a relatively high thermal conductivity such as an Si-based material. When the thermal conductivity of the semiconductor substrate 17a is substantially equal to or higher than the thermal conductivity of the Si-based material, the thickness of the semiconductor element 17a is reduced to about several Ο Ο μππι to make the semiconductor substrate 17a. Since the temperature distribution on the 17a back surface can be made substantially uniform, the target value of the thermal resistance may be achieved without using the PHS 7 or the heat conducting member 10 described above. In such a case, as shown in FIG. 8A, the semiconductor substrate 17 can be directly mounted on the wiring board 2 via the second brazing material 11 via the second brazing material 11, so that the cost is low. Can be reduced.
図 8 aにおいて、 多層配線基板の表層 2 aには、 半導体装置 1 6、 1 7の他、 配線要素 1 0 1と、 抵抗やチップコンデンサなどの回路部品 1 2が実装されてい る。 配線要素 1 0 1または回路部品 1 2と半導体素子 1 6、 1 7は、 例えばボン デイングワイヤ 1 8により電気的に接続されている。  In FIG. 8A, in addition to semiconductor devices 16 and 17, wiring elements 101 and circuit components 12 such as resistors and chip capacitors are mounted on the surface layer 2a of the multilayer wiring board. The wiring element 101 or the circuit component 12 and the semiconductor elements 16 and 17 are electrically connected by, for example, a bonding wire 18.
図 8 aの断面図には示していないが、 多層配線基板 2の各層における配線要素 とスルーホール、 及び半導体素子 1 6、 1 7の組み合わせにより、 例えば携帯通 信端末用の高周波パワーアンプとして動作する一つの半導体装置 （以下、 モジュ ール） が構成される。 図 8 aの場合、 半導体素子 1 6、 1 7のG N DがP H S 7、 熱伝導部材 1 0、 サーマルビア 3、 多層配線基板の裏面 2 b上に形成された G N D配線層 5を介してマザ一ボード 8上の G N D配線層 1 0 2に電気的、 かつ熱的 に接続される。  Although not shown in the cross-sectional view of FIG. 8a, the combination of the wiring elements and through holes in each layer of the multilayer wiring board 2 and the semiconductor elements 16 and 17 operates, for example, as a high-frequency power amplifier for a mobile communication terminal. One semiconductor device (hereinafter, referred to as a module) is configured. In the case of FIG. 8a, the GND of the semiconductor elements 16 and 17 is connected to the mother via the PHS 7, the heat conductive member 10, the thermal via 3, and the GND wiring layer 5 formed on the back surface 2b of the multilayer wiring board. It is electrically and thermally connected to the GND wiring layer 102 on the board 8.
また、 入出力信号用などの電極 1 0 3も多層配線基板裏面 2 bに形成され、 こ の電極 1 0 3と多層配線基板表層 2 a上もしくは層間の配線要素 1 0 1、 回路要 素 1 2との間は配線基板 2側面もしくは内部にスルーホールとして形成された配 線 1 0 4により電気的に接続される。 マザ一ボード 8上には電極 1 0 3に対応す る配線層 1 0 5がそれぞれ形成されており、 電極 1 0 3と配線層 1 0 5が電気的 に接続される。 これらの配線層 5及び電極 1 0 3と配線層 1 0 2、 1 0 5との間 の接続には例えば低融点ハンダ等の第 3のロウ材 1 0 6を用いる。  Electrodes 103 for input / output signals are also formed on the back surface 2b of the multilayer wiring board, and the electrodes 103 and the wiring elements 101 on the surface layer 2a of the multilayer wiring board or between layers, and the circuit elements 1 The wiring 2 is electrically connected to the wiring board 2 by a wiring 104 formed as a through hole on the side surface or inside. Wiring layers 105 corresponding to the electrodes 103 are formed on the motherboard 8, respectively, and the electrodes 103 and the wiring layers 105 are electrically connected. A third brazing material 106 such as low-melting solder is used for connection between the wiring layers 5 and the electrodes 103 and the wiring layers 102 and 105.
上記構成において、 第 1のロウ材 9をハンダ、 第 2のロウ材を熱硬化性の導電 性ペース ト材、 第 3のロウ材をハンダとし、 それぞれの融点及び熱硬化温度を順 に T l、 Τ 2、 Τ 3とする。 まず熱伝導部材 1 0と半導体装置 1 7を多層配線基 板表層 2 aに実装し、 次に半導体装置 1 6を熱伝導部材 1 0上に実装し、 出来上 がったモジュールにおける多層配線基板裏面 2をマザ一ボード 8上に実装するェ 程を考えると  In the above configuration, the first brazing material 9 is a solder, the second brazing material is a thermosetting conductive paste material, and the third brazing material is a solder. , Τ2, Τ3. First, the heat conductive member 10 and the semiconductor device 17 are mounted on the surface 2a of the multilayer wiring board, and then the semiconductor device 16 is mounted on the heat conductive member 10 to obtain a multilayer wiring board in the completed module. Considering the process of mounting back side 2 on motherboard 8
T 1 > T 2 > T 3  T 1> T 2> T 3
となるよう、 材料を選択する。 Select the material so that
また、 上述のように半導体基板 1 7 a上に形成された発熱部 1 7 bの発熱量が 十分小さく、 しかも半導体基板 1 7 aが S i等の熱伝導率の高い材料を用いてい る場合、 P H S 7や熱伝導部材 1 0がなくても熱抵抗を目標とする上限値以下に できる場合があり、 このような場合は P H S 7や熱伝導部材 1 0を用いる必要性 はない。 従って、 複数のチップが一つの多層配線基板 2の上に実装される場合は、 そのチップを構成する半導体基板の物性値や発熱量などから、 熱的かつコスト的 に最適な構成を選択することができる。 半導体素子 1 6の厚さをそのまま t 1、 1 7の厚さを t 9、 マイクロストリップラインで形成されるようなチップ抵抗を 除く回路部品 1 2の厚さを t 8とすると、 上記構成では、 Further, as described above, the heat generation amount of the heat generating portion 17b formed on the semiconductor substrate 17a is sufficiently small, and the semiconductor substrate 17a is made of a material having a high thermal conductivity such as Si. In some cases, the thermal resistance can be reduced to the target upper limit or less even without the PHS 7 or the heat conducting member 10. In such a case, there is no need to use the PHS 7 or the heat conducting member 10. Therefore, when a plurality of chips are mounted on one multilayer wiring board 2, it is necessary to select an optimal configuration thermally and cost-effectively from the physical property values and heat generation values of the semiconductor substrate constituting the chip. Can be. Assuming that the thickness of the semiconductor element 16 is t1 as it is, the thickness of 17 is t9, and the thickness of the circuit component 12 excluding the chip resistor formed by the microstrip line is t8, ,
t 1 < t 8、 かつ t 1 < t 9  t 1 <t 8 and t 1 <t 9
の関係が成立する。 t 8と t 9の関係は特に限定する必要はない。  Is established. The relationship between t8 and t9 does not need to be particularly limited.
なお、 配線基板裏面 2 bの配線要素 5については、 複数の半導体素子 1 6、 1 7に対して共通の回路を形成するよう構成されても、 それぞれが短絡しないよう 構成されていても、 半導体装置全体の機能が確保できるのであれば特に問題はな い。  Regarding the wiring element 5 on the rear surface 2b of the wiring board, the semiconductor element 16 or 17 may be configured to form a common circuit or may not be short-circuited. There is no particular problem as long as the functions of the entire device can be secured.
図 8 bにおいては、 半導体素子 1 7がフェースダウンして実装 （フリップチッ プ実装） された場合を示す。 この場合、 半導体素子 1 7への入出力信号等は多層 配線基板 2内部のスルーホール 1 1 0と配線層 1 1 1を介して半導体素子 1 7へ 供給、 もしくは半導体素子 1 7から出力される。 半導体素子表層の回路網と多層 配線基板 2との間はハンダバンプ 1 1 2等を介して C C B接続される。 図 8 bに 示した断面図では、 各発熱要素 1 7 bの G N Dがハンダバンプ 1 1 2を介してサ 一マルビア 3に直結される。 即ち、 ハンダバンプ 1 1 2は図 1における本発明の 一実施形態での熱伝導部材 4の役割を果たす。 このため、 発熱要素 1 7 bから放 出された熱が効果的にサーマルビア 3に伝達され、 発熱要素 1 7 bから多層配線 基板裏面 2 bまでの熱抵抗を低減することが可能である。  FIG. 8B shows a case where the semiconductor element 17 is mounted face-down (flip-chip mounting). In this case, input / output signals to / from the semiconductor element 17 are supplied to the semiconductor element 17 via the through-holes 110 in the multilayer wiring board 2 and the wiring layer 111, or are output from the semiconductor element 17 . A CCB connection is made between the circuit network on the surface layer of the semiconductor element and the multilayer wiring board 2 via solder bumps 112 and the like. In the sectional view shown in FIG. 8B, the GND of each heating element 17b is directly connected to the thermal via 3 via the solder bumps 112. That is, the solder bumps 112 serve as the heat conducting member 4 in the embodiment of the present invention in FIG. Therefore, the heat released from the heating element 17b is effectively transmitted to the thermal via 3, and the thermal resistance from the heating element 17b to the rear surface 2b of the multilayer wiring board can be reduced.
図 8 a及び 8 bにおいて示した本発明の一実施形態においては、 多層配線基板 裏面 2に形成された配線層 5や電極 1 0 3はそれぞれベタ状配線で、 これらとマ ザ一ボ一ド 8上に形成された配線層 1 0 2、 1 0 5との間を第 3のロウ材 1 0 6 により接合させているが、 この多層配線基板裏面 2 bの下に球状のハンダ等の口 ゥ材 1 1 3を格子状にならべてマザ一ボード 8と接合させる、 いわゆる B G A接 合により実装させる場合も本発明の一実施形態に含む。 図 8 cは上記ような実装 をした場合を示した断面図であるが、 半導体素子 1 7がフリップチップ実装され ていてもいなくてももちろん構わない。 In the embodiment of the present invention shown in FIGS. 8A and 8B, the wiring layers 5 and the electrodes 103 formed on the back surface 2 of the multilayer wiring board are solid wirings, respectively, The third brazing material 106 is used to join the wiring layers 102 and 105 formed on the upper surface 8 with a third brazing material 106. One embodiment of the present invention also includes a case where the members 113 are arranged in a grid and joined to the motherboard 8, that is, mounted by so-called BGA joining. Figure 8c shows the above implementation FIG. 4 is a cross-sectional view showing a case where the semiconductor device 17 is flip-chip mounted.
図 9は本発明を適用した半導体装置の一部を切り出した斜視図であるが、 半導 体装置全体をキャップ 1◦ 7などで封止、 回路部分を保護した場合、 マザ一ボー ド 8への電気的な接続部分はキャップ 1 0 7のかからない部分の側面及び裏面の みであるから、 例えば裏面にある電極 1 0 3はそれぞれ独立した電極で、 電極 1 0 8はサーマルビア 3と短絡する G N D配線層 5の電極のように、 それぞれ役割 が分担されていればよレ、。  FIG. 9 is a perspective view in which a part of a semiconductor device to which the present invention is applied is cut out. When the entire semiconductor device is sealed with a cap 1◦7 or the like and a circuit portion is protected, the mother board 8 is used. Are electrically connected only on the side and the back of the part that does not cover the cap 107.For example, the electrode 103 on the back is an independent electrode, and the electrode 108 is short-circuited with the thermal via 3. Just like the electrodes of the GND wiring layer 5, the roles should be shared.
図 1 0は図 4または図 8 a及び図 9に示した本発明の一実施形態において用い られる半導体装置のキャップ 1 0 7を取り払った上面図 （図 1 0 a ) 、 半導体素 子素子 1 6を通る断面図 （図 1 0 b ) 、 多層配線基板裏面 2を下から見た底面図 (図 1 0 c ) である。 図 1 0では多層配線基板表層 2 aの一部にしか回路が形成 されていないが、 もちろん全面を有効的に利用して回路が形成されていても本発 明の本質を損なうことはない。  FIG. 10 is a top view (FIG. 10a) of the semiconductor device used in the embodiment of the present invention shown in FIG. 4 or FIG. 8a and FIG. 9 with the cap 107 removed, and FIG. A cross-sectional view (FIG. 10b) passing through FIG. 10 is a bottom view (FIG. 10c) of the rear surface 2 of the multilayer wiring board viewed from below. In FIG. 10, the circuit is formed only on a part of the surface layer 2a of the multilayer wiring board. However, even if the circuit is formed by effectively using the entire surface, the essence of the present invention is not spoiled.
図 1 0 aのように、 回路要素 1 2が表層において孤立しているような場合や配 線層 1 0 1が途中で途切れているような場合、 実際には多層配線基板 2の各層に おいて独立した配線 ·回路網が形成され、 スルーホール等を介して電気的に相互 接続されてモジュール全体として一つの製品を構成している。  As shown in Fig. 10a, when the circuit element 12 is isolated on the surface layer or when the wiring layer 101 is interrupted on the way, actually, Independent wiring and a circuit network are formed, and they are electrically interconnected through through holes and the like to constitute one product as a whole module.
図 1 0 bは多層配線基板裏面 2 bにおける配線パターンの一例を示している力 このようにサーマルビア 3と直結する G N D配線層 5がベタ状の配線であっても、 あるいはハンダボールグリッドアレイ （B G A) 状であってももちろん構わない。 独立した電極 1 0 3はそれぞれ、 信号の入出力用の電極などを構成している。 また、 素子の保護の観点から、 キャップ 1 0 7の内側の空間にはレジン等の保 護部材 1 0 9が充填されている場合がある。  FIG. 10b shows an example of a wiring pattern on the back surface 2b of the multilayer wiring board. Thus, even if the GND wiring layer 5 directly connected to the thermal via 3 is a solid wiring, or a solder ball grid array ( (BGA) form of course. Each of the independent electrodes 103 constitutes a signal input / output electrode or the like. Further, from the viewpoint of protection of the element, the space inside the cap 107 may be filled with a protection member 109 such as resin.
図 4または図 8に示した本発明の一実施形態における半導体装置のモジュール 製造プロセスの一例を図 1 1に示す。  FIG. 11 shows an example of a module manufacturing process of the semiconductor device according to the embodiment of the present invention shown in FIG. 4 or FIG.
図 1 1において、 配線基板 2上の所定の位置に第 1のロウ材 9として高融点の ハンダを印刷もしくは塗布する。 次に、 チップコンデンサや抵抗等の部品 1 2及 ぴ熱伝導部材 1 0を先に第一のロウ材 9を印刷もしくは塗布した位置に搭載し、 リフ口一及び洗浄工程で上記部品 1 2及び熱伝導部材 1 0を実装する。 次に、 導 電性銀ペースト等の第 2のロウ材 1 1を所定の位置に塗布し、 P H S 7を有する 半導体素子 1または 1 6や、 P H S構造 7を用いない半導体素子 1または 1 7を 載せ、 上記第 1のロウ材 9の融点より低く、 かつ第 2のロウ材 1 1を硬化させる のには十分高い温度で第 2のロウ材 1 1をべーク、 洗浄する。 更にワイヤボンデ イング等により半導体素子 1または 1 6または 1 7と配線基板 2の所定の位置を 配線 1 8で接続し、 半導体素子保護のための部材 1 0 9を塗布して固定した後、 キャップ 1 0 7をつける。 更に配線基板 2をそれぞれの単位半導体装置ごとに分 割し、 検査工程で合格した半導体装置を完成品とする。 本工程において、 第 1の ロウ材 9、 第 2のロウ材 1 1、 半導体素子保護のための部材 1 0 9は、 それぞれ 工程順に徐々に融点もしくは硬化温度が低くなるような材料とする。 In FIG. 11, high melting point solder is printed or applied as a first brazing material 9 at a predetermined position on the wiring board 2. Next, components 12 such as a chip capacitor and a resistor and a heat conductive member 10 are mounted on the position where the first brazing material 9 is printed or applied first, The components 12 and the heat conducting member 10 are mounted in the opening of the riff and in the cleaning step. Next, a second brazing material 11 such as a conductive silver paste is applied to a predetermined position, and a semiconductor element 1 or 16 having a PHS 7 or a semiconductor element 1 or 17 having no PHS structure 7 is formed. The second brazing material 11 is baked and washed at a temperature lower than the melting point of the first brazing material 9 and at a temperature high enough to harden the second brazing material 11. Further, the semiconductor element 1 or 16 or 17 and the predetermined position of the wiring board 2 are connected by wiring 18 by wire bonding or the like, and a member 109 for protecting the semiconductor element is applied and fixed, and then the cap 1 is formed. 0 Add 7 Further, the wiring board 2 is divided for each unit semiconductor device, and a semiconductor device that has passed the inspection process is defined as a completed product. In this step, the first brazing material 9, the second brazing material 11, and the member 109 for protecting the semiconductor element are made of a material whose melting point or curing temperature gradually decreases in the order of the steps.
なお、 マザ一ボード 8上へのモジュールの実装は、 次の製造プロセスで実施し ても、 あるはモジュールの状態で顧客に出荷し、 顧客側で実装しても構わない。 この場合、 図 8における第 3のロウ材 1 0 6の融点を T 3と他のロウ材及び保護 部材の融点もしくは硬化温度との大小関係は上述した通りでなければならなレ、。 T 3の値については、 予め指示しておいても、 また、 逆に T 3に合わせて他の T 1や T 2として適当なものを選択しても構わない。  The mounting of the module on the mother board 8 may be performed in the following manufacturing process, or may be shipped to the customer in the state of the module and mounted on the customer side. In this case, the magnitude relationship between the melting point of the third brazing material 106 in FIG. 8 and the melting point or the curing temperature of the other brazing material and the protective member must be as described above. The value of T3 may be designated in advance, or conversely, other appropriate values for T1 and T2 may be selected according to T3.
図 1 2に半導体基板 1または 1 6が G a A s系基板 2 1で、 その上にヘテロバ イポーラトランジスタ （以下、 H B T) を形成した場合の発熱部 1 b周辺の模式 的な断面図を示す。  Fig. 12 is a schematic cross-sectional view of the vicinity of the heating part 1b when the semiconductor substrate 1 or 16 is a GaAs-based substrate 21 and a hetero bipolar transistor (hereinafter, HBT) is formed on it. Show.
図 1 2において、 熱伝導部材 1 0の上に第 2の口ゥ材 1 1、 P H S 7を介して 半絶縁性の G a A s系基板 2 1が実装されている。 G a A s基板 2 1の上にはサ ブコレクタ層 2 2、 コレクタ層 2 3、 ベース層 2 4、 ェミッタ層 2 5、 ベース電 極 2 6、 キャップ層 2 7、 ェミッタ電極 2 8、 コレクタ電極 2 9、 層間絶縁膜 3 0及び 3 1、 ェミッタ配線層 3 2等が形成される。 G a A s系基板 2 1の所定の 位置にはバイァホール 3 3と呼ばれる貫通孔が形成され、 G a A s系基板 2 1裏 面の P H S構造 7とエミッタ配線層 3 2とは、 このバイァホール 3 3内に流入し た P H S 7を介して電気的に接続されている。 また、 ェミッタ配線層 3 2とバイ ァホール 3 3との間の配線の一部には、 バラスト抵抗と呼ばれる抵抗 3 4を配置 する場合がある。 In FIG. 12, a semi-insulating GaAs substrate 21 is mounted on a heat conducting member 10 via a second port material 11 and a PHS 7. On the GaAs substrate 21, sub-collector layer 22, collector layer 23, base layer 24, emitter layer 25, base electrode 26, cap layer 27, emitter electrode 28, collector electrode 29, interlayer insulating films 30 and 31 and emitter wiring layer 32 are formed. A through hole called a via hole 33 is formed at a predetermined position of the GaAs substrate 21, and the PHS structure 7 and the emitter wiring layer 32 on the back surface of the GaAs substrate 21 are connected to the via hole 33. 33 Electrically connected via PHS 7 flowing into 3. In addition, a resistor 34 called a ballast resistor is arranged in a part of the wiring between the emitter wiring layer 32 and the via hole 33. May be.
図 4または図 8に示した発熱部 1 bもしくは 1 6 b、 1 7 bは、 図 12におい ては、 個々のべ一ス 24 ·ェミッタ 25層間を集中的に電流が通過する領域であ る。 ここでは、 図面を簡略化するために、 発熱部領域が 1箇所しかないような構 造で示したが、 実際には複数個の発熱領域があってもよい。 また、 発熱領域の数 とバイァホール 33との数は一致しなくてよレ、。 一般的には、 バイァホール 33 の数の方が発熱領域の数より少ない。  The heat generating portions 1b or 16b and 17b shown in FIG. 4 or FIG. 8 are regions in which current flows intensively between the individual bases 24 and 25 in FIG. . Here, for simplification of the drawing, a structure in which there is only one heat-generating region is shown, but there may actually be a plurality of heat-generating regions. Also, the number of heating regions and the number of via holes 33 do not have to match. Generally, the number of via holes 33 is smaller than the number of heat generating regions.
図 12に示すような構造では、 エミッタ配線 32からバイァホール 33を介し て PHS 7、 更には配線基板 2内のサーマルビア 3の裏面まで電気的に接続され る。 配線基板 2は、 更にマザ一ボードに実装されるが、 この時配線基板 2内のェ ミッタ配線と電気的に接続された配線、 例えば図 10の裏面配線 5、 をマザーボ 一ドの共通 GNDに接地することで、 電位を一定に保つことができる。  In the structure shown in FIG. 12, the emitter wiring 32 is electrically connected to the PHS 7 via the via hole 33 and further to the back surface of the thermal via 3 in the wiring board 2. The wiring board 2 is further mounted on the motherboard.At this time, the wiring electrically connected to the emitter wiring in the wiring board 2, for example, the back wiring 5 in FIG. 10 is connected to the common GND of the motherboard. By grounding, the potential can be kept constant.
図 13に、 図 1 2で示したような G a As系一 HBT素子 1または 16におレ、 て、 上記発熱領域 （フィンガー） 1 9の寸法が幅 2 μπι、 長さ 20 μηι、 本数 1 6 本 X 8列 = 1 28本であった場合の発熱領域のレイァゥト図の一例を示す。  In FIG. 13, the heat generation region (finger) 19 has a width of 2 μπι, a length of 20 μηι, and a number of 1 in the GaAs-based HBT element 1 or 16 as shown in FIG. FIG. 9 shows an example of a layout diagram of a heat generation area when 6 lines × 8 columns = 128 lines.
図 1 3において、 半導体基板 1または 1 6、 及び PHS 7の寸法は、 1辺の長 さが 0. 9mmもしくは 1. 0 mmの正方形、 熱伝導部材 1 0の寸法は辺長が 1. 4 mmもしくは 1. 3 mmの正方形、 もしくは縦 2. 4 mm、 横:！ . 6 mmの長 方形であるとし、 配線基板 2内のサーマルビア 3は個々の直径が 0. 1 5 mmで、 0. 35 mmの縦横等ピッチ間隔で配置されている場合を想定する。 今後図 14 以降で検討する熱伝導部材 10の厚さや材料及び寸法等については、 図 4、 12、 1 3及び上記の基準に基づいて最適化を実施した場合の結果を示す。 なお、 フィ ンガー 1 9の寸法や数は、 発熱領域 1 bと配線基板裏面 2 bの間の熱抵抗の絶対 値には強く影響するが、 熱伝導部材 1 0を用いることによる熱抵抗低減効果の最 適化にはあまり強く影響しないことが熱伝導解析により明らかになつており、 熱 伝導部材 1 0とサーマルビア 3を有する配線基板 2、 及び P H S構造 7の組み合 わせによる熱抵抗低減効果の定性的評価には 1ケースの発熱領域の寸法及び配置 について検討すればほぼ十分である。 なお、 特に断わらない場合、 熱伝導部材 1 0の材質は銅、 PHS構造 7は金メッキ層であるとする。 また、 PHS構造 7の 厚さは、 特に断わらない場合は 1 5 μ πι、 第一のロウ材 9と第二のロウ材 1 1の 熱伝導率は等しく、 その厚さはそれぞれ、 3 Ο μ πιであるとして検討した結果を 示す。 In FIG. 13, the dimensions of the semiconductor substrate 1 or 16 and the PHS 7 are squares each having a side length of 0.9 mm or 1.0 mm, and the dimensions of the heat conductive member 10 are each a side length of 1.4. mm or 1.3 mm square, or 2.4 mm long, horizontal:! It is assumed that each of the thermal vias 3 in the wiring board 2 has a diameter of 0.15 mm and is arranged at an equal pitch of 0.35 mm in the vertical and horizontal directions. For the thickness, material, dimensions, etc. of the heat conducting member 10 to be studied in the future from Fig. 14 onwards, the results when optimization is performed based on Figs. 4, 12, 13 and the above criteria are shown. The size and number of the fingers 19 strongly affect the absolute value of the thermal resistance between the heat generating region 1b and the rear surface 2b of the wiring board. It has been clarified by heat conduction analysis that it does not significantly affect the optimization of the thermal resistance.The effect of reducing the thermal resistance by the combination of the heat conductive member 10 and the wiring board 2 having the thermal vias 3 and the PHS structure 7 For the qualitative evaluation of the above, it is almost enough to consider the dimensions and arrangement of the heat generating area in one case. Unless otherwise specified, the material of the heat conductive member 10 is copper, and the PHS structure 7 is a gold plated layer. Also, PHS structure 7 The thickness was 15 μππ unless otherwise specified, and the thermal conductivity of the first brazing material 9 and the second brazing material 11 were the same, and the thickness was 3 そ れ ぞ れ μππ, respectively. The results are shown.
図 1 4に G a A s系基板 2 1もしくは G a A s系の代りに S i系を用いた場合 について、 定常熱伝導解析を用いて求めた、 熱伝導部材 1 0の厚さと装置全体 (モジュール） 熱抵抗との間の関係を示す。  Figure 14 shows the thickness of the heat-conducting member 10 and the overall device obtained by using steady-state heat conduction analysis for the case where the GaAs substrate 21 or the SiAs system was used instead of the GaAs system. (Module) Indicates the relationship with the thermal resistance.
図 1 4において、 横軸は熱伝導部材 1 0の厚さ、 縦軸はモジュール熱抵抗であ る。 図 1 4によれば、 基板 2 1の厚さによらず、 熱伝導部材 1 0を P H S構造 7 と配線基板 2との間に設置することにより、 モジュール熱抵抗を低減できること、 また、 熱伝導部材 1 0の厚さの最適値は検討範囲内においてはほぼ 3 0 0 μ πι前 後であることがわかる。 S i基板を用いた方がモジュール熱抵抗が小さいのは、 S iの熱伝導率が G a A sの熱伝導率より高いためである。 なお、 G a A s — H B Tを採用するのは、 上記の高周波デバイス用パワーアンプの場合、 出力向上及 び高率改善のためであり、 熱抵抗の問題とは別個の問題である。  In FIG. 14, the horizontal axis represents the thickness of the heat conducting member 10 and the vertical axis represents the module thermal resistance. According to FIG. 14, it is possible to reduce the module thermal resistance by installing the heat conductive member 10 between the PHS structure 7 and the wiring board 2 irrespective of the thickness of the substrate 21. It can be seen that the optimal value of the thickness of the member 10 is about 300 μπι within the range of consideration. The reason for using the Si substrate to have a smaller module thermal resistance is that the thermal conductivity of Si is higher than the thermal conductivity of GaAs. The use of G a As -HBT is for the above-mentioned high-frequency device power amplifier in order to improve the output and the high rate, and is separate from the problem of thermal resistance.
図 1 5に G a A s基板 2 1もしくは半導体素子 1または 1 6、 及び P H S構造 7の寸法と、 熱伝導部材の寸法との組み合わせによりモジュール熱抵抗がどの程 度変化するかを定常熱伝導解析により検討した結果を示す。  Figure 15 shows the steady-state heat conduction to determine how much the module thermal resistance changes due to the combination of the dimensions of the GaAs substrate 21 or semiconductor element 1 or 16 and the PHS structure 7 and the dimensions of the heat conducting member. The results examined by analysis are shown.
図 1 5において、 図 1 4同様、 図の横軸は熱伝導部材 1 0の厚さ、 縦軸はモジ ユール熱抵抗である。 この図から、 半導体素子 1 6のサイズの若干の大小はほと んど熱抵抗に影響せず、 熱伝導部材 1 0のサイズが大きくモジュール熱抵抗に影 響することがわかる。 これは、 配線基板 2内のサーマルビア 3が半導体素子 1 6 の面積よりも広い範囲に配置された場合に、 半導体素子 1 6よりも熱伝導部材 1 0の面積を大きくし、 半導体素子 1 6直下にないサーマルビア 3にも発熱領域 8 で発生した熱を逃がすことのできる構造にすることでモジュール全体の熱抵抗が 低減できることを示す。  In FIG. 15, as in FIG. 14, the horizontal axis of the figure is the thickness of the heat conducting member 10 and the vertical axis is the module thermal resistance. From this figure, it can be seen that the size of the semiconductor element 16 has little or no effect on the thermal resistance, and the size of the heat conductive member 10 is large and affects the module thermal resistance. This is because when the thermal via 3 in the wiring board 2 is arranged in a wider area than the area of the semiconductor element 16, the area of the heat conductive member 10 is made larger than that of the semiconductor element 16, and the semiconductor element 16 This shows that the thermal resistance of the entire module can be reduced by adopting a structure that allows the heat generated in the heat generating area 8 to escape to the thermal via 3 not directly below.
図 1 4及び図 1 5から、 熱伝導部材 1 0の厚さは少なくとも 1 0 0 μ πι程度以 上、 3 0 0 / m程度とし、 また、 その面積は半導体素子 1 6よりも大きく、 なる ベく多くのサーマルビア 3の上にまたがるような寸法とすることにより、 モジュ ール熱抵抗を低減できる。 本発明においても、 熱伝導部材 1 0は上記のような構 造とすることが望ましい。 From FIGS. 14 and 15, the thickness of the heat conducting member 10 is at least about 100 μππ and about 300 / m, and its area is larger than that of the semiconductor element 16. By setting the dimensions so as to extend over as many thermal vias 3 as possible, the module thermal resistance can be reduced. Also in the present invention, the heat conducting member 10 has the above-described structure. It is desirable to make it.
図 1 6に、 熱伝導部材 1 0がなく、 配線基板 2上に第二のロウ材 1 1を用いて 直接半導体素子 1または 1 6を実装した場合の、 PHS構造 7の厚さとモジユー ル熱抵抗の関係を定常熱伝導解析により検討した結果を示す。  Figure 16 shows the thickness and module heat of the PHS structure 7 when the semiconductor element 1 or 16 is directly mounted on the wiring board 2 using the second brazing material 11 without the heat conducting member 10 The result of examining the relationship of resistance by steady heat conduction analysis is shown.
図 1 6において、 横軸は PHS構造 7の厚さ、 縦軸はモジュール熱抵抗である。 図 1 6より、 熱伝導部材 1 0を用いずにそれとほぼ同等の熱抵抗低減を実現する ためには、 PHS構造 7の厚さを 50〜6 0 μπιか、 それ以上にする必要がある ことがわかる。 上記のような厚い金メツキ膜を作るのは工程的にもコスト的にも 困難ではあるが、 条件が許せば上記のような構造を採用しても構わなレ、。  In FIG. 16, the horizontal axis is the thickness of the PHS structure 7, and the vertical axis is the module thermal resistance. According to Fig. 16, the thickness of the PHS structure 7 must be 50 to 60 μπι or more to achieve almost the same reduction in thermal resistance without using the heat conducting member 10. I understand. It is difficult to make a thick gold plating film as described above, both in terms of process and cost. However, if conditions permit, the above structure may be used.
図 1 7に、 PHS構造 7がない場合に熱伝導部材 1 0のみの効果で熱抵抗を低 滅しょうとするとどのような結果になるかを検討した結果を示す。  Figure 17 shows the results of examining the results when trying to reduce the thermal resistance by the effect of only the heat conducting member 10 without the PHS structure 7.
図 1 7において、 横軸は熱伝導部材 1 0の厚さ、 縦軸はモジュール熱抵抗を示 す。 図より、 熱伝導部材 1 0の厚さの最適値は図 1 2や 1 3と同様に 300 μm 前後であるが、 G a A s基板 2 1を用いた場合は PHS構造 7がないと熱抵抗が 十分には小さくならないことがわかる。 従って、 G a A s基板 2 1に対しては P HS構造 7が必須である。 一方、 S i系の基板の場合、 熱伝導部材 1 0の厚さを 最適化すると PHS構造 7があってもなくてもモジュール熱抵抗はほとんど変わ らなレ、。 従って、 図 8や 1 1に示した本発明の一実施形態のように、 S i系の制 御用 I Cに対しては PHS構造 7はなくても特に問題ない。 本発明においては、 G a A s基板のように熱伝導率が 50 W/ (m · K) 程度かそれ以下の基板 2 1を 用いている場合については PHS構造 7を設け、 S i基板のように熱伝導率が 1 48W/ (m - K) 程度かそれ以上の基板を用いている場合は PHS構造 7を設け ないような構成にして構わない。 基板 2 1の熱伝導率が 50前後から 1 48程度 までの場合、 その厚さや発熱量に応じて PHS 7及び熱伝導部材 1 0を用いる力 否かを選択できる。  In FIG. 17, the horizontal axis represents the thickness of the heat conducting member 10 and the vertical axis represents the module thermal resistance. From the figure, the optimum value of the thickness of the heat conducting member 10 is about 300 μm, as in Figs. 12 and 13, but when the GaAs substrate 21 is used, the heat It turns out that the resistance is not small enough. Therefore, the PHS structure 7 is essential for the GaAs substrate 21. On the other hand, in the case of Si-based substrates, if the thickness of the heat conducting member 10 is optimized, the module thermal resistance hardly changes with or without the PHS structure 7. Therefore, as in the embodiment of the present invention shown in FIGS. 8 and 11, there is no particular problem even without the PHS structure 7 for the Si-based control IC. In the present invention, when a substrate 21 having a thermal conductivity of about 50 W / (mK) or less, such as a GaAs substrate, is used, a PHS structure 7 is provided, and a Si substrate is provided. As described above, when a substrate having a thermal conductivity of about 148 W / (m−K) or more is used, a configuration without the PHS structure 7 may be employed. When the thermal conductivity of the substrate 21 is about 50 to about 148, whether or not to use the PHS 7 and the heat conductive member 10 can be selected according to the thickness and the calorific value.
図 1 8に、 熱伝導部材 1 0の材料を銅からアルミニウムまたはモリブデンとし た場合のモジュール熱抵抗と熱伝導部材 1 0の厚さの関係の検討結果を示す。 図 1 8において、 アルミニウムまたはモリブデンは、 それぞれ、 銅より熱伝導 率が低いため、 銅を用いた場合ほどの熱抵抗低減効果を得ることはできないが、 やはり、 厚さが 2 0 0〜 3 0 0 μ πι程度の範囲に厚さの最適値があるとともに、 若干の熱抵抗低減効果を得ることができる。 このこと力、ら、 熱伝導部材 1 0の材 料としては、 半導体基板 2 1と熱伝導率が同等であるか、 あるいはそれよりも高 い材料を選択することが必要である。 できれば銅と同程度以上の熱伝導率をもつ 材料を選択することが望ましレ、。 FIG. 18 shows the results of an examination of the relationship between the module thermal resistance and the thickness of the heat conducting member 10 when the material of the heat conducting member 10 is changed from copper to aluminum or molybdenum. In Figure 18, aluminum and molybdenum have lower thermal conductivity than copper, so they cannot achieve the same thermal resistance reduction effect as copper. Again, the thickness has an optimum value in the range of about 200 to 300 μπι, and a slight thermal resistance reduction effect can be obtained. As a material of the heat conducting member 10, it is necessary to select a material having a heat conductivity equal to or higher than that of the semiconductor substrate 21. If possible, it is desirable to select a material that has a thermal conductivity at least as high as that of copper.
本発明によれば、 半導体基板を厚くすることなく、 半導体素子からの熱を多層 配線基板から外部に効率良く伝達させることが可能な半導体装置を低コストで提 供することができる。  According to the present invention, a semiconductor device capable of efficiently transmitting heat from a semiconductor element to the outside from a multilayer wiring board without increasing the thickness of a semiconductor substrate can be provided at low cost.

Claims

請求の範囲 The scope of the claims
1. 配線基板上に実装される半導体素子と、 前記配線基板内に配置され、 この 配線基板を厚さ方向に貫通して設けられた第 1の熱伝導部材と、 前記半導体素子 と第 1の熱伝導部材とを熱的に接続する第 2の熱伝導部材とを備えた半導体装置。 1. a semiconductor element mounted on a wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction; A second heat conductive member for thermally connecting the heat conductive member to the semiconductor device;
2. 配線基板上に実装される半導体素子と、 前記配線基板内に配置され、 この 配線基板を厚さ方向に貫通して設けられた第 1の熱伝導部材と、 この第 1の熱伝 導部材と前記半導体素子との間に設けられた熱拡散板と、 この熱拡散板と前記第 1の熱伝導部材とを熱的に接続する第 2の熱伝導部材を設けた半導体装置。  2. a semiconductor element mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction; A semiconductor device comprising: a heat diffusion plate provided between a member and the semiconductor element; and a second heat conduction member for thermally connecting the heat diffusion plate and the first heat conduction member.
3. 配線基板上に実装される半導体素子と、 前記配線基板内に配置され、 この 配線基板を厚さ方向に貫通して設けられた第 1の熱伝導部材と、 この第 1の熱伝 導部材と前記半導体素子との間に設けられ、 前記半導体素子の面積以上の面積を 有する熱拡散板と、 この熱拡散板と前記第 1の熱伝導部材とを熱的に接続し、 前 記半導体素子の面積以上の面積を有する第 2の熱伝導部材を設けた半導体装置。  3. a semiconductor element mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction; and a first heat conductive member. A heat diffusion plate provided between the member and the semiconductor element and having an area equal to or larger than the area of the semiconductor element; and thermally connecting the heat diffusion plate and the first heat conductive member; A semiconductor device provided with a second heat conductive member having an area equal to or larger than the area of the element.
4. 請求項 1記載の半導体装置において、 前記半導体素子が S i等の単結晶半 導体基板または G a A s等の化合物半導体基板上に、 複数のトランジスタまたは ダイォード等からなる多フィンガー素子が形成された半導体装置。  4. The semiconductor device according to claim 1, wherein the semiconductor element is a single-crystal semiconductor substrate such as Si or a compound semiconductor substrate such as GaAs, and a multi-finger element including a plurality of transistors or diodes is formed. Semiconductor device.
5. 請求項 1記載の半導体装置において、 前記半導体素子と配線基板との間に 配置される第 2の熱伝導部材は、 上記半導体素子よりも熱伝導率の高い材料であ る半導体装置。  5. The semiconductor device according to claim 1, wherein the second heat conductive member disposed between the semiconductor element and the wiring board is a material having higher thermal conductivity than the semiconductor element.
6. 請求項 2又は 3記載の半導体装置において、 前記半導体素子と配線基板と の間に配置される第 2の熱伝導部材と、 上記半導体素子と第 2の熱伝導部材との 間に配置される熱拡散板のいずれもが上記半導体素子よりも熱伝導率の高い材料 である半導体装置。  6. The semiconductor device according to claim 2, wherein a second heat conductive member disposed between the semiconductor element and the wiring board; and a second heat conductive member disposed between the semiconductor element and the second heat conductive member. A semiconductor device wherein each of the heat diffusion plates is made of a material having a higher thermal conductivity than the semiconductor element.
7. 請求項 3記載の半導体装置において、 前記半導体素子、 第 2の熱伝導部材、 熱拡散板のなかで、 熱拡散板が最も薄く、 第 2の熱伝導部材が最も厚い構成であ る半導体装置。  7. The semiconductor device according to claim 3, wherein the heat diffusion plate is the thinnest and the second heat conduction member is the thickest among the semiconductor element, the second heat conduction member, and the heat diffusion plate. apparatus.
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