JP2845232B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2845232B2
JP2845232B2 JP354397A JP354397A JP2845232B2 JP 2845232 B2 JP2845232 B2 JP 2845232B2 JP 354397 A JP354397 A JP 354397A JP 354397 A JP354397 A JP 354397A JP 2845232 B2 JP2845232 B2 JP 2845232B2
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JP
Japan
Prior art keywords
semiconductor device
chip
substrate
semiconductor
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP354397A
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Japanese (ja)
Other versions
JPH10199900A (en
Inventor
和則 麻埜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
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Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP354397A priority Critical patent/JP2845232B2/en
Publication of JPH10199900A publication Critical patent/JPH10199900A/en
Application granted granted Critical
Publication of JP2845232B2 publication Critical patent/JP2845232B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明はプレーテッドヒート
シンク構造（以下、ＰＨＳ構造と称する）を有する半導
体装置に関し、特に発熱の大きな高出力ＧａＡｓ電界効
果トランジスタ（ＦＥＴ）を備える半導体装置に適用し
て好適な半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plated heat sink structure (hereinafter, referred to as a PHS structure), and more particularly to a semiconductor device having a high-power GaAs field-effect transistor (FET) that generates a large amount of heat. Semiconductor device.

【０００２】[0002]

【従来の技術】一般に、高出力ＧａＡｓＦＥＴは動作時
にチャネル温度が上昇するが、信頼性を確保するために
はパッケージも含めたＦＥＴの熱抵抗を低減し、チヤネ
ル温度の上昇を抑える必要がある。ＦＥＴチップの熱抵
抗低減のためにはＧａＡｓ基板厚を薄くし、その裏面を
ヒートシンクやパッケージに近接させた状態で実装する
ことで、ＧａＡｓ基板の表面側に形成されている素子で
発生した熱を速やかに基板の裏面から放熱させることが
有効である。また、この場合ＦＥＴチップの機槻的強度
を保つために、裏面にＡｕメッキ層等の金属層がが形成
される。このようにして製造された構造をＰＨＳ構造と
称する。2. Description of the Related Art Generally, the channel temperature of a high-power GaAs FET rises during operation, but it is necessary to reduce the thermal resistance of the FET including the package and suppress the rise of the channel temperature in order to ensure reliability. In order to reduce the thermal resistance of the FET chip, the thickness of the GaAs substrate is reduced, and the rear surface is mounted close to a heat sink or package, so that the heat generated by the elements formed on the front surface of the GaAs substrate can be reduced. It is effective to quickly radiate heat from the back surface of the substrate. In this case, a metal layer such as an Au plating layer is formed on the back surface in order to maintain the mechanical strength of the FET chip. The structure manufactured in this way is called a PHS structure.

【０００３】図７に従来のこの種のＰＨＳ構造を有する
高出力ＧａＡｓＦＥＴのＦＥＴチップ２１の平面図とそ
のＢＢ線断面図を示す。ＧａＡｓ基板２２の表面に図示
を省略したＦＥＴ素子が形成されて絶縁膜２３で被覆さ
れており、またこのＧａＡｓ基板２２は裏面側が研磨あ
るいはエッチングされて３０〜５０μｍまで薄化され、
かつこの裏面に１０〜３０μｍの厚さのＡｕメッキ膜２
５が形成されている。そして、図８に示すように、前記
ＦＥＴチップ２１は、パッケージ或いはヒートシンク２
７上に載置され、その裏面側においてＡｕＳｎ合金等の
半田２６によりろう付けされて実装が行われる。FIG. 7 shows a plan view of a conventional high power GaAs FET chip 21 having a PHS structure of this type and a sectional view taken along the line BB. An unillustrated FET element is formed on the surface of the GaAs substrate 22 and covered with an insulating film 23. The GaAs substrate 22 is polished or etched on the back side to be thinned to 30 to 50 μm.
And an Au plating film 2 having a thickness of 10 to 30 μm
5 are formed. Then, as shown in FIG. 8, the FET chip 21 is
7 and is mounted on the back surface by brazing with a solder 26 such as an AuSn alloy.

【０００４】[0004]

【発明が解決しようとする課題】ところで、前記しよう
にＦＥＴチップをパッケージ等に実装する場合には、Ａ
ｕＳｎ合金等の半田を溶融させるのに３００℃以上で加
熱する必要がある。このとき、図８に示したように、Ｇ
ａＡｓ基板２２とＡｕメッキ膜２５の熱膨張係数の差に
よりＦＥＴチップ２１は周辺部が表面側に反り、この周
辺部がパッケージに密着せずに、間隙が生じる。このた
め、この周辺部において半田２６が厚く形成されること
になり、半田層の厚くなったＦＥＴチップ周辺部の熱抵
抗がチップ中心部に比べて上昇する。その結果、動作時
にＦＥＴ素子のチャネル温度が周辺部において局所的に
上昇し、熱暴走や熱的破壊、長期信頼性の低下といった
問題が生じることになる。特に、高出力ＦＥＴでは、ゲ
ート幅をかせぐためにインターディジット構造と呼ばれ
る単位ＦＥＴを並列に配置した構造を採用するが、出力
向上のためにゲート幅を増やすことでチップ横幅が増大
するため、チップ長辺方向の反り量が大きくなり、その
結果両端部での熱抵抗が増大する。When the FET chip is mounted on a package or the like as described above, A
It is necessary to heat at 300 ° C. or more to melt solder such as uSn alloy. At this time, as shown in FIG.
Due to the difference in the thermal expansion coefficient between the aAs substrate 22 and the Au plating film 25, the peripheral portion of the FET chip 21 is warped to the surface side, and the peripheral portion does not adhere to the package, and a gap is generated. For this reason, the solder 26 is formed thicker in this peripheral portion, and the thermal resistance of the peripheral portion of the FET chip having a thicker solder layer is higher than that of the central portion of the chip. As a result, the channel temperature of the FET element locally rises in the peripheral portion during operation, causing problems such as thermal runaway, thermal destruction, and deterioration in long-term reliability. In particular, high-power FETs employ a structure called unitary FETs arranged in parallel in order to gain gate width.However, increasing the gate width to improve output increases the chip width, so the chip length increases. The amount of warpage in the side direction increases, and as a result, the thermal resistance at both ends increases.

【０００５】なお、ＧａＡｓＦＥＴチップの熱抵抗はＧ
ａＡｓ基板、半田層、パッケージのベースのそれぞれの
部分の熱抵抗を足し合わせた値である。単純には素子が
形成されている発熱部から熱流の流れ込む面積および層
の厚さ、各々の材料の熱伝導率で決まる。組立て実装時
に通常用いられるＡｕＳｎ半田は、実装されたＦＥＴを
長時間動作させることによりＳｎが拡散するため熱伝導
率が低下し、半田層部分の熱抵抗が上昇する。The thermal resistance of a GaAs FET chip is G
This is a value obtained by adding the thermal resistances of the respective portions of the aAs substrate, the solder layer, and the package base. Simply, it is determined by the area where the heat flows from the heat generating portion where the element is formed, the thickness of the layer, and the thermal conductivity of each material. AuSn solder, which is usually used at the time of assembly and mounting, operates the mounted FET for a long time to diffuse Sn, so that the thermal conductivity decreases and the thermal resistance of the solder layer increases.

【０００６】このような問題点を解決するために特開昭
６１−２３３５０号公報では、チップ自体を厚く形成す
るとともに、素子部の直下が薄くなるように部分的にエ
ッチングを行い、その部分にＡｕを充填する構造が提案
されている。この構造ではチップ厚を大きくしているた
め、組立て時のチップの反りが低減でき、前記問題点を
回避することができる。しかしながら、素子部の直下を
薄くし、さらに充填するＡｕ層を厚く形成するため、温
度変化を受けた場合等に素子部に加えられる応力が大き
くなり、薄くされた素子部にクラックが生じる等の問題
が新たに発生することになり、チップの信頼性を低下さ
せる要因となる。In order to solve such a problem, Japanese Patent Application Laid-Open No. 61-23350 discloses a method in which a chip itself is formed to be thick and partially etched so that a portion immediately below an element portion is thinned. A structure for filling with Au has been proposed. In this structure, since the chip thickness is increased, the warpage of the chip at the time of assembly can be reduced, and the above problem can be avoided. However, since the thickness directly under the element portion is made thinner and the Au layer to be filled is formed thicker, the stress applied to the element portion becomes large when a temperature change occurs, and cracks occur in the thinned element portion. A new problem arises, which causes a reduction in chip reliability.

【０００７】本発明の目的は、チップにおける反りが発
生した場合でも、チップ周辺部での熱抵抗の増加を抑制
し、チップにおける熱抵抗の均一化を図った信頼性の高
い半導体装置を提供することにある。An object of the present invention is to provide a highly reliable semiconductor device which suppresses an increase in thermal resistance in a peripheral portion of a chip even when a warp occurs in the chip and makes the thermal resistance in the chip uniform. It is in.

【０００８】[0008]

【課題を解決するための手段】本発明は、表面に半導体
素子が形成された半導体基板の裏面に、比較的に厚く金
属膜が形成されているＰＨＳ構造を有する半導体装置に
おいて、半導体素子が形成されている領域の一部を含む
半導体基板の周辺部の基板厚が中央部に比べて薄く形成
されていることを特徴とする。半導体素子は、例えば単
位ＦＥＴを並列に配置したインターディジット構造とし
て構成され、半導体基板はこの単位ＦＥＴの配列方向の
両端部の基板厚が中央部に比べて薄く形成される。ここ
で、半導体基板の周辺部の基板厚さは、中央部の基板厚
さの５０〜７０％程度に設定され、また基板厚さが薄く
された半導体基板の周辺部は、中央部に対して１／３〜
１／５の長さ範囲であることが好ましい。SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device having a PHS structure in which a relatively thick metal film is formed on the back surface of a semiconductor substrate having a semiconductor element formed on the surface. The semiconductor substrate is characterized in that the thickness of the peripheral portion of the semiconductor substrate including a part of the region is thinner than the central portion. The semiconductor element has, for example, an interdigit structure in which unit FETs are arranged in parallel, and the semiconductor substrate is formed such that the substrate thickness at both ends in the arrangement direction of the unit FETs is smaller than that at the center. Here, the substrate thickness at the peripheral portion of the semiconductor substrate is set to about 50 to 70% of the substrate thickness at the central portion, and the peripheral portion of the semiconductor substrate having the reduced substrate thickness is more than the central portion. 1/3 ~
It is preferably in the range of 1/5 length.

【０００９】[0009]

【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１は本発明を高出力ＧａＡｓＦＥ
ＴのＦＥＴチップに適用した実施形態であり、（ａ）は
平面図、（ｂ）はＡＡ線断面図である。ＦＥＴチップ１
を構成するＧａＡｓ基板２の表面には、ソース電極Ｓ、
ゲート電極Ｇ、ドレイン電極Ｄを備える複数個のＦＥＴ
が形成されている。ここで、出力を向上させるのにゲー
ト幅を大きくする必要があるため、基本ＦＥＴ構造とし
て単位ＦＥＴが複数個並列に構成された櫛形ゲート構造
と称する構造が用いられている。この場合、単位ＦＥＴ
のフィンガ長を一定とした場合、その本数によってゲー
ト幅が決まるため、通常１チップ内に数１０から数１０
０本の単位ＦＥＴを並べるが、それに伴いチップ横幅が
増大し、図示のように一方向（幅方向）に長い矩形状に
形成される。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a high-power GaAsFE of the present invention.
In this embodiment, the present invention is applied to a T FET chip, where (a) is a plan view and (b) is a cross-sectional view taken along line AA. FET chip 1
The source electrode S,
A plurality of FETs having a gate electrode G and a drain electrode D
Are formed. Here, since it is necessary to increase the gate width to improve the output, a structure called a comb gate structure in which a plurality of unit FETs are arranged in parallel is used as a basic FET structure. In this case, the unit FET
When the finger length is constant, the gate width is determined by the number of fingers.
Although zero unit FETs are arranged, the lateral width of the chip increases accordingly, and the unit FETs are formed in a rectangular shape that is long in one direction (width direction) as illustrated.

【００１０】前記ＦＥＴチップ１のＧａＡｓ基板２は３
０〜５０μｍ程度の厚さとして形成されているが、その
裏面において、前記幅方向の両端部２ａが、幅方向の長
さの１／３〜１／５の長さの領域にわたって削成され、
これら両端部２ａの厚さが１０〜３０μｍ程度にまで低
減されている。これにより、この両端部２ａの厚さは、
中央部２ｂの厚さに比べて５０〜７０％の厚さとなって
いる。そして、ＧａＡｓ基板の裏面の全面に薄いＴｉ／
Ａｕ膜４が形成され、さらにその表面にメッキ法により
厚さ１０〜３０μｍのＡｕメッキ膜４が形成されてい
る。なお、ＧａＡｓ基板２の表面には、前記ＦＥＴを被
覆するための絶縁膜３が形成されており、この実施形態
ではこの絶縁膜３はチップ１の周辺部には存在しない構
成とされている。The GaAs substrate 2 of the FET chip 1 is 3
Although it is formed as a thickness of about 0 to 50 μm, on the back surface, both ends 2 a in the width direction are cut over a region of １ ／ to １ ／ of the length in the width direction,
The thickness of both ends 2a is reduced to about 10 to 30 μm. Thereby, the thickness of the both ends 2a is
The thickness is 50 to 70% of the thickness of the central portion 2b. Then, a thin Ti /
An Au film 4 is formed, and an Au plating film 4 having a thickness of 10 to 30 μm is formed on the surface thereof by a plating method. An insulating film 3 for covering the FET is formed on the surface of the GaAs substrate 2. In this embodiment, the insulating film 3 does not exist in the periphery of the chip 1.

【００１１】図２及び図３は図１に示したＦＥＴチップ
１の製造方法を工程順に示す断面図である。先ず、図２
（ａ）のように、ＧａＡｓ基板２、ここではＧａＡｓウ
ェハ表面に図１に示したようなＦＥＴ素子を形成し、こ
れらＦＥＴ素子形成領域を絶縁膜３で被覆した後、この
ＧａＡｓウェハ２の表面を下側に向けてワックス等の接
着剤１１でガラス板１２に貼り付ける。この状態でＧａ
Ａｓウェハ２の裏面を研磨することによりＧａＡｓウェ
ハを薄化する。さらに硫酸、過酸化水素水あるいは燐
酸、過酸化水素水混合液などのエッチング液を用いてＧ
ａＡｓエッチングを行い、最終的に３０〜５０μｍまで
薄くする。次に、図２（ｂ）に示すように、チップ部分
を覆うようにフォトレジスト１３を形成し、前記エッチ
ング液を用いるか、あるいは塩素系のガスを使用した反
応性イオンエッチング（ＲＩＥ）を用いることでチップ
間の領域をエッチングして除去し、個々のチップに分離
する。2 and 3 are sectional views showing a method of manufacturing the FET chip 1 shown in FIG. 1 in the order of steps. First, FIG.
1A, an FET element as shown in FIG. 1 is formed on the surface of a GaAs substrate 2, here, a GaAs wafer, and these FET element formation regions are covered with an insulating film 3; Is attached to the glass plate 12 with an adhesive 11 such as wax with the lower side facing down. In this state, Ga
The GaAs wafer is thinned by polishing the back surface of the As wafer 2. Further, using an etching solution such as sulfuric acid, hydrogen peroxide or a mixture of phosphoric acid and hydrogen peroxide, G
Perform aAs etching, and finally reduce the thickness to 30 to 50 μm. Next, as shown in FIG. 2B, a photoresist 13 is formed so as to cover the chip portion, and the above-mentioned etching solution or reactive ion etching (RIE) using a chlorine-based gas is used. As a result, the region between the chips is removed by etching, and separated into individual chips.

【００１２】さらに、図２（ｃ）に示すように、チップ
の幅方向の中央部の２／３〜４／５の領域をフォトレジ
スト１４で覆い、前記したと同様の反応性イオンエッチ
ングを用いてチップ両端部２ａを１０〜２０μｍ程度エ
ッチングし、両端部２ａをさらに薄く形成する。次に、
図３（ａ）のように、前記フォトレジストを除去した
後、メッキ下地層として全面にスバッタ法によりＴｉ／
Ａｕ膜４を被着させる。ここでＴｉおよびＡｕの膜厚と
して、たとえばＴｉ（１０００Å）／Ａｕ（１０００
Å）を用いる。次いで、チップ分離領域を保護するよう
にフォトレジスト１５を形成した後、電解メッキ法を用
いてチップ裏面領域にＡｕ膜５を１０〜２０μｍの厚さ
に形成する。その後、図３（ｂ）のように、フォトレジ
ストを除去し、Ａｕメッキされた領域以外のＴｉ／Ａｕ
膜４をイオンミリング法によりエッチング除去する。さ
らに、ＧａＡｓウェハを貼り付けたガラス板１２からチ
ップを剥がすことにより、ＦＥＴチップが完成する。Further, as shown in FIG. 2C, a 2/3 to 4/5 region at the center in the width direction of the chip is covered with a photoresist 14, and the same reactive ion etching as described above is used. Then, both ends 2a of the chip are etched by about 10 to 20 μm to form both ends 2a even thinner. next,
As shown in FIG. 3A, after removing the photoresist, Ti / Ti is formed on the entire surface by a sputtering method as a plating underlayer.
An Au film 4 is deposited. Here, as the film thickness of Ti and Au, for example, Ti (1000 °) / Au (1000
Use Å). Next, after a photoresist 15 is formed so as to protect the chip separation region, an Au film 5 is formed to a thickness of 10 to 20 μm on the chip back surface region by using an electrolytic plating method. Thereafter, as shown in FIG. 3B, the photoresist is removed, and Ti / Au other than the Au-plated region is removed.
The film 4 is removed by etching by an ion milling method. Furthermore, the FET chip is completed by peeling the chip from the glass plate 12 to which the GaAs wafer is attached.

【００１３】このように形成されたＦＥＴチップは、図
４に示すように、ＡｕＳｎ半田１６を用いてパッケージ
１７にマウントされる。このとき、ＦＥＴチップの裏面
のＡｕメッキ膜５をパッケージ１７に接触させた状態で
半田付けを行う。このため、この半田付け時の加熱によ
り、ＧａＡｓ基板２とＡｕメッキ膜５との熱膨張率の違
いに基づく反りが発生し、チップ１の両端部２ａが上方
向に湾曲される。The FET chip thus formed is mounted on a package 17 using AuSn solder 16, as shown in FIG. At this time, soldering is performed with the Au plating film 5 on the back surface of the FET chip in contact with the package 17. Therefore, due to the heating at the time of the soldering, warpage occurs based on the difference in the coefficient of thermal expansion between the GaAs substrate 2 and the Au plating film 5, and both ends 2a of the chip 1 are curved upward.

【００１４】そして、マウントされたＦＥＴチップのＦ
ＥＴ素子に通電してＦＥＴを動作させた場合、印加され
たＤＣ電力のうち一部は出力電力になるが、大部分は熱
として消費され、ＦＥＴ形成領域において発熱が生じ
る。図５は図１に示した本発明のＦＥＴチップと、図７
に示した従来のＦＥＴチップをそれぞれパッケージにマ
ウントした状態におけるチップ長辺方向のチャネル温度
分布を示す。ここでＤＣバイアスはたとえばドレイン電
圧１０Ｖ，ドレイン電流５Ａの場合を示す。図５に示す
ように、従来のチップではチップ両端部のチャネル温度
が増加しているのに対して、本発明のチップでは両端部
のチャネル温度の上昇は抑制されており、均一な温度分
布となっている。このことから、本発明の構成では、チ
ップ周辺部での熱抵抗の増加が抑制され、チップにおけ
る熱抵抗の均一化を図った信頼性の高い半導体装置が得
られることになる。Then, the F of the mounted FET chip is
When the FET is operated by energizing the ET element, part of the applied DC power becomes output power, but most is consumed as heat, and heat is generated in the FET formation region. FIG. 5 shows the FET chip of the present invention shown in FIG.
3 shows a channel temperature distribution in the long-side direction of the chip when the conventional FET chips shown in FIG. Here, the DC bias indicates a case where the drain voltage is 10 V and the drain current is 5 A, for example. As shown in FIG. 5, in the conventional chip, the channel temperature at both ends of the chip is increased, whereas in the chip of the present invention, the increase in the channel temperature at both ends is suppressed. Has become. From this, in the configuration of the present invention, an increase in thermal resistance in the peripheral portion of the chip is suppressed, and a highly reliable semiconductor device with uniform thermal resistance in the chip can be obtained.

【００１５】図６は本発明の第２の実施形態のＦＥＴチ
ップの断面図である。この実施形態では、同図に示され
るように、ＦＥＴチップ１Ａの両端部２ａは、ＧａＡｓ
基板２Ａの裏面側においてテーバー状に削成され、中央
部２ｂに対して徐々に厚さが低減された構成とされてい
る。そして、このＧａＡｓ基板２Ａの裏面にはＡｕメッ
キ膜５が形成されている。この構成によっても、ＦＥＴ
チップの両端部の厚さが低減されていることで、ＦＥＴ
チップをマウントしたときに生じる反りによって両端部
での半田の厚さが増大された場合でも、両端部を含めた
ＦＥＴチップ全体のチャネル温度分布の均一化が実現で
きる。FIG. 6 is a sectional view of an FET chip according to a second embodiment of the present invention. In this embodiment, both ends 2a of the FET chip 1A are made of GaAs, as shown in FIG.
The back surface of the substrate 2A is cut into a taber shape, and the thickness is gradually reduced with respect to the central portion 2b. An Au plating film 5 is formed on the back surface of the GaAs substrate 2A. With this configuration, the FET
By reducing the thickness of both ends of the chip, FET
Even when the thickness of the solder at both ends is increased due to warpage generated when the chip is mounted, the channel temperature distribution of the entire FET chip including both ends can be made uniform.

【００１６】ここで、前記各実施形態では、ＦＥＴチッ
プに複数個のＦＥＴが一方向に配列されている例を示し
ているが、複数個のＦＥＴが一方向およびこれと直交す
る方向のそれぞれに配列されている場合には、ＦＥＴチ
ップの周辺部において半導体基板の厚さを薄くするよう
に構成する。Here, in each of the above embodiments, an example is shown in which a plurality of FETs are arranged in one direction on the FET chip. However, the plurality of FETs are arranged in one direction and in a direction orthogonal thereto. When arranged, the thickness of the semiconductor substrate is reduced at the periphery of the FET chip.

【００１７】なお、特開平６−１７７１７８号公報に
は、本発明と同様に半導体チップの裏面の周縁部を切欠
いた上で、半田により基板にマウントする構造が開示さ
れているが、この公報の技術は、半導体チップの裏面に
メッキ膜が比較的厚く形成されているＰＨＳ構造の半導
体装置ではなく、しかも半導体チップに生じる反りが要
因とされる熱抵抗の均一化を図るものではなく、この点
で本発明とは実質的な構成が相違している。また、公報
の技術は、本発明のように、複数の素子の配列方向の両
端部を薄く形成して熱抵抗の均一化を図ることで、複数
の素子の特性の均一化を図ることを示唆するものではな
い。Japanese Patent Application Laid-Open No. 6-177178 discloses a structure in which a peripheral portion of the back surface of a semiconductor chip is cut out and mounted on a substrate by soldering as in the present invention. The technology is not a semiconductor device having a PHS structure in which a plating film is formed relatively thickly on the back surface of the semiconductor chip, and furthermore, it is not intended to make the thermal resistance uniform due to the warpage generated in the semiconductor chip. Therefore, the actual configuration is different from the present invention. In addition, the technique disclosed in the publication suggests that the characteristics of a plurality of elements are made uniform by forming both ends in the arrangement direction of the plurality of elements thinner to make the thermal resistance uniform, as in the present invention. It does not do.

【００１８】[0018]

【発明の効果】以上説明したように本発明は、ＰＨＳ構
造を有する半導体装置において、半導体素子が形成され
ている領域の一部を含む半導体基板の周辺部の基板厚が
中央部に比べて薄く形成されているので、マウントされ
た半導体装置に反りが発生した場合でも、周辺部の熱抵
抗を中央部と同程度に低減することが可能となり、半導
体装置の全体の熱抵抗を均一化して均一な素子温度分布
を保つことが可能となる。これにより、高出力のＧａＡ
ｓＦＥＴにおいても十分な信頼性のある半導体装置を得
ることが可能となる。As described above, according to the present invention, in a semiconductor device having a PHS structure, the thickness of a peripheral portion of a semiconductor substrate including a part of a region where a semiconductor element is formed is smaller than that of a central portion. As a result, even if the mounted semiconductor device is warped, the thermal resistance at the peripheral portion can be reduced to the same level as the central portion, and the overall thermal resistance of the semiconductor device can be made uniform. Element temperature distribution can be maintained. Thereby, high output GaAs
It is possible to obtain a sufficiently reliable semiconductor device even for an sFET.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施形態の半導体装置の平面図と
ＡＡ線断面図である。FIG. 1 is a plan view and a cross-sectional view taken along line AA of a semiconductor device according to a first embodiment of the present invention.

【図２】図１の半導体装置の製造方法を工程順に示す断
面図のその１である。FIG. 2 is a first sectional view showing the method of manufacturing the semiconductor device in FIG. 1 in the order of steps;

【図３】図１の半導体装置の製造方法を工程順に示す断
面図のその２である。FIG. 3 is a second sectional view illustrating the method of manufacturing the semiconductor device in FIG. 1 in the order of steps;

【図４】図１の半導体装置をマウントした状態を示す断
面図である。FIG. 4 is a sectional view showing a state where the semiconductor device of FIG. 1 is mounted.

【図５】従来と本発明の各半導体装置におけるチャネル
温度分布を比較して示す図である。FIG. 5 is a diagram showing a comparison between channel temperature distributions in a conventional semiconductor device and each semiconductor device of the present invention.

【図６】本発明の第２の実施形態の断面図である。FIG. 6 is a cross-sectional view of a second embodiment of the present invention.

【図７】従来の半導体装置の一例の平面図とＢＢ線断面
図である。FIG. 7 is a plan view and a cross-sectional view taken along line BB of an example of a conventional semiconductor device.

【図８】図７の半導体装置をマウントした状態の断面図
である。8 is a sectional view of a state where the semiconductor device of FIG. 7 is mounted.

【符号の説明】[Explanation of symbols]

１，１Ａ ＦＥＴチップ ２，２Ａ ＧａＡｓ基板 ２ａ 両端部 ２ｂ 中央部 ３ 絶縁膜 ４ Ｔｉ／Ａｕ膜 ５ Ａｕメッキ膜 1, 1A FET chip 2, 2A GaAs substrate 2a Both ends 2b Central part 3 Insulating film 4 Ti / Au film 5 Au plating film

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 表面に半導体素子が形成された半導体基
板の裏面に、比較的に厚く金属膜が形成されているプレ
ーテッドヒートシンク構造を有する半導体装置におい
て、前記半導体素子が形成されている領域の一部を含む
半導体基板の周辺部の基板厚が中央部に比べて薄く形成
されていることを特徴とする半導体装置。In a semiconductor device having a plated heat sink structure in which a relatively thick metal film is formed on a back surface of a semiconductor substrate having a semiconductor element formed on a front surface, a region where the semiconductor element is formed is provided. A semiconductor device characterized in that the thickness of a peripheral portion of a semiconductor substrate including a part thereof is formed thinner than that of a central portion. 【請求項２】 半導体素子は、単位ＦＥＴを並列に配置
したインターディジット構造として構成され、前記半導
体基板はこの単位ＦＥＴの配列方向の両端部の基板厚が
中央部に比べて薄く形成されている請求項１の半導体装
置。2. The semiconductor element is configured as an interdigit structure in which unit FETs are arranged in parallel, and the semiconductor substrate is formed such that the substrate thickness at both ends in the arrangement direction of the unit FETs is smaller than that at the center. The semiconductor device according to claim 1. 【請求項３】 半導体基板の周辺部の基板厚さは、中央
部の基板厚さの５０〜７０％程度に設定されてなる請求
項１または２の半導体装置。3. The semiconductor device according to claim 1, wherein a substrate thickness at a peripheral portion of the semiconductor substrate is set to about 50 to 70% of a substrate thickness at a central portion. 【請求項４】 基板厚さが薄くされた半導体基板の周辺
部は、中央部に対して１／３〜１／５の長さ範囲である
請求項３の半導体装置。4. The semiconductor device according to claim 3, wherein a peripheral portion of the semiconductor substrate having a reduced substrate thickness has a length in a range of ３ to ５ of a central portion. 【請求項５】 半導体基板はＧａＡｓ基板であり、この
ＧａＡｓ基板の裏面の金属膜はＡｕメッキ膜である請求
項１ないし４のいずれかの半導体装置。5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a GaAs substrate, and the metal film on the back surface of the GaAs substrate is an Au plating film. 【請求項６】 半導体装置は、裏面において金属膜に対
して濡れ性のある金属ろう材によりパッケージまたはヒ
ートシンクにマウントされる請求項５の半導体装置。6. The semiconductor device according to claim 5, wherein the semiconductor device is mounted on a package or a heat sink with a brazing metal having wettability to a metal film on a back surface.
JP354397A 1997-01-13 1997-01-13 Semiconductor device Expired - Fee Related JP2845232B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP354397A JP2845232B2 (en) 1997-01-13 1997-01-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP354397A JP2845232B2 (en) 1997-01-13 1997-01-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH10199900A JPH10199900A (en) 1998-07-31
JP2845232B2 true JP2845232B2 (en) 1999-01-13

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JP (1) JP2845232B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4480818B2 (en) * 1999-09-30 2010-06-16 株式会社ルネサステクノロジ Semiconductor device
DE10106836B4 (en) 2001-02-14 2009-01-22 Infineon Technologies Ag Integrated circuit arrangement of a flat substrate
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