JP2868008B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

Kind Code: A1 Abstract: When heating a semiconductor device into a package or the like, it is possible to prevent a crack originating from a through hole formed in a semiconductor substrate from occurring, and as a result, electrical characteristics are obtained. Semiconductor device capable of preventing deterioration of reliability and reliability, and a method of manufacturing the same. SOLUTION: An element portion 5 is provided on a front surface side of a semiconductor substrate 1, a through hole 6 is formed at a position corresponding to a ground electrode 3 of the element portion 5 of the semiconductor substrate 1, and a semiconductor substrate 1 is provided on a back surface side of the semiconductor substrate 1. And a metal layer 8 connected to the ground electrode 3 through the through-hole 6 is provided, and a stress buffer layer 21 is provided between the semiconductor substrate 1 and the metal layer 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a plated heat sink (PHS) structure and a via hole structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 12 is a cross-sectional view showing a conventional semiconductor device, and has a PHS structure and a via hole structure.
This is an example of a semiconductor chip on which an As field effect transistor (hereinafter abbreviated as GaAsFET) is formed. This F
In the ET chip, an FET element (element section) 5 having a gate electrode 2, a source electrode (ground electrode) 3 and a drain electrode 4 is formed on a surface of a GaAs substrate (semiconductor substrate) 1. Via holes (through holes) 6 penetrating the GaAs substrate 1 are formed in portions corresponding to the electrodes 3.

A metal layer serving as a conductive path for Au plating, for example, a Ti—Au layer 7 is formed on the entire back surface of the GaAs substrate 1 including the inner surface of the via hole 6, and a PHS is formed on the Ti—Au layer 7. An Au layer 8 is formed, and further, for example, a Ti layer 9 is formed as a barrier metal in and around the via hole 6. Ti layer 9
Is formed in order to prevent the diffusion of Sn from the solder (solder) in the via hole 6 which causes the deterioration of the FET characteristics, and may not be formed when not particularly required.

Next, a method of manufacturing the GaAs FET chip will be described with reference to FIG. First, FIG.
As shown in FIG. 1A, a gate electrode 2, a source electrode 3, and a gate electrode 2 are formed on the surface of a GaAs substrate 1 by various conventional process techniques.
After the drain electrode 4 and the like are sequentially formed and the FET element 5 is manufactured, the back surface side of the GaAs substrate 1 is thinned to 50 μm by polishing and etching, and a resist pattern is formed on the back surface of the GaAs substrate 1 by a normal lithography technique. 1
Form one.

[0005] Next, as shown in FIG.
In a portion of the s substrate 1 corresponding to the source electrode 3, a via hole 6 penetrating the substrate 1 is formed from the back surface of the substrate 1 by a normal etching technique. Next, as shown in FIG. 3C, the Ti—Au layers 7 are each
It is formed on the entire back surface including the inside of the via hole 6 by sputtering or vapor deposition so as to have a thickness of 0 nm.
An Au layer 8 is formed by electrolytic plating so as to have a thickness of 15 μm.

Although not shown here, at this time, in order to easily perform pelletization (pelletization) in a post-process,
In many cases, a mask pattern made of a photoresist is formed on the scribe line, the Au is plated and then removed, and the plating path is etched by ion milling or the like using the plated Au as a mask. If necessary, as shown in FIG. 3D, a Ti layer 9 having a thickness of 300 nm, for example, is formed as a barrier metal by sputtering or vapor deposition, and the inside of the via hole 6 is formed by ordinary lithography, etching, or the like. And its peripheral part.

Japanese Patent Application Laid-Open No. 4-144157 discloses a high-frequency high-power semiconductor device in which warpage of a chip due to stress is suppressed. This semiconductor device is composed of GaAs
An element portion such as an FET is formed in a surface region of a semiconductor substrate such as s. A plated Au layer is formed as a PHS in an element portion region of the semiconductor substrate including via holes, and the line is formed in a region other than the element portion. A plating layer having an expansion coefficient equal to that of the semiconductor substrate and different from the plated Au layer is formed. As this plating layer, for example, Au-S
_{i, C, SiO, SiO 2} , SiC, Si 3 N 4, Cu and Ni-Si, dispersion plating layer C, etc., or Mo,
Laminated plating of W, WSi and Ni is used.

[0008]

The conventional FE
In the T chip, when this FET chip is incorporated in a package, it is necessary to heat it to the melting point of the solder or more.
For example, when AuSn is used as the solder, the temperature reaches 280 ° C. Therefore, GaAs [linear expansion coefficient: 5.9 × 10 ⁻⁶ (/ K), Young's modulus: 85.
5 × 10 ⁹ (N / m ² )] and Au [linear expansion coefficient: 14.2]
× 10 ⁻⁶ (/ K), Young's modulus: 80 × 10 ⁹ (N /
m ² )] due to the difference in the coefficient of linear expansion.
As shown in FIG. 14, there is a problem that cracks 13 often occur starting from via holes 6 having a structure in which stress concentration is likely to occur.

In a conventional high-frequency high-power semiconductor device, chip warpage is reduced because stress is suppressed in a region other than an element portion such as an FET, but the structure of GaAs and Au around a via hole is reduced. However, there is a problem that the concentration of the stress applied to the via hole is not eased because it is not different from the conventional one.

Also, since the via hole has a structure that is opened from the front surface side of the substrate and is connected to the back surface by applying a metal, the element portion such as an FET on the surface of the substrate is masked with a resist or the like to be long. It is necessary to perform time etching. In this case, if the masking property of the resist or the like is not sufficient, the element portion is damaged, and the electrical characteristics of the FET or the like fluctuate. Also, it is necessary to open a via hole before polishing the semiconductor substrate. When the depth of the via hole varies, there is a problem that a via hole that cannot be connected to the PHS occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and cracks are generated from a through hole formed in a semiconductor substrate as a starting point when heating a semiconductor device into a package or the like. Can be prevented
As a result, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can prevent deterioration of electrical characteristics and reliability.

[0012]

In order to solve the above-mentioned problems, the present invention provides the following semiconductor device and a method of manufacturing the same. That is, in the semiconductor device of the present invention, an element portion is provided on a front surface side of a semiconductor substrate, a through hole is formed at a position corresponding to a ground electrode of the element portion on the semiconductor substrate, and the semiconductor device is formed on a back surface side of the semiconductor substrate. A semiconductor device provided with a metal layer for radiating heat generated in the substrate and connecting to the ground electrode through the through hole, wherein a stress buffer layer is provided between the semiconductor substrate and the metal layer.

[0013] The stress buffer layer may be provided on the entire back surface including the inner surface of the through hole of the semiconductor substrate. Further, the stress buffer layer may be provided only in a peripheral portion of the through hole.
Further, the stress buffer layer may be provided on an inner surface of the through hole of the semiconductor substrate and a peripheral portion thereof. Further, the stress buffer layer may be embedded in a through hole of the semiconductor substrate.

In the method of manufacturing a semiconductor device according to the present invention, an element portion is formed on a front surface of a semiconductor substrate, and a through hole is formed from a back surface of the semiconductor substrate at a position corresponding to a ground electrode of the element portion. And forming a metal layer connected to the ground electrode through the through hole on the back side of the semiconductor substrate, by dissipating heat generated in the semiconductor substrate, and forming the through hole. The method is provided with a step of forming a stress buffer layer on the back surface side of the semiconductor substrate later.

In the semiconductor device of the present invention, the stress buffer layer is provided between the semiconductor substrate and the metal layer, so that the semiconductor device can be heated at the time of assembling the semiconductor device into a package or the like.
The stress applied from the metal layer is relieved by the stress buffer layer and hardly applied to the semiconductor substrate. This prevents cracks originating from the through holes formed in the semiconductor substrate, thereby preventing deterioration of electrical characteristics and reliability.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a stress buffer layer on the back side of the semiconductor substrate is provided after the step of forming a through hole in the semiconductor substrate. Can easily provide a stress buffer layer. This makes it possible to manufacture a semiconductor device free from cracks originating from the through holes in the semiconductor substrate and without deterioration in electrical characteristics and reliability due to the cracks.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention, and a GaAs (III-V compound semiconductor) FET chip having a PHS structure and a via hole structure. This is an example. This GaAsF
In the ET chip, an FET element 5 having a gate electrode 2, a source electrode 3, and a drain electrode 4 is formed on the surface of a GaAs substrate 1, and a via hole 6 is formed in a portion of the GaAs substrate 1 corresponding to the source electrode 3. Have been.

A stress buffer layer (stress buffer layer) 21 made of a metal material having a linear expansion coefficient close to that of the GaAs substrate 1 and having a large Young's modulus is formed on the entire back surface of the GaAs substrate 1 including the inner surface of the via hole 6. On the stress buffer layer 21, a metal layer serving as a conductive path of Au plating, for example, a layered Ti-Au layer 7 is formed, and on the Ti-Au layer 7, an Au layer 8 is formed as PHS. I have.

Further, for example, a Ti layer 9 is formed as a barrier metal in and around the via hole 6. As the stress buffer layer 21, a W film having a thickness of about 5 μm [linear expansion coefficient: 4.5 × 10 ⁻⁶ (/ K), Young's modulus: 345 × 10 ⁹ (N / m ² )] is preferable. Also,
The Ti layer 9 need not be formed if it is not particularly required, as in the conventional example.

Next, a method of manufacturing the GaAs FET chip will be described with reference to FIG. First, as shown in FIG. 2A, a gate electrode 2, a source electrode 3, a drain electrode 4, and the like are sequentially formed on the surface of a GaAs substrate 1 by various conventional process techniques, and a FET element 5 is manufactured. G
The back surface of the aAs substrate 1 is thinned by polishing, etching or the like, and a resist pattern 11 is formed on the back surface of the GaAs substrate 1 by ordinary lithography. Here, the GaAs substrate 1 is thinned to 50 μm.

Next, as shown in FIG.
In a portion of the s substrate 1 corresponding to the source electrode 3, a via hole 6 penetrating the substrate 1 is formed from the back surface of the substrate 1 by a normal etching technique. Next, as shown in FIG.
A film made of a metal material having a large Young's modulus near the As substrate 1 is formed on the entire back surface of the GaAs substrate 1 including the inner surface of the via hole 6 by a method such as sputtering or vapor deposition. As the stress buffer layer 21, a W film having a thickness of about 5 μm [linear expansion coefficient: 4.5 × 10 ⁻⁶ (/ K), Young's modulus: 345 × 10
⁹ (N / m ² )].

Next, as shown in FIG. 1D, a Ti-Au layer 7 as a metal layer serving as a conductive path for plating is formed on the stress buffer layer 21 so as to have a thickness of about 50 nm.
A thickness of 00 nm is formed by sputtering or vapor deposition, and then an Au layer 8 is formed as a PHS to a thickness of 15 μm by electrolytic plating or the like. Although not shown here, at this time, in order to easily perform pelletizing in a later step, a mask pattern is formed on the scribe line by using a photoresist, and is removed after plating Au, and the plated Au is used as a mask. The plating path is often etched by ion milling or the like.

If necessary, as shown in FIG. 3E, a barrier metal for preventing the diffusion of Sn from the solder in the via hole 6 which causes the deterioration of the FET characteristics is formed by sputtering or vapor deposition. A film is formed only inside and around the via hole 6 by ordinary lithography, etching or the like. Here, as the barrier metal, for example,
The Ti layer 9 is formed with a thickness of 300 nm by sputtering or vapor deposition.

Here, the coefficient of linear expansion of Au is about 2.4 times larger than that of GaAs, while the stress buffer layer 21 is made of Ga.
Since As and As have a similar coefficient of linear expansion, stress due to a temperature change applied to the GaAs substrate 1 is small. On the other hand, even when the stress caused by the temperature change due to the difference between the linear expansion coefficient of Au and the stress buffer layer 21 is large, the stress buffer layer 21 has a large Young's modulus and a small deformation with respect to the same magnitude of stress. Therefore, the magnitude of the stress caused by Au transmitted to the GaAs substrate 1 is very small.

When W is used as the stress buffer layer 21, for example, W has a linear expansion coefficient close to that of GaAs (about 0.
76 times), the stress due to the temperature change applied to the GaAs substrate 1 by W is small. On the other hand, W has a large Young's modulus (approximately 4.3 of Au) even when stress caused by a temperature change due to a difference in linear expansion coefficient between Au and W (about 3.2 times) is large.
Times), since the deformation is small for the same magnitude of stress,
The magnitude of the stress caused by Au transmitted to the GaAs substrate 1 is very small.

FIG. 3 shows W of GaAs in the case of a three-layered bimetal structure (GaAs / W / Au) for simplicity.
FIG. 9 is a diagram showing the result of calculating the stress on the side surface, and FIG.
Is 50 μm and the thickness of Au is 15 μm,
By setting the thickness of W to 5 μm, the result is that the stress is reduced by almost half. However, since the critical stress at which a crack occurs in the via hole 6 varies depending on the transition density of the substrate and the like, it is difficult to accurately determine the actually required amount of stress relaxation.

As described above, the GaAs of the present embodiment
According to the sFET chip, the stress buffer layer 21 made of a metal material having a linear expansion coefficient close to that of the GaAs substrate 1 and having a large Young's modulus is formed on the entire back surface of the GaAs substrate 1 including the inner surface of the via hole 6. There is an effect that it is possible to prevent the occurrence of cracks originating from the via holes 6 which occur when heating the chip at the time of assembling it into a package.

In this embodiment, the GaAsFE
Although the description has been made taking the T chip as an example, regardless of the type of semiconductor and the type of FET constituting the FET chip, PH
Needless to say, the present invention can be applied to a semiconductor element having S.

[Second Embodiment] FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention, which is an example of a GaAs FET chip having a PHS structure and a via hole structure. In this GaAs FET chip, similarly to the first embodiment, an FET element 5 having a gate electrode 2, a source electrode 3, and a drain electrode 4 is formed on the surface of a GaAs substrate 1, and the source electrode 3 of the GaAs substrate 1 is formed. Via holes 6 are formed in portions corresponding to.

The inner surface of the via hole 6 and G
A stress buffer layer (stress buffer layer) 31 made of a metal material having a linear expansion coefficient close to that of the GaAs substrate 1 and having a large Young's modulus is formed around the via hole 6 on the back surface of the aAs substrate 1. On the layer 31 and on the back surface of the GaAs substrate 1 other than the stress buffer layer 31, a metal layer serving as a conductive path of Au plating, for example, a layered Ti-Au
A layer 7 is formed, and Au is formed on the Ti-Au layer 7 as PHS.
Layer 8 is formed.

Further, for example, a Ti layer 9 is formed as a barrier metal inside and around the via hole 6. As the stress buffer layer 31, a W film (linear expansion coefficient: 4.5 × 10 ⁻⁶ (/ K), Young's modulus: 345 × 10 ⁹ (N / m ² )) having a thickness of about 5 μm is preferable. Also,
The Ti layer 9 need not be formed if it is not particularly required, as in the conventional example.

Next, a method of manufacturing the GaAs FET chip will be described with reference to FIG. First, as shown in FIG. 5A, similarly to the first embodiment, the GaAs substrate 1
A gate electrode 2, a source electrode 3, a drain electrode 4 and the like are sequentially formed on the surface of the substrate by various conventional process techniques.
After the ET element 5 is manufactured, the back surface of the GaAs substrate 1 is thinned by polishing, etching, or the like, and a resist pattern 11 is formed on the back surface of the GaAs substrate 1 by a normal lithography technique. Here, the GaAs substrate 1 is 50
The thickness has been reduced to μm.

Next, as shown in FIG.
In a portion of the s substrate 1 corresponding to the source electrode 3, a via hole 6 penetrating the substrate 1 is formed from the back surface of the substrate 1 by a normal etching technique. Next, as shown in FIG. 3C, in order to form a stress buffer layer 31, a film 32 made of a metal material having a linear expansion coefficient close to that of the GaAs substrate 1 and having a high Young's modulus is formed by a method such as sputtering or vapor deposition. A film is formed on the entire back surface of the GaAs substrate 1 including the inner surface of the via hole 6.

As the film 32, a W film [linear expansion coefficient: 4.
5 × 10 ⁻⁶ (/ K), Young's modulus: 345 × 10 ⁹ (N /
m ² )] is formed on the entire back surface of the GaAs substrate 1 including the inner surface of the via hole 6 by a method such as sputtering or vapor deposition. Next, as shown in FIG.
The film 32 formed on the entire rear surface of the substrate is patterned using a normal lithography technique and an etching technique so as to remain only in the inner portion of the via hole 6 and its peripheral portion, thereby forming the stress buffer layer 31.

FIG. 6 is a bottom view showing the stress buffer layer 31. In the film 32 formed on the entire rear surface of the GaAs substrate 1, the stress buffer layer 31 is formed by leaving a certain area from the via hole 6. Other areas are removed. Here, about 10 μm from via hole 6
, And W in other regions is removed.

Next, as shown in FIG. 3E, the metal serving as a conductive path for plating is formed on the stress buffer layer 31 and on the back surface of the GaAs substrate 1 in the other area as in the first embodiment. Each of the Ti-Au layers 7 is about 50 nm,
An Au layer 8 is formed as a PHS to a thickness of 15 μm by electrolytic plating or the like, and is formed by sputtering or vapor deposition to a thickness of 200 nm.

Although not shown here, at this time, a mask pattern of a photoresist is formed on a scribe line in order to easily perform pelletizing in a later step.
In many cases, Au is removed after plating, and the plating path is etched by ion milling or the like using the plated Au as a mask.

If necessary, as shown in FIG. 3F, a barrier metal for preventing the diffusion of Sn from the solder in the via hole 6 which causes the deterioration of the FET characteristics is formed by sputtering or vapor deposition. A film is formed only inside and around the via hole 6 by ordinary lithography, etching or the like. Here, as the barrier metal, for example,
The Ti layer 9 is formed to a thickness of 300 nm by sputtering or vapor deposition.

In the present embodiment, since the stress buffer layer 31 is not provided except for the inner surface of the via hole 6 and its peripheral portion, the stress other than the peripheral portion of the via hole 6 is not reduced. However, since there is no stress concentration outside the via hole 6 and cracks are originally unlikely to occur, no problems occur except for an increase in the number of patterning steps.

On the other hand, as in the first embodiment, GaAs
As compared with the case where the stress buffer layer 21 is formed on the entire back surface of the substrate 1, the stress buffer layer 31 having a small thermal conductivity is not provided in the region other than the via hole 6, so that the thermal resistance is slightly reduced and the heat radiation property is further improved. There is an advantage that an FET chip excellent in the above can be obtained.

Third Embodiment FIG. 7 is a sectional view showing a semiconductor device according to a third embodiment of the present invention, which is an example of a GaAs FET chip having a PHS structure and a via hole structure. This GaAs FET chip has a gate electrode 2, a source electrode 3, and a drain electrode 4 on the surface of a GaAs substrate 1, as in the first and second embodiments.
An element 5 is formed, and a via hole 6 is formed in a portion of the GaAs substrate 1 corresponding to the source electrode 3.

A donut-shaped stress buffer layer (stress buffer layer) 41 made of a metal material having a linear expansion coefficient close to that of the GaAs substrate 1 and having a large Young's modulus is provided only in the peripheral portion of the via hole 6 on the back surface of the GaAs substrate 1. Are formed, and the via holes 6 including on the stress buffer layer 41 are formed.
A metal layer serving as a conductive path for Au plating, for example, a layered Ti-Au layer 7 is formed on the inner surface of the GaAs substrate 1 and the back surface of the GaAs substrate 1, and an Au layer 8 is formed as a PHS on the Ti-Au layer 7. I have.

Further, for example, a Ti layer 9 is formed as a barrier metal inside and around the via hole 6. As the stress buffer layer 41, a W film [linear expansion coefficient: 4.5 × 10 ⁻⁶ (/ K), Young's modulus: 345 × 1
0 ⁹ (N / m ² )]. The Ti layer 9 need not be formed if it is not particularly necessary, as in the conventional example.

Next, a method of manufacturing the GaAs FET chip will be described with reference to FIG. First, as shown in FIG. 8A, GaAs is formed in the same manner as in the first and second embodiments.
A gate electrode 2, a source electrode 3, a drain electrode 4, and the like are sequentially formed on the surface of the s substrate 1 by various conventional process technologies, and an FET element 5 is manufactured. Then, the back surface of the GaAs substrate 1 is polished and etched. Make it thinner. Here, the GaAs substrate 1 is thinned to 50 μm.

Next, a film 42 made of a metal material having a high Young's modulus and a linear expansion coefficient close to that of the GaAs substrate 1 and serving as the stress buffer layer 41 is formed by a method such as sputtering or vapor deposition. Here, as the film 42, a W film [linear expansion coefficient:
4.5 × 10 ^-6 (/ K), Young's modulus: 345 × 10
⁹ (N / m ² )]. Next, as shown in FIG. 2B, the film 42 is buttered in a donut shape so as to remain only in the peripheral portion of the region where the via hole 6 is to be formed and not to remain in the via hole 6, so as to reduce the stress buffer. Layer 4
Let it be 1.

FIG. 9 is a bottom view showing the stress buffer layer 41. The stress buffer layer 41 is formed by patterning the film 42 only in the peripheral portion of the via hole 6 into a donut shape having a certain width. . Here, patterning is performed in a donut shape having a width of about 10 μm. Next, as shown in FIG. 1C, a resist pattern 11 is formed on the back surface of the GaAs substrate 1, and a via hole 6 is formed by a normal etching technique.

Next, as shown in FIG. 2D, the resist pattern 11 is peeled off, and the inner surface of the via hole 6 including the stress buffer layer 41 and the back surface of the GaAs substrate 1 are removed.
As in the first and second embodiments, the Ti—Au layer 7 as a metal layer serving as a conductive path for plating is set to about 50 nm,
A thickness of 00 nm is formed by sputtering or vapor deposition, and then an Au layer 8 is formed as a PHS to a thickness of 15 μm by electrolytic plating or the like.

Although not shown here, at this time, a mask pattern of a photoresist is formed on the scribe line in order to easily perform pelletizing in a later step.
In many cases, Au is removed after plating, and the plating path is etched by ion milling or the like using the plated Au as a mask.

If necessary, as shown in FIG. 3E, a barrier metal for preventing the diffusion of Sn from the solder in the via hole 6 which causes the deterioration of the FET characteristics is formed by sputtering or vapor deposition. A film is formed only inside and around the via hole 6 by ordinary lithography, etching or the like. Here, as the barrier metal, for example,
The Ti layer 9 is formed with a thickness of 300 nm by sputtering or vapor deposition.

In the present embodiment, since the stress buffer layer 41 is provided only in the peripheral portion of the via hole 6 and is not provided in other regions, the stress outside the peripheral portion of the via hole 6 is not relaxed. Not only the via hole 6
The internal stress is not relieved. However, the stress in the region along the periphery of the opening of the via hole 6 is reduced, the stress transmitted from the opening of the via hole 6 to the inside of the via hole 6 is reduced, and the degree of concentration of the stress can be reduced. it can.

On the other hand, compared to the first and second embodiments,
Since the stress buffer layer 41, which is a metal layer having a low thermal conductivity, is not formed inside the via hole 6, the thermal resistance is slightly reduced in the via hole 6, and an FET having better heat radiation characteristics can be obtained. There is.

[Fourth Embodiment] FIG. 10 shows a fourth embodiment of the present invention.
1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, which is an example of a GaAs FET chip having a PHS structure and a via hole structure. This GaAs FET chip has a gate electrode 2, a source electrode 3 and a drain electrode 4 on the surface of a GaAs substrate 1, as in the first to third embodiments.
An element 5 is formed, and a via hole 6 is formed in a portion of the GaAs substrate 1 corresponding to the source electrode 3.

A stress buffer layer (stress buffer layer) 51 made of a metal material having a linear expansion coefficient close to that of the GaAs substrate 1 and having a large Young's modulus is embedded in the via hole 6. 51 and Ga
On the back surface of the As substrate 1, a metal layer serving as a conductive path of Au plating, for example, a layered Ti-Au layer 7 is formed.
An Au layer 8 is formed on one Au layer 7 as PHS.

Further, at a position corresponding to the via hole 6 on the Au layer 8, that is, at a position corresponding to the stress buffer layer 51, for example, a Ti layer 9 is formed as a barrier metal. As the stress buffer layer 51, a W film [linear expansion coefficient: 4.5 × 10 ⁻⁶ (/ K), Young's modulus: 345 × 1
0 ⁹ (N / m ² )]. The Ti layer 9 need not be formed if it is not particularly necessary, as in the conventional example.

Next, a method of manufacturing the GaAs FET chip will be described with reference to FIG. First, FIG.
As shown in (a), similar to the first to third embodiments,
A gate electrode 2, a source electrode 3, a drain electrode 4 and the like are sequentially formed on the surface of the GaAs substrate 1 by various conventional process technologies, and an FET element 5 is manufactured. Then, the back surface of the GaAs substrate 1 is polished and etched. A thin resist layer 11 is formed on the back surface of the GaAs substrate 1 by a normal lithography technique. Here, GaA
The s-substrate 1 is thinned to 50 μm.

Next, as shown in FIG.
In a portion of the s substrate 1 corresponding to the source electrode 3, a via hole 6 penetrating the substrate 1 is formed from the back surface of the substrate 1 by a normal etching technique. Next, as shown in FIG. 4C, a buried layer 52 made of a metal material having a high Young's modulus and a linear expansion coefficient close to that of the GaAs substrate 1 is selected.
The stress buffer layer 51 is formed in the via hole 6 using a method such as D growth.

Alternatively, the buried layer 52 is formed on the entire back surface of the GaAs substrate 1 by a method such as CVD growth or sputtering or vapor deposition, and the buried layer 52 is left in the via hole 6 by polishing, etching, or the like. It may be. As the metal material of the buried layer 52, W
[Linear expansion coefficient: 4.5 × 10 ^-6 (/ K), Young's modulus: 3
45 × 10 ⁹ (N / m ² )] is preferably used.

Next, as shown in FIG. 4D, a Ti-Au layer 7 as a conductive path for plating is formed on the stress buffer layer 51 and the back surface of the GaAs substrate 1 by about 50 nm and 200 nm, respectively. Is formed by sputtering, vapor deposition, or the like so that the thickness of the Au layer 8 becomes PHS.
Is formed to a thickness of 15 μm by electrolytic plating or the like.

Although not shown here, at this time, a mask pattern of a photoresist is formed on a scribe line in order to facilitate pelletization in a later step.
In many cases, Au is removed after plating, and the plating path is etched by ion milling or the like using the plated Au as a mask.

If necessary, as shown in FIG. 7E, a barrier metal for preventing the diffusion of Sn from the solder in the via hole 6 which causes the deterioration of the FET characteristics is formed by sputtering or vapor deposition. A film is formed only at a position corresponding to the stress buffer layer 51 on the Au layer 8 by ordinary lithography, etching or the like. Here, as the barrier metal, for example, a Ti layer 9 having a thickness of 300 nm is formed by sputtering or vapor deposition.

In this embodiment, since the stress buffer layer 51 is not provided except for the via hole 6, the via hole 6
, But the stresses other than via holes 6 are not reduced. However, as compared with the second and third embodiments, the via holes 6 can be formed without a lithography process.
There is an advantage that a metal layer can be formed only on the metal layer.

In connection with the description of the claims, the present invention can further take the following aspects. (1) The semiconductor device according to claim 1, wherein the semiconductor substrate is a III-V compound semiconductor substrate, and the stress buffer layer has a linear expansion coefficient similar to that of the III-V compound semiconductor substrate and a Young's modulus. It is made of a large metal material. (2) The semiconductor device according to (1), wherein the III-
The group V compound semiconductor substrate is a GaAs substrate, the metal layer is a metal layer including at least an Au layer, and the stress buffer layer includes at least one or more selected from W, Mo, and CuW. It is a metal material.

(3) a step of forming an element portion on the front surface side of the semiconductor substrate, and a step of forming a stress buffer layer on a rear surface side of the semiconductor substrate at a position corresponding to a ground electrode of the element portion; Forming a through hole from the back side at a position corresponding to the ground electrode of the element portion of the semiconductor substrate, and dissipating heat generated in the semiconductor substrate to the back side of the semiconductor substrate and passing through the through hole; Forming a metal layer connected to the ground electrode. (4) The method of manufacturing a semiconductor device according to claim 6,
The step of forming the stress buffer layer is a step of forming the stress buffer layer on the entire back surface including the inner surface of the through hole of the semiconductor substrate.

(5) In the method of manufacturing a semiconductor device according to claim 6, the step of forming the stress buffer layer includes forming a stress buffer layer on the entire back surface including the inner surface of the through hole of the semiconductor substrate, and forming the stress buffer layer. The method is characterized by selectively removing the layer and leaving a stress buffer layer only on the inner surface of the through hole of the semiconductor substrate and its peripheral portion. (6) In the method of manufacturing a semiconductor device according to claim 6,
The step of forming the stress buffer layer is a step of embedding the stress buffer layer in the through hole of the semiconductor substrate.

[0066]

As described above, according to the semiconductor device of the present invention, the stress buffer layer is provided between the semiconductor substrate and the metal layer. In addition, the stress applied from the metal layer is reduced by the stress buffer layer, so that the stress applied to the semiconductor substrate can be prevented. Therefore, generation of cracks originating from the through holes formed in the semiconductor substrate can be prevented, and as a result, electrical characteristics and reliability can be prevented from deteriorating. Can be improved.

According to the method of manufacturing a semiconductor device of the present invention,
Since the step of forming a stress buffer layer on the back side of the semiconductor substrate is provided after the step of forming the through hole in the semiconductor substrate, the stress buffer layer can be easily provided between the semiconductor substrate and the metal layer. In addition, it is possible to easily manufacture a semiconductor device in which no crack originating from the through hole of the semiconductor substrate is generated, and the electrical characteristics and reliability are not deteriorated due to the crack.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a view showing Ga in the semiconductor device according to the first embodiment of the present invention;
GaAs in a three-layer bimetal structure of As / W / Au
FIG. 9 is a diagram showing a calculation result of stress on the W-side surface of FIG.

FIG. 4 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a process chart illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a bottom view showing a pattern of a stress buffer layer of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a process chart illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 9 is a bottom view showing a pattern of a stress buffer layer of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a process chart illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a conventional semiconductor device.

FIG. 13 is a process chart showing a conventional method for manufacturing a semiconductor device.

FIG. 14 is a schematic view showing a defect of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 GaAs substrate (semiconductor substrate) 2 gate electrode 3 source electrode (ground electrode) 4 drain electrode 5 FET element (element section) 6 via hole (through hole) 7 Ti-Au layer 8 Au layer 9 Ti layer 11 resist layer 13 crack 21 stress buffer layer (stress buffer layer) 31 stress buffer layer (stress buffer layer) 32 film 41 stress buffer layer (stress buffer layer) 42 film 51 stress buffer layer (stress buffer layer) 52 buried layer

Claims (6)

(57) [Claims] An element portion is provided on a front surface side of a semiconductor substrate, a through hole is formed at a position of the semiconductor substrate corresponding to a ground electrode of the element portion, and a through hole is generated in the semiconductor substrate on a back surface side of the semiconductor substrate. A semiconductor device comprising a metal layer for radiating heat and connecting to the ground electrode through the through hole, wherein a stress buffer layer is provided between the semiconductor substrate and the metal layer. 2. The semiconductor device according to claim 1, wherein the stress buffer layer is provided on the entire back surface including the inner surface of the through hole of the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein said stress buffer layer is provided only in a peripheral portion of said through hole. 4. The semiconductor device according to claim 1, wherein said stress buffer layer is provided on an inner surface of a through hole of said semiconductor substrate and a peripheral portion thereof. 5. The semiconductor device according to claim 1, wherein said stress buffer layer is embedded in a through hole of said semiconductor substrate. 6. A step of forming an element portion on a front surface side of a semiconductor substrate, a step of forming a through hole from a back surface side of the semiconductor substrate at a position corresponding to a ground electrode of the element portion, Forming a metal layer connected to the ground electrode through the through hole by dissipating heat generated in the semiconductor substrate on the back surface side, after the step of forming the through hole, Forming a stress buffer layer on the back side of the semiconductor substrate.