JP2842528B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a wiring by electrolytic plating.

[0002]

2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device of this type has been disclosed in Japanese Patent Application Laid-Open No. 63-161644, for example, when forming wiring by electrolytic plating, the adhesion to a surface protective film is reduced. Used for security purposes.

FIG. 4 is a sectional view of a manufacturing process showing an example of a conventional method of manufacturing a semiconductor device. In FIG.
Is a substrate, 22 is a metal thin film, 23 is a photoresist, 24
Is a wiring pattern, 25 is Au plating, 26 is an uneven portion, 27
Is a plating wiring, and 28 is a surface protection film.

A metal thin film 22 is formed on a substrate 21 (FIG. 4A). Next, a wiring pattern 24 is formed with a photoresist 23.
(FIG. 4 (b)), and A is formed by electrolytic plating.
u is formed inside the wiring pattern 24 (FIG. 4).
(C)). Then immersed in Au etching solution for a short time
An uneven portion 26 is formed on the surface of the u-plate 25 (FIG. 4).
(D)) Thereafter, the photoresist 23 and the metal thin film 22 for the plating electrode other than the wiring portion are removed to form a plating wiring 27 (FIG. 4E). Next, a surface protection film 28 is formed (FIG. 4F).

As another method, for example, Japanese Patent Laid-Open No. 5-206
No. 122 describes a technique of selectively growing a metal film on an Au wiring by using electroless plating after forming an Au wiring, and then forming a surface protective film.

In any of the methods, after forming the wiring by plating, a process for improving the adhesion of the wiring surface is performed.

[0007]

The first problem is that the number of steps increases.

[0008] The reason is that after forming the Au wiring, the unevenness of the surface layer is etched or film-formed to enhance the adhesion to the surface protective film.

A second problem is that the reliability is reduced.

[0010] The reason is that the etching process after the formation of the wiring reduces the cross-sectional area of the wiring, and in the worst case, there is a risk that the wiring is opened. In addition, the growth of the metal film after the formation of the wiring narrows the distance between the wirings and involves a risk of short-circuit between the wirings.

An object of the present invention is to provide a method for forming a plated wiring having excellent adhesion to a surface protective film while ensuring the burying property of a through hole.

[0012]

According to the present invention, a step of forming a power supply layer on an insulating film, a step of masking the power supply layer with a desired circuit pattern using a photoresist, and a step of exposing the power supply layer from the photoresist After forming a plating film on the power supply layer using a plating solution, using a plating solution having a temperature higher than the temperature of the plating solution on the plating film, the crystal grains are larger than the plating film and the surface irregularities are larger. A method of manufacturing a semiconductor device, comprising: forming a plating film; and forming an insulating protective film or an interlayer insulating film that covers the plating film having large irregularities is obtained.

According to the present invention, a silicon substrate or G
forming a lower layer wiring on an a-As substrate, forming an insulating film covering the substrate and the lower wiring, and forming a through hole reaching the upper surface of the lower wiring in the insulating film; Forming a power supply layer on the entire surface, masking the power supply layer with a desired circuit pattern using a photoresist, and a plating solution so as to fill the through hole on the power supply layer exposed from the photoresist. After forming a plating film using, a step of forming a plating film on the plating film having a larger crystal grain than the plating film using a plating solution having a temperature higher than the temperature of the plating solution, the surface unevenness is large. Forming an insulating protective film or an interlayer insulating film covering the plating film having large irregularities.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein the desired circuit pattern is a circuit pattern that does not mask the through hole.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the step of removing the photoresist and the power supply film below the photoresist after forming the plating film having large irregularities. A method is obtained.

Further, according to the present invention, the surface of the plating film formed so as to fill the inside of the through hole is formed by:
A method for manufacturing a semiconductor device characterized by having a smooth surface with small crystal grains is obtained.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein the plating film formed up to the completion of the filling of the through hole and the plating film having large irregularities are both Au plating films. Can be

[0018]

[0019]

When the plating solution is kept at a low temperature until the filling of the through-hole is completed, the crystal nucleus growth is promoted, so that the film surface becomes smooth and the embedding property of the through-hole is improved. After completion of the through-hole burying, by performing plating at a high temperature, the growth of existing crystal nuclei is promoted, and the unevenness of the formed wiring surface is increased, so that the adhesion to the surface protective film is improved. FIG. 2 is a schematic cross-sectional view showing the growth of an Au plating film at a low plating solution temperature at a low temperature, and FIG. From FIG. 2, it can be easily understood from FIG. 2 that when the plating is performed at a low temperature, the crystal grains become small and a smooth surface is formed, and when the plating is performed at a high temperature, the crystal grains are large and the irregularities are large.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. 1A to 1E are schematic cross-sectional views of a manufacturing process showing one embodiment of a method for manufacturing a semiconductor device according to the present invention. In FIG. 1, 1 is a silicon substrate, 2 is a lower Al wiring, 3 is a 8000 angstrom thick SiO ₂ film formed by the CVD method, 4 is a through hole opened for electrical connection with the lower Al wiring, 5 is a thickness of 3000 formed by a sputtering method.
Angstrom / 1000 Angstrom Au /
TiW film 7 is a low temperature A film formed at a plating solution temperature of 40 ° C.
A u-plated film, 8 is a high-temperature Au-plated film formed at a plating solution temperature of 60 ° C., and 9 is a polyimide film for surface protection. The gold plating solution used is Neutronex 210N (Tanaka Kikinzoku sales).

Next, a manufacturing method according to the present invention will be described with reference to FIG.
This will be described with reference to FIG. Lower Al wiring 2 on silicon substrate 1
After forming the SiO ₂ film 3, the through hole 4 is formed.
Is opened (FIG. 1 (a)). Next, an Au / TiW film 5 serving as a power supply layer at the time of plating is formed and then masked by a photoresist 6 so that a desired circuit pattern can be formed (FIG. 1B). A
A u-plated film 7 is formed (FIG. 1C), and then a high-temperature Au-plated film 8 is formed to a desired thickness (FIG. 1D). After the plating is completed, the photoresist 6 and the unnecessary portions of Au / Ti
The W film 5 is removed to form a polyimide film 9 (FIG. 1).
(E)).

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the above-described embodiment of the present invention, the step of forming a surface protective film on a plated wiring has been described, but this may be an interlayer insulating film of a multilayer wiring, for example.

In the present invention, a silicon substrate is used as the substrate, but this may be another type of semiconductor substrate such as a Ga-As substrate.

In the present invention, the lower layer is made of Al wiring, but the material is Au, which is the same as the plating film, or Cu, A
There is no limitation on l-Cu or Al-Si-Cu or the material. Also, it is not necessary to be a wiring, and an element such as a transistor or a resistor may be used. Similarly, 4 may be a contact hole.

Further, according to the present invention, CVD is used as an interlayer insulating film.
Was used SiO ₂ film by law, it may be a LPD method and substrate oxidation, also other than SiO ₂ insulating film such as Si
It may be an inorganic insulating film such as ON or Si ₃ N ₄ or an organic insulating film such as a polyimide film.

Also, 300 as a metal thin film at the time of gold plating.
0 angstrom / 1000 angstrom Au
Although the / TiW film was used, the thickness is not limited as long as there is no disconnection in the opening, and Pt / Ti or Au
/ Ti, Cr, Ni, Cu.

In this embodiment, the temperature of the plating solution is set to 40
Although there are two stages, that is, C and 60C, any temperature between 35C and 80C may be used, and the number of heating stages may be more.
Further, the Au plating solution used is not limited.

Although a polyimide film is used as the surface protective film, any organic or inorganic film can be used as long as it is an insulating / protective film.

[0029]

According to the present invention, it is possible to form irregularities on the surface layer for enhancing the adhesion to the surface protective film during the formation of the Au wiring. , The number of steps can be reduced.

Further, according to the present invention, since the Au wiring can be formed according to the design dimensions, there is no danger of the open / short of the wiring which has conventionally occurred at the time of processing the unevenness of the wiring surface, and the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a process chart showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional view of an Au plating film grown at a low plating solution temperature.

FIG. 3 is a schematic sectional view of an Au plating film grown at a high plating solution temperature.

FIG. 4 is a process chart showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 lower Al wiring 3 SiO ₂ film 4 through hole 5 Au / TiW film 6 photoresist 7 low temperature Au plating film 8 high temperature Au plating film 9 polyimide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768 C25D 5/02

Claims (6)

(57) [Claims] 1. A step of forming a power supply layer on an insulating film, a step of masking the power supply layer with a desired circuit pattern using a photoresist, and using a plating solution on the power supply layer exposed from the photoresist. Forming a plating film on the plating film, using a plating solution having a higher temperature than the temperature of the plating solution to form a plating film having crystal grains larger than the plating film and having a large surface irregularity, Forming an insulating protective film or an interlayer insulating film that covers the plating film having large irregularities. 2. A step of forming a lower wiring on a silicon substrate or a Ga-As substrate, a step of forming an insulating film covering the substrate and the lower wiring, and reaching the upper surface of the lower wiring in the insulating film. A step of opening a through hole, a step of forming a power supply layer on the entire surface, and a step of masking the power supply layer with a desired circuit pattern using a photoresist,
After forming a plating film using a plating solution on the power supply layer exposed from the photoresist so as to fill the inside of the through hole, using a plating solution higher than the temperature of the plating solution on the plating film. A semiconductor comprising: a step of forming a plating film having crystal grains larger than the plating film and having a large surface irregularity; and a step of forming an insulating protective film or an interlayer insulating film covering the plating film having the large irregularity. Device manufacturing method. 3. The method according to claim 2, wherein the desired circuit pattern is a circuit pattern that does not mask the through hole. 4. The method according to claim 1, further comprising, after forming the plating film having large irregularities, removing the photoresist and the power supply film below the photoresist. 13. The method for manufacturing a semiconductor device according to item 5. 5. The plating film according to claim 2, wherein a surface of the plating film formed so as to fill the through hole has a smooth surface with small crystal grains. Of manufacturing a semiconductor device. 6. The plating film formed until the through hole is completely buried and the plating film having large irregularities are both Au.
The method for manufacturing a semiconductor device according to claim 2, wherein the method is a plating film.