JP2003068671A - Electrode for semiconductor device - Google Patents

Electrode for semiconductor device

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Publication number
JP2003068671A
JP2003068671A JP2001252087A JP2001252087A JP2003068671A JP 2003068671 A JP2003068671 A JP 2003068671A JP 2001252087 A JP2001252087 A JP 2001252087A JP 2001252087 A JP2001252087 A JP 2001252087A JP 2003068671 A JP2003068671 A JP 2003068671A
Authority
JP
Japan
Prior art keywords
electrode
alloy
semiconductor device
forming
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001252087A
Other languages
Japanese (ja)
Inventor
Gousaku Katou
豪作 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2001252087A priority Critical patent/JP2003068671A/en
Publication of JP2003068671A publication Critical patent/JP2003068671A/en
Pending legal-status Critical Current

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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
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Abstract

PROBLEM TO BE SOLVED: To provide an electrode for semiconductor device, with which metal peelings in a non-alloy electrode are reduced. SOLUTION: In the electrode for semiconductor device, the non-alloy, electrode formed on a semiconductor layer or wafer, is covered with a metal peel protecting layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置用電極
および該電極の形成方法、ならびに該電極を有する半導
体装置に関する。TECHNICAL FIELD The present invention relates to an electrode for a semiconductor device, a method for forming the electrode, and a semiconductor device having the electrode.

【０００２】[0002]

【従来の技術】例えば、半導体レーザ、発光ダイオード
またはトランジスタなどの半導体装置に用いられる電極
は、その形成に際してアロイ化（合金化）と呼ばれる熱
処理を施し、半導体層または基板と電極材料の接合を強
めるのが一般的である。しかし、高温、例えば約３００
℃以上の温度でアロイ化を行うと、半導体装置に悪影響
を与えることがある。例えば、半導体レーザにおいて
は、前記高温下でのアロイ化により、しきい値電流Ｉ
ｔｈの上昇、寿命の低下または信頼性の低下などの問題
が生じることがある。2. Description of the Related Art For example, an electrode used in a semiconductor device such as a semiconductor laser, a light emitting diode or a transistor is subjected to a heat treatment called alloying (alloying) at the time of its formation to strengthen the bonding between the semiconductor layer or the substrate and the electrode material. Is common. However, high temperatures, eg about 300
If alloying is performed at a temperature of ℃ or more, the semiconductor device may be adversely affected. For example, in a semiconductor laser, due to alloying at high temperature, the threshold current I
Problems such as an increase in th , a decrease in life, and a decrease in reliability may occur.

【０００３】そのため、電極の形成に際してアロイ化を
施さないノンアロイ電極が開発されている。例えばＧａ
Ａｓ系半導体化合物からなる半導体装置に用いられる電
極としては、ｎ型電極にはＡｕＧｅ／Ｎｉ／Ａｕなどの
アロイ電極が使用されているが、ｐ型電極にはＴｉ／Ｐ
ｔ／Ａｕなどのノンアロイ電極が使用されている。な
お、「ＡｕＧｅ／Ｎｉ／Ａｕ」という表記は、半導体層
または基板側からＡｕＧｅ合金、Ｎｉ、Ａｕがこの順序
で積層されていることを示している。以下も同様であ
る。Therefore, non-alloy electrodes have been developed which are not alloyed when forming the electrodes. For example Ga
As an electrode used in a semiconductor device made of an As-based semiconductor compound, an alloy electrode such as AuGe / Ni / Au is used as an n-type electrode, but Ti / P is used as a p-type electrode.
A non-alloy electrode such as t / Au is used. The notation “AuGe / Ni / Au” indicates that the AuGe alloy, Ni, and Au are stacked in this order from the semiconductor layer or substrate side. The same applies to the following.

【０００４】しかし、ノンアロイ電極は、半導体装置の
製造工程において電極を構成している金属が剥れやすく
（以下、この現象を「メタル剥れ」という）、製品不良
を誘発する可能性があり、製品不良による歩留りの低下
が問題となっていた。基板側の電極にノンアロイ電極を
用いる場合、特に前記メタル剥れが起こりやすかった。
なぜなら、例えば半導体レーザなどの発光素子の場合、
その製造工程において、基板側の電極はフルカットやダ
イシングをする際の表側となり、また、ワイヤボンドを
打つ側にもなるため、損傷を受けやすいからである。However, in the non-alloy electrode, the metal forming the electrode is easily peeled off in the manufacturing process of the semiconductor device (hereinafter, this phenomenon is referred to as “metal peeling”), and there is a possibility of causing a product defect. The reduction in yield due to product defects has been a problem. When a non-alloy electrode is used as the substrate-side electrode, the metal peeling is particularly likely to occur.
Because, in the case of a light emitting device such as a semiconductor laser,
This is because, in the manufacturing process, the electrode on the substrate side is the front side when full cutting or dicing is performed, and is also the side on which wire bonding is performed, so that the electrode is easily damaged.

【０００５】[0005]

【発明が解決しようとする課題】本発明は、ノンアロイ
電極においてメタル剥れが低減されている半導体装置用
電極を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide an electrode for a semiconductor device in which non-alloy electrode has reduced metal peeling.

【０００６】[0006]

【課題を解決するための手段】本発明者は、上記目的を
達成すべく、まずメタル剥れの原因について検討を加え
た。ノンアロイ電極には、例えば白金などのノンアロイ
系金属からなる薄膜を有する場合が多い。そして、かか
るノンアロイ系金属は、熱処理により拡散しにくく、合
金化しにくいという性質（ノンアロイ性）を有する。本
発明者は、メタル剥れが前記ノンアロイ性に起因するこ
とを知見した。すなわち、ノンアロイ電極においては、
前記ノンアロイ性に起因して密着性の悪い島状部分が生
じており、例えばフルカットやダイシング、またはワイ
ヤボンドなどの半導体装置の製造工程において、電極に
力が加わったときにかかる島状部分が剥れるのである。In order to achieve the above object, the present inventor first examined the cause of metal peeling. The non-alloy electrode often has a thin film made of non-alloy metal such as platinum. Then, such a non-alloy metal has a property (non-alloying property) that it is difficult to diffuse and become alloyed by heat treatment. The present inventors have found that metal peeling is caused by the non-alloy property. That is, in the non-alloy electrode,
Due to the non-alloy property, an island-shaped portion with poor adhesion is generated, and for example, in a semiconductor device manufacturing process such as full-cutting, dicing, or wire bonding, the island-shaped portion applied when a force is applied to the electrode is generated. It comes off.

【０００７】本発明者は、上記メタル剥れが生じるメカ
ニズムに着目し、ノンアロイ電極の最表層をメタル剥れ
保護層で覆うことにより、メタル剥れを低減することが
できることを知見した。本発明者は、さらに検討を重ね
て本発明を完成した。The present inventor has paid attention to the mechanism of the metal peeling and found that the metal peeling can be reduced by covering the outermost surface layer of the non-alloy electrode with the metal peeling protection layer. The present inventor has further studied and completed the present invention.

【０００８】すなわち、本発明は、（１） 半導体層ま
たは基板に形成されているノンアロイ電極がメタル剥れ
保護層で被覆されていることを特徴とする半導体装置用
電極、（２） メタル剥れ保護層が、アロイ系金属膜で
あることを特徴とする前記（１）に記載の半導体装置用
電極、（３） アロイ系金属が、金、チタン、ニッケ
ル、クロム、銀、アルミニウム、マグネシウム、鉛およ
び鉄から選ばれる少なくとも１種類の金属であることを
特徴とする前記（２）に記載の半導体装置用電極、に関
する。That is, according to the present invention, (1) an electrode for a semiconductor device characterized in that a non-alloy electrode formed on a semiconductor layer or a substrate is covered with a metal peeling protection layer, and (2) metal peeling. The protective layer is an alloy metal film, the electrode for a semiconductor device according to (1) above, and (3) the alloy metal is gold, titanium, nickel, chromium, silver, aluminum, magnesium, or lead. And the electrode for a semiconductor device according to (2) above, which is at least one kind of metal selected from iron and iron.

【０００９】また、本発明は、（４） ノンアロイ電極
が、白金膜を含む膜積層構造を有することを特徴とする
前記（１）に記載の半導体装置用電極、（５） ノンア
ロイ電極が、半導体層または基板側からチタン膜、白金
膜、金膜がこの順序で積層されていることを特徴とする
前記（４）に記載の半導体装置用電極、（６） 半導体
層または基板が、ｐ型であることを特徴とする前記
（１）に記載の半導体装置用電極、（７） 半導体層ま
たは基板が、III−Ｖ族半導体化合物からなることを特
徴とする前記（１）に記載の半導体装置、に関する。Further, according to the present invention, (4) the non-alloy electrode has a film laminated structure containing a platinum film, and (5) the non-alloy electrode is a semiconductor. A titanium film, a platinum film, and a gold film are laminated in this order from the layer or substrate side, the electrode for a semiconductor device according to (4) above, and (6) the semiconductor layer or substrate is p-type. (7) The semiconductor device electrode according to (1) above, (7) the semiconductor layer or the substrate is made of a III-V group semiconductor compound, according to (1) above, Regarding

【００１０】また、本発明は、（８） 前記（１）に記
載の電極を有することを特徴とする半導体装置、（９）
半導体装置が、半導体レーザ、発光ダイオードまたは
トランジスタであることを特徴とする前記（８）に記載
の半導体装置、（１０） （ａ）半導体層または基板に
蒸着によりノンアロイ電極を形成する工程と、（ｂ）前
記ノンアロイ電極上にメタル剥れ保護層を形成する工程
と、（ｃ）所望により熱処理を行う工程とを含むことを
特徴とする半導体装置用電極の形成方法、（１１）
（ａ）半導体層または基板に蒸着によりノンアロイ電極
を形成する工程と、（ｂ）半導体層または基板に形成さ
れたノンアロイ電極に電極パターンを形成する工程と、
（ｃ）電極パターンにより分離された個々のノンアロイ
電極上にメタル剥れ保護層を形成する工程と、（ｄ）所
望により熱処理を行う工程とを含むことを特徴とする半
導体装置用電極の形成方法、（１２） メタル剥れ保護
層を形成する工程が、アロイ系金属膜をスパッタリング
により製膜する工程であることを特徴とする前記（１
０）または（１１）に記載の半導体装置用電極の形成方
法、に関する。The present invention also provides (8) a semiconductor device having the electrode described in (1) above, (9)
The semiconductor device is a semiconductor laser, a light emitting diode or a transistor, and the semiconductor device according to (8) above, (10) (a) a step of forming a non-alloy electrode on a semiconductor layer or a substrate by vapor deposition, (b) a method for forming a metal peeling protection layer on the non-alloy electrode, and (c) a step of performing heat treatment if desired, a method for forming an electrode for a semiconductor device, (11)
(A) a step of forming a non-alloy electrode on the semiconductor layer or the substrate by vapor deposition; and (b) a step of forming an electrode pattern on the non-alloy electrode formed on the semiconductor layer or the substrate.
A method of forming an electrode for a semiconductor device, comprising: (c) a step of forming a metal peeling protection layer on each non-alloy electrode separated by an electrode pattern; and (d) a step of performing a heat treatment as desired. (12) The step of forming a metal peeling protection layer is a step of forming an alloy metal film by sputtering.
0) or the method of forming an electrode for a semiconductor device according to (11).

【００１１】[0011]

【発明の実施の形態】本発明において、ノンアロイ電極
とはアロイ化されていない電極をいう。言い換えれば、
ノンアロイ電極とは半導体層または基板との間での合金
化が少ない電極をいう。また、アロイ化しなくてもオー
ミック接触が得られる電極をいう。ノンアロイ電極とし
ては、公知の構造を有していてよいが、具体的には、ノ
ンアロイ系金属膜を含有する電極が挙げられる。ノンア
ロイ系金属は、上述したように熱処理により拡散しにく
く、合金化しにくいという性質（ノンアロイ性）を有す
る金属をいい、具体的にはＰｔなどが挙げられる。BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the non-alloyed electrode means an electrode which is not alloyed. In other words,
The non-alloy electrode is an electrode that is less likely to be alloyed with the semiconductor layer or the substrate. In addition, it refers to an electrode that can obtain ohmic contact without alloying. The non-alloy electrode may have a known structure, and specifically, an electrode containing a non-alloy metal film can be mentioned. The non-alloy metal is a metal having a property (non-alloying property) that it is difficult to diffuse by heat treatment and is difficult to alloy as described above, and specifically, Pt and the like can be mentioned.

【００１２】本発明で用いるノンアロイ電極の好ましい
態様としては、半導体層または基板側からチタン膜、白
金膜、金膜がこの順序で積層されている電極が挙げられ
る。ここでチタンを用いるのは半導体層または基板に対
する密着性が良いためであり、同様に良好な密着性を有
する他の金属、例えばクロム等を用いることもできる。
また、さらに金属膜が積層されている電極であってもよ
い。かかる電極として好ましくは、ニッケル膜、チタン
膜、白金膜、金膜がこの順序で積層されている電極が挙
げられる。A preferred embodiment of the non-alloy electrode used in the present invention is an electrode in which a titanium film, a platinum film and a gold film are laminated in this order from the semiconductor layer or substrate side. Titanium is used here because it has good adhesiveness to the semiconductor layer or the substrate, and other metals having similarly good adhesiveness, such as chromium, can also be used.
Further, it may be an electrode in which a metal film is further laminated. Preferred as such an electrode is an electrode in which a nickel film, a titanium film, a platinum film, and a gold film are laminated in this order.

【００１３】上記ノンアロイ電極は、半導体層または基
板上に形成される。該半導体層または基板は、本発明に
係る電極が用いられる装置、その装置の用途などに応じ
て、当技術分野で用いられている公知の材料からなる半
導体層または基板であってよい。半導体層または基板と
しては、例えばIII−Ｖ族半導体化合物からなることが
好ましい。また、半導体層または基板が、ｐ型半導体層
または基板であることも好ましい。The non-alloy electrode is formed on a semiconductor layer or a substrate. The semiconductor layer or substrate may be a semiconductor layer or substrate made of a known material used in the art, depending on the device in which the electrode according to the present invention is used, the application of the device, and the like. The semiconductor layer or the substrate is preferably made of, for example, a III-V semiconductor compound. It is also preferable that the semiconductor layer or substrate is a p-type semiconductor layer or substrate.

【００１４】上記III−Ｖ族半導化合物とは、化学式Ｉ
ｎａＡｌｂＧａｃＮｘＡｓｙＰｚ（ａ，ｂ，ｃ≦１，ａ
＋ｂ＋ｃ＝１，ｘ，ｙ，ｚ≦１，ｘ＋ｙ＋ｚ＝１）にお
いて組成比ａ，ｂおよびｃならびにｘ、ｙおよびｚをそ
れぞれの範囲内で変化させたすべての組成の半導体を含
むものを基本とする。さらに、III族元素であるＩｎ、
Ａｌ、Ｇａの一部をＢに置き換えたものや、Ｖ族元素で
あるＮ、Ａｓ、Ｐの一部をＳｂに置き換えたものも含ま
れる。本発明においては、中でも上記化学式において、
ｃおよびｙが０でないＧａＡｓ系半導体化合物が好まし
い。より好ましくは、化学式ＡｌｂＧａｃＡｓ（０≦ｂ
＜１，０＜ｃ≦１，ｂ＋ｃ＝１）において組成比ｂおよ
びｃをそれぞれの範囲内で変化させたすべての組成の半
導体化合物が挙げられる。The III-V group semiconductor compound is represented by the chemical formula I
n a Al b Ga c N x As y P z (a, b, c ≦ 1, a
+ B + c = 1, x, y, z ≦ 1, x + y + z = 1) and the composition ratios a, b and c and the semiconductors of all compositions in which x, y and z are changed within respective ranges are basically included. To do. Furthermore, In, which is a group III element,
Also included are those in which a part of Al and Ga are replaced with B, and those in which a part of the V group elements N, As and P are replaced with Sb. In the present invention, in the above chemical formula,
A GaAs-based semiconductor compound in which c and y are not 0 is preferable. More preferably, the chemical formula Al b Ga c As (0 ≦ b
In the case of <1,0 <c ≦ 1, b + c = 1), the semiconductor compounds having all the compositions in which the composition ratios b and c are changed within the respective ranges are included.

【００１５】上記III−Ｖ族半導化合物は、任意のドー
パントを含むものであっても良い。ｎ型不純物として、
Ｓｉ、Ｇｅ、Ｓｅ、Ｔｅ、Ｃ等を用いることができる。
ｐ型不純物として、Ｍｇ、Ｚｎ、Ｂｅ、Ｃａ、Ｓｒ、Ｂ
ａ等を用いることができる。なお、かかるｐ型不純物を
ドープしたのみではIII−Ｖ族化合物半導体を低抵抗の
ｐ型半導体とすることは困難であり、ｐ型不純物をドー
プした後にIII−Ｖ族化合物半導体を電子線照射、プラ
ズマ照射または炉による加熱にさらすことが好ましい。The III-V group semiconductor compound may include any dopant. As an n-type impurity,
Si, Ge, Se, Te, C or the like can be used.
As p-type impurities, Mg, Zn, Be, Ca, Sr, B
a or the like can be used. It is difficult to make the III-V group compound semiconductor into a low-resistance p-type semiconductor only by doping the p-type impurity. Therefore, after the p-type impurity is doped, the III-V group compound semiconductor is irradiated with an electron beam. Exposure to plasma irradiation or heating by a furnace is preferred.

【００１６】本発明の半導体装置用電極は、上述のノン
アロイ電極がメタル剥れ保護層で被覆されていることを
特長とする。上記メタル剥れ保護層は、（ａ）導電性
で、かつ（ｂ）ノンアロイ電極を構成する金属、特にノ
ンアロイ電極の最表層を構成する金属、または／および
ノンアロイ電極が形成されている半導体層もしくは基板
と、接着性の良いものが好ましい。メタル剥れ保護層を
構成する材料としては、上記特長を有していれば特に限
定されず、公知の材料を用いてよい。The semiconductor device electrode of the present invention is characterized in that the non-alloy electrode described above is covered with a metal peeling protection layer. The metal peeling protection layer is (a) electrically conductive and (b) a metal forming the non-alloy electrode, particularly a metal forming the outermost layer of the non-alloy electrode, or / and a semiconductor layer on which the non-alloy electrode is formed, or It is preferable that it has good adhesion to the substrate. The material forming the metal peeling protection layer is not particularly limited as long as it has the above characteristics, and known materials may be used.

【００１７】本発明において、上記メタル剥れ保護層は
アロイ系金属膜であることが好ましい。アロイ系金属と
は、熱処理により拡散しやすく、合金化しやすい性質を
有する金属をいう。具体的に、アロイ系金属としては、
金、チタン、ニッケル、クロム、銀、アルミニウム、マ
グネシウム、鉛もしくは鉄、またはそれらの合金などが
挙げられる。アロイ系金属としては、上記のものに限定
されず、熱拡散率の大きい金属であれば、本発明におい
て用いることができる。ここで、金属薄膜の熱拡散率の
測定方法は確立されていないので熱拡散率の具体的な数
値を上げることはできないが、将来かかる方法が確立さ
れたときに、上記具体的に例示した金属のうち、最も熱
拡散率が低い金属における熱拡散率の値よりも熱拡散率
の大きい金属は、本発明で用いる「アロイ系金属」とし
て挙げられる。In the present invention, the metal peeling protection layer is preferably an alloy type metal film. The alloy-based metal is a metal that has a property of being easily diffused by heat treatment and easily alloyed. Specifically, as an alloy metal,
Examples thereof include gold, titanium, nickel, chromium, silver, aluminum, magnesium, lead or iron, or alloys thereof. The alloy metal is not limited to the above, and any metal having a large thermal diffusivity can be used in the present invention. Here, since a method for measuring the thermal diffusivity of the metal thin film has not been established, it is not possible to raise a specific value for the thermal diffusivity, but when such a method was established in the future, the metal specifically exemplified above will be used. Among them, the metal having the larger thermal diffusivity than the value of the thermal diffusivity of the metal having the lowest thermal diffusivity is mentioned as the “alloy metal” used in the present invention.

【００１８】本発明において、メタル剥れ保護層による
被覆は、ノンアロイ電極の一部に施されているだけであ
ってもよいが、メタル剥れの低減という本発明の目的か
らは、ノンアロイ電極の全面においてメタル剥れ保護層
による被覆が施されていることが好ましい。また、メタ
ル剥れ保護層の厚さは特に限定されないが、半導体装置
の製造工程におけるフルカットまたはダイシングなどの
切り分け工程に影響を与えない程度であることが好まし
い。具体的に、メタル剥れ保護層の厚さは約１〜５０μ
ｍ程度、好ましくは約１〜１０μｍ程度、より好ましく
は約２〜５μｍ程度が好適である。さらに、メタル剥れ
保護層は、同一または異なった材料からなる層が複数層
積層されていてもよいが、製造の容易性などの観点から
一層であることが好ましい。また、メタル剥れ保護層
は、通常は、半導体装置の最外層を形成する。In the present invention, the coating with the metal peeling protection layer may be applied only to a part of the non-alloy electrode, but for the purpose of the present invention of reducing metal peeling, the non-alloy electrode is covered. It is preferable that the entire surface is covered with a metal peeling protection layer. The thickness of the metal peeling protection layer is not particularly limited, but it is preferable that the metal peeling protection layer does not affect the cutting process such as full cutting or dicing in the manufacturing process of the semiconductor device. Specifically, the thickness of the metal peeling protection layer is about 1 to 50 μm.
m, preferably about 1 to 10 μm, more preferably about 2 to 5 μm. Further, the metal peeling protection layer may be formed by laminating a plurality of layers made of the same or different materials, but one layer is preferable from the viewpoint of ease of production. The metal peeling protection layer usually forms the outermost layer of the semiconductor device.

【００１９】本発明に係る半導体装置用電極は、公知の
方法を用いて形成することができる。半導体装置用電極
の形成方法の好ましい態様としては、具体的には、
（ａ）半導体層または基板上にノンアロイ電極を形成
し、（ｂ）ついで前記ノンアロイ電極上にメタル剥れ保
護層を形成し、（ｃ）その後所望により熱処理を行うと
いう方法が挙げられる。The semiconductor device electrode according to the present invention can be formed by a known method. As a preferred embodiment of the method for forming an electrode for a semiconductor device, specifically,
(A) A non-alloy electrode is formed on the semiconductor layer or the substrate, (b) a metal peeling protection layer is then formed on the non-alloy electrode, and (c) a heat treatment is then performed, if desired.

【００２０】半導体層または基板上にノンアロイ電極を
形成する方法は、当技術分野において十分確立されてい
るので、それに従ってよい。具体的には、蒸着、好まし
くは真空蒸着により、ノンアロイ電極を形成するのが好
適である。真空蒸着は、半導体層または基板と電極の界
面に不純物が混入する可能性が少なく、また、半導体層
または基板面内に均一な厚みで電極層を形成できる簡便
な方法だからである。Methods for forming non-alloy electrodes on semiconductor layers or substrates are well established in the art and may be followed. Specifically, it is suitable to form the non-alloy electrode by vapor deposition, preferably vacuum vapor deposition. This is because the vacuum deposition is less likely to have impurities mixed in the interface between the semiconductor layer or the substrate and the electrode, and is a simple method that can form the electrode layer with a uniform thickness in the plane of the semiconductor layer or the substrate.

【００２１】ノンアロイ電極上にメタル剥れ保護層を形
成する方法も、メタル剥れ保護層を構成する材料に応じ
て公知方法を用いてよい。例えばメタル剥れ保護層がア
ロイ系金属膜である場合は、公知の薄膜形成方法を用い
ることができる。かかる薄膜形成方法としては、具体的
に、例えばハライド気相成長法、分子線エピタキシー
（Molecular Beam Epitaxy；ＭＢＥ）法、スパッタリン
グもしくは真空蒸着などの物理気相成長（ＰＶＤ）法；
ＶＰＥ(Vapor Phase Epitaxy)法；有機金属気層成長
（ＭＯＣＶＤ）法などの化学気相成長（ＣＶＤ）法；ま
たは液相エピタキシ（ＬＰＥ）法等が挙げられる。中で
も、スパッタリングを用いることが、設備投資および使
用原料が少なくて済むことから好ましい。As the method for forming the metal peeling protection layer on the non-alloy electrode, a known method may be used depending on the material constituting the metal peeling protection layer. For example, when the metal peeling protection layer is an alloy type metal film, a known thin film forming method can be used. Specific examples of such a thin film forming method include a halide vapor deposition method, a molecular beam epitaxy (MBE) method, and a physical vapor deposition (PVD) method such as sputtering or vacuum deposition;
VPE (Vapor Phase Epitaxy) method; chemical vapor deposition (CVD) method such as metal organic chemical vapor deposition (MOCVD) method; or liquid phase epitaxy (LPE) method. Above all, it is preferable to use sputtering because it requires less capital investment and less raw materials.

【００２２】その後、熱処理を行うことが好ましい。熱
を加えることにより、ノンアロイ電極において密着性の
悪い島状部分をメタル剥れ保護層により三次元的に抑え
ることができ、外圧や力によるメタル剥れをより効果的
に抑制することができる。熱処理は、半導体装置の製造
工程において、電極形成後、フルカットまたはダイシン
グの前に通常行われる熱処理と同様の条件に従って行え
ばよい。After that, it is preferable to perform heat treatment. By applying heat, it is possible to three-dimensionally suppress the island-shaped portion having poor adhesion in the non-alloy electrode by the metal peeling protection layer, and it is possible to more effectively suppress metal peeling due to external pressure or force. The heat treatment may be performed under the same conditions as the heat treatment usually performed after the electrodes are formed and before full cutting or dicing in the manufacturing process of the semiconductor device.

【００２３】本発明に係る半導体装置用電極の形成方法
のより好ましい態様としては、（ａ）半導体層または基
板上に蒸着によりノンアロイ電極を形成する工程と、
（ｂ）半導体層または基板上のノンアロイ電極に電極パ
ターンを形成する工程と、（ｃ）分離された個々のノン
アロイ電極上にメタル剥れ保護層を形成する工程と、
（ｄ）所望により熱処理を行う工程とからなる方法が挙
げられる。In a more preferred embodiment of the method for forming an electrode for a semiconductor device according to the present invention, (a) a step of forming a non-alloy electrode on a semiconductor layer or a substrate by vapor deposition,
(B) a step of forming an electrode pattern on the non-alloy electrode on the semiconductor layer or the substrate, and (c) a step of forming a metal peeling protection layer on each of the separated non-alloy electrodes.
(D) A method including a step of performing heat treatment if desired.

【００２４】半導体装置の製造工程において、電極形成
後にフルカットやダイシングを行うことを鑑みれば、上
記（ｂ）半導体層または基板上のノンアロイ電極に電極
パターンを形成する工程を施すことが好ましい。上記電
極パターンを形成する工程は、公知の方法に従ってよ
い。例えば、（ａ）ネガレジスト膜を用いたフォトリソ
グラフィーとリフトオフとの組み合わせにより、または
（ｂ）フォトリソグラフィーとエッチングとの組み合わ
せにより、所望の電極パターンを容易に形成することが
できる。In view of performing full cutting and dicing after forming electrodes in the manufacturing process of the semiconductor device, it is preferable to perform the above step (b) of forming an electrode pattern on the non-alloy electrode on the semiconductor layer or the substrate. The step of forming the electrode pattern may be according to a known method. For example, a desired electrode pattern can be easily formed by (a) a combination of photolithography using a negative resist film and lift-off, or (b) a combination of photolithography and etching.

【００２５】本発明に係る半導体装置用電極およびその
形成方法の具体的態様を、図１を用いて以下に示す。し
かし、本発明はこれに限定されないことは言うまでもな
い。まず、図１（ａ）に示すように、ｐ型ＧａＡｓ基板
１上にネガフォトレジストを塗布し、レジスト膜２を形
成する。その後、図１（ｂ）に示すように、このレジス
ト膜２をフォトリソグラフィー法によりパターニング
し、形成すべきノンアロイ電極に対応する部分に開口を
有するレジストパターンを形成する。かかるレジストパ
ターンの形成前に予めネガレジスト膜の表面をブロムベ
ンゼンで処理することが好ましい。かかるブロムベンゼ
ン処理により、図１（ｂ）に示すようなオーバーハング
構造を作ることができる。また、レジストパターンにお
けるレジスト膜２の厚さは後述するチタン膜、白金膜お
よび金膜の膜積層構造からなるノンアロイ電極の厚さよ
りも十分に大きくなるように選択する。さらに、本工程
において、フォトリソグラフィーにおける露光は、例え
ば縮小投影露光装置（いわゆるステッパー）のような光
学式露光装置を用いて行われるのが好ましい。なお、上
記レジストパターンの形成は、電子線レジストと電子ビ
ームリソグラフィー法とを用いて行うこともできる。Specific embodiments of the semiconductor device electrode and the method for forming the same according to the present invention will be described below with reference to FIG. However, it goes without saying that the present invention is not limited to this. First, as shown in FIG. 1A, a negative photoresist is applied on the p-type GaAs substrate 1 to form a resist film 2. Thereafter, as shown in FIG. 1B, the resist film 2 is patterned by a photolithography method to form a resist pattern having an opening at a portion corresponding to the non-alloy electrode to be formed. It is preferable to treat the surface of the negative resist film with brombenzene in advance before forming such a resist pattern. The bromine treatment makes it possible to form an overhang structure as shown in FIG. Further, the thickness of the resist film 2 in the resist pattern is selected to be sufficiently larger than the thickness of the non-alloy electrode having a film laminated structure of a titanium film, a platinum film and a gold film described later. Further, in this step, exposure in photolithography is preferably performed using an optical exposure apparatus such as a reduction projection exposure apparatus (so-called stepper). The resist pattern can also be formed using an electron beam resist and an electron beam lithography method.

【００２６】ついで、図１（ｃ）に示すように、真空蒸
着によりチタン膜３を全面に形成し、引き続いて同じく
真空蒸着により白金膜４を、さらに金膜５を全面に形成
する。ここで、全面とは、レジスト膜２上および、レジ
スト膜２でマスクされていないｐ型ＧａＡｓ基板１上を
いう。ついで、例えばアセトンのような有機溶剤に浸け
てレジスト膜２を溶解除去することにより、このレジス
ト膜２上に形成されたチタン膜３、白金膜４および金膜
５を除去する。この結果、図１（ｄ）に示すように、レ
ジストパターンの開口部に対応する部分におけるｐ型Ｇ
ａＡｓ基板１上にのみ、チタン膜３、白金膜４および金
膜５の積層構造からなるノンアロイ電極が残される。Then, as shown in FIG. 1C, a titanium film 3 is formed on the entire surface by vacuum evaporation, and subsequently a platinum film 4 and a gold film 5 are formed on the entire surface by vacuum evaporation as well. Here, the entire surface refers to the resist film 2 and the p-type GaAs substrate 1 not masked by the resist film 2. Then, the resist film 2 is dissolved and removed by immersing it in an organic solvent such as acetone to remove the titanium film 3, the platinum film 4 and the gold film 5 formed on the resist film 2. As a result, as shown in FIG. 1D, the p-type G in the portion corresponding to the opening of the resist pattern is formed.
Only on the aAs substrate 1, the non-alloy electrode having the laminated structure of the titanium film 3, the platinum film 4, and the gold film 5 is left.

【００２７】ついで、図１（ｅ）に示すように、上記の
ようにパターニングされた個々のノンアロイ電極の上を
金の薄膜で被覆する。このとき、金膜の厚さは約５μｍ
程度が好適である。金の薄膜の形成方法は、Ａｕスパッ
タコーターなどを用いるのが、薄膜の形成工程の容易
性、使用原料の量の観点から好ましい。その後、熱処理
を施すのが好ましい。熱処理としては、例えばＲＴＡ
（RapidThermal Annealing）法や一般的な電気炉による
方法により、例えば約５００〜６００℃程度の温度で、
短時間、例えば１秒〜数分間程度を行うことが好まし
い。この熱処理の際の雰囲気としては、例えばＮ２ガス
または微量のＨ２ガスを添加したＮ２ガスから成る雰囲
気を用いるのが好ましい。ついで、図１（ｆ）に示すよ
うに、半導体装置（半導体素子）ごとに切り分けられ
る。また、ダイシングにより素子分離されることもあ
る。Then, as shown in FIG. 1 (e), a gold thin film is coated on the individual non-alloy electrodes patterned as described above. At this time, the thickness of the gold film is about 5 μm
The degree is suitable. As a method of forming a gold thin film, it is preferable to use an Au sputter coater or the like from the viewpoint of the ease of forming the thin film and the amount of raw materials used. After that, it is preferable to perform heat treatment. As the heat treatment, for example, RTA
(Rapid Thermal Annealing) method or a method using a general electric furnace, for example, at a temperature of about 500 to 600 ° C.
It is preferable to perform it for a short time, for example, for about 1 second to several minutes. The atmosphere during the heat treatment, preferably for example to use an atmosphere composed of N 2 gas added with H 2 gas of the N 2 gas or trace. Then, as shown in FIG. 1F, the semiconductor device (semiconductor element) is cut into individual pieces. Further, the elements may be separated by dicing.

【００２８】上述の本発明に係る電極は、種々の半導体
装置に応用することができる。本発明に係る半導体装置
としては、特に限定されないが、例えば半導体レーザも
しくは発光ダイオードなどの発光装置、またはバイポー
ラトランジスタ（ＨＢＴ），電界効果トランジスタ（Ｆ
ＥＴ）もしくは高移動度トランジスタ（ＨＥＭＴ）など
のトランジスタなどが挙げられる。The electrode according to the present invention described above can be applied to various semiconductor devices. The semiconductor device according to the present invention is not particularly limited, but for example, a light emitting device such as a semiconductor laser or a light emitting diode, a bipolar transistor (HBT), a field effect transistor (F).
ET) or a transistor such as a high mobility transistor (HEMT).

【００２９】本発明に係る半導体装置においては、ｐ型
電極およびｎ型電極ともに本発明に係る電極が用いられ
ていてもよいし、いずれか片方のみに本発明に係る電極
が用いられていてもよい。好ましくは、ｐ型電極に本発
明に係る電極を用いるのが好適である。また、本発明に
係る半導体装置が半導体レーザである場合は、基板側の
電極として本発明に係る電極が用いられているのが好適
である。なぜなら、上述したように、基板側の電極はフ
ルカットやダイシングする際の表側となり、また、ワイ
ヤボンドを打つ側にもなり、損傷を受けやすいため、本
発明に係る電極のようにメタル剥れが起きにくい構造の
電極を用いるほうが、製品不良が生じにくいからであ
る。In the semiconductor device according to the present invention, the electrode according to the present invention may be used for both the p-type electrode and the n-type electrode, or the electrode according to the present invention may be used for only one of them. Good. Preferably, the electrode according to the present invention is used for the p-type electrode. Further, when the semiconductor device according to the present invention is a semiconductor laser, it is preferable that the electrode according to the present invention is used as the electrode on the substrate side. This is because, as described above, the electrode on the substrate side is the front side at the time of full cutting or dicing, and also the side for hitting the wire bond, and is easily damaged, so that metal peeling like the electrode according to the present invention occurs. This is because product defects are less likely to occur when an electrode having a structure that does not easily cause

【００３０】本発明に係る半導体装置の具体的実施態様
として、本発明に係る電極を有するＧａＡｓ系半導体レ
ーザについて述べる。図２に、該ＧａＡｓ系半導体レー
ザの共振器長方向に垂直な断面模式図を示す。ＧａＡｓ
系半導体レーザにおいては、ｐ型ＧａＡｓ基板１１上に
Ａｌ０．７Ｇａ０．３Ａｓからなるｐ型クラッド層１２
が積層され、該ｐ型クラッド層１２上にＡｌ０．１Ｇａ
０．９Ａｓからなる活性層１３が積層され、該活性層１
３の上にＡｌ０．７Ｇａ０．３Ａｓからなるｎ型クラッ
ド層１４が積層されている。そして、この該ＧａＡｓ系
半導体レーザは、ｎ型クラッド層１４の上部にストライ
プ状の凸部が形成され、該ストライプ状の凸部の両端に
ＳｉＯ２の絶縁膜５からなる非電流注入領域が設けられ
ているという電流狭窄構造を有する。As a specific embodiment of the semiconductor device according to the present invention, a GaAs semiconductor laser having the electrode according to the present invention will be described. FIG. 2 shows a schematic cross-sectional view perpendicular to the cavity length direction of the GaAs semiconductor laser. GaAs
In the semiconductor laser, the p-type clad layer 12 made of Al 0.7 Ga 0.3 As is formed on the p-type GaAs substrate 11.
Of Al 0.1 Ga on the p-type cladding layer 12
The active layer 13 made of 0.9 As is laminated to form the active layer 1.
3 has an n-type clad layer 14 made of Al 0.7 Ga 0.3 As laminated thereon. In this GaAs semiconductor laser, stripe-shaped convex portions are formed on the upper portion of the n-type cladding layer 14, and non-current injection regions made of the insulating film 5 of SiO 2 are provided at both ends of the stripe-shaped convex portions. It has a current confinement structure.

【００３１】さらに、ｎ型クラッド層４および絶縁膜１
５の上に、ｎ型電極１６が設けられている。ｎ型電極１
６は、ｎ型クラッド層１４側からＡｕＧｅ合金、Ｎｉ、
Ａｕがこの順序で積層されているアロイ電極である。一
方、ｐ型ＧａＡｓ基板１１の裏面にはｐ型電極が設けら
れている。ｐ型電極は、基板側からＴｉ、Ｐｔ、Ａｕが
この順序で積層されているノンアロイ電極１７を、金膜
１８がその全面において被覆している本発明に係る電極
である。Further, the n-type cladding layer 4 and the insulating film 1
An n-type electrode 16 is provided on the electrode 5. n-type electrode 1
6 is AuGe alloy, Ni, from the n-type cladding layer 14 side.
Au is an alloy electrode laminated in this order. On the other hand, a p-type electrode is provided on the back surface of the p-type GaAs substrate 11. The p-type electrode is an electrode according to the present invention in which a non-alloy electrode 17 in which Ti, Pt, and Au are stacked in this order from the substrate side is covered with a gold film 18 on the entire surface.

【００３２】上記ｐ型電極についてより詳しく説明す
る。ノンアロイ電極１７に金膜１８を被覆する前の半導
体レーザの基板面の模式図を図３に記載する。半導体レ
ーザの横方向の大きさ（幅）は、約３００μｍ程度であ
る。また、半導体レーザの共振器長方向の大きさ（長
さ）は、約２００μｍ程度である。そして、電極のパタ
ーニングにより、半導体レーザの縁から約１０μｍ程度
はｐ型ＧａＡｓ基板１１がむき出しになっている。かか
る形状のノンアロイ電極１７を包み込むように金膜１８
が被覆している。すなわち、ノンアロイ電極１７だけで
なく、ｐ型ＧａＡｓ基板１１がむき出しなっている部分
にも金膜１８が形成されている。The p-type electrode will be described in more detail. A schematic view of the substrate surface of the semiconductor laser before coating the non-alloy electrode 17 with the gold film 18 is shown in FIG. The lateral size (width) of the semiconductor laser is about 300 μm. The size (length) of the semiconductor laser in the cavity length direction is about 200 μm. The p-type GaAs substrate 11 is exposed from the edge of the semiconductor laser by about 10 μm due to the patterning of the electrodes. The gold film 18 is formed so as to surround the non-alloy electrode 17 having such a shape.
Is covered. That is, the gold film 18 is formed not only on the non-alloy electrode 17 but also on the exposed portion of the p-type GaAs substrate 11.

【００３３】[0033]

【発明の効果】本発明に係る半導体装置用電極において
は、ノンアロイ電極がメタル剥れ保護層で被覆されてい
るので、電極を構成する金属、特にノンアロイ系金属の
密着性を向上することができ、その結果、従来ノンアロ
イ電極で問題となっていた半導体装置の製造工程におけ
るメタル剥れを低減することができる。また、本発明に
係る半導体装置は、特に電極形成後のフルカットやダイ
シングなどの製造工程においてメタル剥れが少ない。そ
の結果、製造工程下流の歩留まりが向上し、例えばヒー
トシンク、サブマウント、金ワイヤーなどの投入量が低
減できる。すなわち、本発明によって、半導体装置の製
造の効率化、コストダウンを図ることができる。In the electrode for a semiconductor device according to the present invention, the non-alloy electrode is covered with the metal peeling protection layer, so that the adhesion of the metal constituting the electrode, especially the non-alloy type metal can be improved. As a result, it is possible to reduce metal peeling in the manufacturing process of a semiconductor device, which has been a problem in the conventional non-alloy electrode. In addition, the semiconductor device according to the present invention has less metal peeling particularly in manufacturing processes such as full cutting and dicing after forming electrodes. As a result, the yield in the downstream of the manufacturing process is improved, and the input amount of heat sink, submount, gold wire, etc. can be reduced. That is, according to the present invention, it is possible to improve the efficiency of manufacturing a semiconductor device and reduce the cost.

【００３４】さらに、本発明に係る電極を基板側の電極
として用いている半導体レーザにおいては、基板側から
の熱の放散が良好となるという利点もある。その結果、
半導体レーザの発熱による電気特性の変化などを防止す
ることができ、半導体レーザの信頼性の向上を図ること
ができる。Further, in the semiconductor laser using the electrode according to the present invention as the electrode on the substrate side, there is also an advantage that the heat dissipation from the substrate side is good. as a result,
It is possible to prevent changes in electrical characteristics due to heat generation of the semiconductor laser, and to improve reliability of the semiconductor laser.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明に係る電極の製造工程を示す模式図で
ある。FIG. 1 is a schematic view showing a manufacturing process of an electrode according to the present invention.

【図２】 本発明に係る半導体装置の代表例であるＧａ
Ａｓ系半導体レーザの共振器長方向に垂直な断面模式図
である。FIG. 2 is a typical example of a semiconductor device according to the present invention, Ga.
It is a cross-sectional schematic diagram perpendicular to the cavity length direction of an As type semiconductor laser.

【図３】 ノンアロイ電極に金膜を被覆する前の図２に
示した半導体レーザの基板面の模式図である。3 is a schematic view of a substrate surface of the semiconductor laser shown in FIG. 2 before a non-alloy electrode is coated with a gold film.

【符号の説明】[Explanation of symbols]

１ ｐ型ＧａＡｓ基板 ２ レジスト膜 ３ チタン膜 ４ 白金膜 ５ 金膜 ６ ノンアロイ電極 ７ 金膜 ８ 半導体装置 １１ ｐ型ＧａＡｓ基板 １２ ｐ型クラッド層 １３ 活性層 １４ ｎ型クラッド層 １５ 絶縁膜 １６ ｎ型電極 １７ ノンアロイ電極 １８ 金膜 1 p-type GaAs substrate 2 Resist film 3 Titanium film 4 Platinum film 5 gold film 6 Non-alloy electrode 7 gold film 8 Semiconductor devices 11 p-type GaAs substrate 12 p-type clad layer 13 Active layer 14 n-type clad layer 15 Insulating film 16 n-type electrode 17 Non-alloy electrode 18 gold film

フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｓ 5/02 Ｈ０１Ｌ 21/90 Ｄ ５Ｆ０７３ Ｆターム(参考） 4K029 AA04 AA06 AA24 BA02 BA03 BA04 BA05 BA07 BA09 BA12 BA13 BA17 BB02 BC03 BD02 CA01 CA05 4M104 AA04 AA05 BB15 CC01 DD37 FF13 GG04 GG06 GG08 GG12 HH08 5F033 GG02 HH07 HH08 HH13 HH14 HH17 HH18 MM05 PP15 PP19 PP20 QQ42 QQ73 XX13 5F041 AA25 AA43 CA82 CA92 DA07 5F044 EE04 EE12 5F073 CB22 DA30 EA28 FA27 Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01S 5/02 H01L 21/90 D 5F073 F term (reference) 4K029 AA04 AA06 AA24 BA02 BA03 BA04 BA05 BA07 BA09 BA12 BA13 BA17 BB02 BC03 BD02 CA01 CA05 4M104 AA04 AA05 BB15 CC01 DD37 FF13 GG04 GG06 GG08 GG12 HH08 5F033 GG02 HH07 HH08 HH13 HH14 HH17 HH18 MM05 PP15 PP19 PP20 QQ42 QQ73 XX13 5F041 AA25 A074FQ4AQ4

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 半導体層または基板に形成されているノ
ンアロイ電極がメタル剥れ保護層で被覆されていること
を特徴とする半導体装置用電極。1. An electrode for a semiconductor device, wherein a non-alloy electrode formed on a semiconductor layer or a substrate is covered with a metal peeling protection layer. 【請求項２】 メタル剥れ保護層が、アロイ系金属膜で
あることを特徴とする請求項１に記載の半導体装置用電
極。2. The electrode for a semiconductor device according to claim 1, wherein the metal peeling protection layer is an alloy metal film. 【請求項３】 アロイ系金属が、金、チタン、ニッケ
ル、クロム、銀、アルミニウム、マグネシウム、鉛およ
び鉄から選ばれる少なくとも１種類の金属であることを
特徴とする請求項２に記載の半導体装置用電極。3. The semiconductor device according to claim 2, wherein the alloy-based metal is at least one metal selected from gold, titanium, nickel, chromium, silver, aluminum, magnesium, lead and iron. Electrodes. 【請求項４】 ノンアロイ電極が、白金膜を含む膜積層
構造を有することを特徴とする請求項１に記載の半導体
装置用電極。4. The electrode for a semiconductor device according to claim 1, wherein the non-alloy electrode has a film laminated structure including a platinum film. 【請求項５】 ノンアロイ電極が、半導体層または基板
側からチタン膜、白金膜、金膜がこの順序で積層されて
いることを特徴とする請求項４に記載の半導体装置用電
極。5. The electrode for a semiconductor device according to claim 4, wherein the non-alloy electrode has a titanium film, a platinum film, and a gold film stacked in this order from the semiconductor layer or substrate side. 【請求項６】 半導体層または基板が、ｐ型であること
を特徴とする請求項１に記載の半導体装置用電極。6. The electrode for a semiconductor device according to claim 1, wherein the semiconductor layer or the substrate is p-type. 【請求項７】 半導体層または基板が、III−Ｖ族半導
体化合物からなることを特徴とする請求項１に記載の半
導体装置。7. The semiconductor device according to claim 1, wherein the semiconductor layer or the substrate is made of a III-V group semiconductor compound. 【請求項８】 請求項１に記載の電極を有することを特
徴とする半導体装置。8. A semiconductor device comprising the electrode according to claim 1. 【請求項９】 半導体装置が、半導体レーザ、発光ダイ
オードまたはトランジスタであることを特徴とする請求
項８に記載の半導体装置。9. The semiconductor device according to claim 8, wherein the semiconductor device is a semiconductor laser, a light emitting diode or a transistor. 【請求項１０】 （ａ）半導体層または基板に蒸着によ
りノンアロイ電極を形成する工程と、（ｂ）前記ノンア
ロイ電極上にメタル剥れ保護層を形成する工程と、
（ｃ）所望により熱処理を行う工程とを含むことを特徴
とする半導体装置用電極の形成方法。10. A step of forming a non-alloy electrode on a semiconductor layer or a substrate by vapor deposition, and a step of forming a metal peeling protection layer on the non-alloy electrode.
(C) A step of performing heat treatment as desired, and a method of forming an electrode for a semiconductor device. 【請求項１１】 （ａ）半導体層または基板に蒸着によ
りノンアロイ電極を形成する工程と、（ｂ）半導体層ま
たは基板に形成されたノンアロイ電極に電極パターンを
形成する工程と、（ｃ）電極パターンにより分離された
個々のノンアロイ電極上にメタル剥れ保護層を形成する
工程と、（ｄ）所望により熱処理を行う工程を含むこと
とを特徴とする半導体装置用電極の形成方法。11. A process of forming a non-alloy electrode on a semiconductor layer or a substrate by vapor deposition, a process of forming an electrode pattern on the non-alloy electrode formed on a semiconductor layer or a substrate, and a process of forming an electrode pattern on the non-alloy electrode. A method for forming an electrode for a semiconductor device, comprising: a step of forming a metal peeling protection layer on each of the non-alloy electrodes separated by the step (d); and a step (d) of heat treatment. 【請求項１２】 メタル剥れ保護層を形成する工程が、
アロイ系金属膜をスパッタリングにより製膜する工程で
あることを特徴とする請求項１０または１１に記載の半
導体装置用電極の形成方法。12. The step of forming a metal peeling protection layer comprises:
The method for forming an electrode for a semiconductor device according to claim 10 or 11, which is a step of forming an alloy metal film by sputtering.
JP2001252087A 2001-08-22 2001-08-22 Electrode for semiconductor device Pending JP2003068671A (en)

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009252775A (en) * 2008-04-01 2009-10-29 National Institute Of Advanced Industrial & Technology Structure for protecting junction between diamond surface and metal piece
JP2013138209A (en) * 2011-12-27 2013-07-11 Advanced Optoelectronic Technology Inc Light-emitting diode package manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009252775A (en) * 2008-04-01 2009-10-29 National Institute Of Advanced Industrial & Technology Structure for protecting junction between diamond surface and metal piece
JP2013138209A (en) * 2011-12-27 2013-07-11 Advanced Optoelectronic Technology Inc Light-emitting diode package manufacturing method

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