JPH05166849A - Semiconductor element - Google Patents

Abstract

PURPOSE:To obtain the title semiconductor element wherein the contact heat resistance of a semiconductor substrate with a PHS is reduced and the operating temperature of the element is lowered by a method wherein the following are formed: protruding and recessed parts which are formed on the rear side of the semiconductor substrate and whose depth does not reach an action region; and a metal layer for heat-dissipating use which is formed on the protruding and recessed parts so as to come into close contact with them. CONSTITUTION:The title semiconductor element is provided with the following: an action region 11 which is formed on one main face side of a semiconductor substrate 10; protruding and recessed parts which are formed on the other main face side of the semiconductor substrate 10 and whose depth does not reach the action region 11; and a metal layer 17 for heat-dissipating use which is formed on the protruding and recessed parts so as to come into close contact with them. For example, an n-type action layer 11, a source electrode 12s, a drain electrode 12d and a gate electrode 13 are formed on a semi-insulating GaAs substrate 10. Then, the substrate 10 is polished from the rear so as to obtain a thickness of 30mum; after that, the rear is etched selectively by an RIE method; grooves whose width and interval (w) are 2mum and whose depth (d) is 2mum are formed. Then, the rear is plated with Au whose thickness is 30mum; a PHS 17 is formed; a high-output GaAs FET is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high power gallium arsenide field effect transistor (hereinafter referred to as G
It is related to the structure of aAsFET (abbreviation).

[0002]

2. Description of the Related Art A high power semiconductor device generates a large amount of heat during operation. This heat often causes a reduction in output and a deterioration in reliability, and sometimes causes thermal runaway to destroy the device. Therefore, to improve heat dissipation as much as possible,
It is the key to improve the device performance including reliability. Particularly in a high-power GaAs FET, the heat resistance of the material itself is higher than that of an element made of a material such as Si, so that heat dissipation is poor, which is one of the factors that hinder high integration.

One of the conventional methods for improving heat dissipation has been to cut a semiconductor substrate having a high thermal resistance as thin as possible. Here, conventional high-power GaAs
The sectional structure of the FET is shown in FIG. In the figure, 300 is a semi-insulating GaAs substrate, and usually has a thickness of about 30 to 50 μm. An n-type operating layer 301 on the semi-insulating substrate 300,
A source electrode 302s, a drain electrode 302d, and a gate electrode 303 are formed, and the n-type operating layer 301 is in operation.
An electric current flows through and heat is generated. Semi-insulating GaAs substrate 3
Below 00, PHS (Plated Heat Sin)
The metal layer 307 for heat dissipation called k) is mainly composed of Au.
It is common to form such a material with a thickness of about 30 to 50 μm. Since the element is fixed to the circuit board or the enclosure by soldering via the metal layer 307,
The heat generated from the n-type operating layer 301 is generated by the semi-insulating substrate 300.
Is emitted to the outside through the metal layer 307.

[0004]

The thermal resistance of the device is mainly determined by the thermal resistance of the semi-insulating GaAs substrate 300 (hereinafter abbreviated as substrate) and the thermal resistance of the contact portion between the substrate and PHS. The thinner the substrate is, and the larger the contact area between the substrate and PHS is, the lower the thermal resistance is, so that the operating temperature can be lowered and a high performance element can be obtained.

However, it is almost the limit to reduce the thickness of the substrate due to restrictions on the strength of the substrate in the manufacturing process, handling problems after completion of the element, etc. It is difficult to lower. Also, the substrate and PH
If the size of the element is simply increased in order to increase the contact area of S, there is a problem that the mounting density is reduced.

In order to solve the above problems, it is an object of the present invention to provide a semiconductor device having a structure in which the contact thermal resistance between the semiconductor substrate and PHS is reduced and the operating temperature of the device is lowered.

[0007]

A semiconductor device according to the present invention has an operating region formed on one main surface side of a semiconductor substrate and an operating region formed on the other main surface side of the semiconductor substrate. It is characterized in that it is provided with an uneven surface portion having a depth which does not exist and a heat dissipation metal layer formed in close contact with the uneven surface portion.

[0008]

The semiconductor device according to the present invention can increase the contact area between the PHS and the semiconductor substrate while maintaining the size of the element by providing the semiconductor substrate with irregularities. As a result, the contact thermal resistance between the semiconductor substrate and PHS is reduced and the operating temperature of the device is lowered, so that good performance is obtained.

[0009]

(Embodiment 1) Hereinafter, the structure of a high-power GaAs FET according to an embodiment of the present invention is shown in a sectional view in FIG. 1, and a method of forming the same is shown in FIG. 2 and FIG. Indicate.

As shown in FIG. 1, the structure of an example of a high-power GaAs FET has a semi-insulating GaAs substrate 10 in which a groove having a depth d and a width w is formed on a surface in contact with the PHS 17 at intervals w.
Is formed by. In this case, the semi-insulating GaAs substrate 10 and the PHS 11 are formed by forming a groove having a size of d = w.
The contact area of is twice as large as that when the groove is not formed.

Next, the manufacturing process of the structure of the high-power GaAs FET of one embodiment will be described with reference to FIGS. 2 and 3.

First, an n-type impurity is implanted at a predetermined position on the semi-insulating GaAs substrate 200 by, for example, an ion implantation method, and then a heat treatment for activating the impurity is performed to form an n-type operating layer 201 (see FIG. 2 (a)).

Next, the source electrode 202s and the drain electrode 202d are formed by using a known photolithography technique, lift-off method or the like, and alloying is performed by heat treatment to obtain ohmic contact (FIG. 2B).

Next, the gate electrode 203 is formed using the well-known photolithography technique and lift-off method (FIG. 2C).

Next, the semi-insulating GaAs substrate 200 is polished from the back surface so that the thickness is, for example, 30 μm, then photoresist layers 204a and 204b are applied to the front surface and the back surface, and the photoresist layer at predetermined positions on the back surface. 204b is exposed to form an opening 205 having a width of 2 μm, for example (FIG. 3A).

Next, the semi-insulating substrate 200 is selectively etched and removed by, for example, RIE (reactive ion etching) method to form a groove 206 having a width of 2 μm and a depth of 2 μm (FIG. 3B).

Finally, the back surface of the semi-insulating GaAs substrate 200 is plated with Au to a thickness of 30 μm, and P is formed.
The HS 207 is formed, and the high power GaAs FET is completed (FIG. 3C).

Although the present invention has been described by taking the GaAs FET as an example, the present invention is not limited to this and can be similarly applied to other semiconductor materials.

Further, although the irregularities formed on the back surface of the semiconductor substrate are described here as linear grooves formed in parallel with each other, the grooves may have a curved plane shape, or each groove may have a curved shape. You may cross. Furthermore, the cross-sectional shape does not have to be rectangular as shown in this embodiment, and may be triangular, semicircular, mesa-shaped, or the like.

[0020]

As described above, according to the present invention, it becomes possible to manufacture an element having a low thermal resistance without changing the size of the element, and it is possible to reduce the output of a high output element and the deterioration of reliability. Can be prevented.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of an embodiment of a high-power GaAs FET according to the present invention.

2A to 2C are cross-sectional views showing a step-by-step manufacturing process of a GaAs FET according to an embodiment of the present invention.

3A to 3C are cross-sectional views showing a manufacturing process of a GaAs FET of one embodiment according to the present invention in the order of processes subsequent to FIG.

FIG. 4 is a sectional view showing the structure of a conventional GaAs FET.

[Explanation of symbols]

 10, 200, 300 semi-insulating GaAs substrate 11, 201, 301 n-type operating layer 12s, 202s, 302s source electrode 12d, 202d, 302d drain electrode 13, 203, 303 gate electrode 205 resist opening 206 groove 17, 207, 307 PHS

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 23/36 29/44 C 7738-4M

Claims (1)

[Claims] 1. An operating region formed on one main surface side of a semiconductor substrate, an uneven surface portion formed on the other main surface side of the semiconductor substrate and having a depth not reaching the operating region, and the uneven surface portion. A semiconductor element comprising a heat-dissipating metal layer formed in close contact.