JPS6123350A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6123350A JPS6123350A JP14468884A JP14468884A JPS6123350A JP S6123350 A JPS6123350 A JP S6123350A JP 14468884 A JP14468884 A JP 14468884A JP 14468884 A JP14468884 A JP 14468884A JP S6123350 A JPS6123350 A JP S6123350A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pellet
- active region
- gaas
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000008188 pellet Substances 0.000 abstract description 24
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 18
- 230000008094 contradictory effect Effects 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 230000020169 heat generation Effects 0.000 abstract description 3
- 229910052709 silver Inorganic materials 0.000 abstract description 3
- 238000007747 plating Methods 0.000 abstract description 2
- 230000001629 suppression Effects 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000005855 radiation Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000009278 visceral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野） ゛一本発明は半
導体装置の形状、特に放熱効果の改善された基板形状に
′関するものである。 □（従来の技術）
一般に、高出力ＧａＡｓショットキー接合ゲート轍−葬
効巣トランジスタ（以゛下、ＭＥ８ＦＥＴという）のベ
レット構造は、以下に示す”様−に二種類に大別゛でき
る゛。 ′］ ・ｌａ） 厚
さ４００〜５００μｍのＧ ａ Ａ ｓウニ／’−表面
にＰＥＴとして必要な電極、パッシベーション膜を形成
し、その後機械的研摩によ、！＞ｔＳＯμｍ程度まで薄
くする。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the shape of a semiconductor device, particularly to a substrate shape with improved heat dissipation effect. □ (Prior Art) In general, the bullet structure of a high-power GaAs Schottky junction gate rut-effect transistor (hereinafter referred to as ME8FET) can be roughly divided into two types as shown below. '] ・la) Electrodes and a passivation film necessary for PET are formed on the surface of Ga As sea urchin/'- with a thickness of 400 to 500 μm, and then the thickness is reduced to about !>tSO μm by mechanical polishing.
（ｂ） 機械的研摩により１５０μｍ 程度まで薄七
°した後、ケミカルエツチングによシ３ｏ〜５０′μｍ
程度までさらに薄くする。但し、ペレットの機械的強度
を補強するため、゛例えばＡｕあるいはＡｇなどをメッ
キし、最終的なベレットあ厚さをｌＯＯμｍ程度とする
。 ゛ □（ａ）の構造の特徴は、利点とし
てペレットマウン４，５７デイ７夛時。、変化１強く、
６ツｙｈｌ’ラツク、電極あるいは゛パッシベーション
膜層基板との剥れを抑えたり、残留応力低減を図れるが
、欠蕉と１では熱伝導の゛低いＧ ａ Ａ ｓの基板の
厚さが厚い′ｆｃｈ臓抵抗及高゛くなることである。一
方、（ｂ）“の゛構造の特徴ば、利点゛としてＧ ａ
Ａ ｓの基板の′−さが薄い元め熱抵抗低減を図れるが
、゛欠点としてはＧａＡｓとマウ′ント扇゛ソルダー！
’ Ｇ’ａ’Ａ ｓと裏ｉメッために加熱処理時にベレ
ットの「反シ」が大きくなシ易いことである。(b) After being thinned to a thickness of about 150 μm by mechanical polishing, it is etched by chemical etching to a thickness of 30 to 50 μm.
Make it even thinner to a certain extent. However, in order to reinforce the mechanical strength of the pellet, it is plated with, for example, Au or Ag, so that the final pellet thickness is about 100 μm.゛ □The structure of (a) has the advantage of having a pellet mount of 4,57 days and 7 times. , change 1 strongly,
6. Easy to use, it is possible to suppress peeling from the electrode or passivation film layer substrate and reduce residual stress, but in 1 and 1, the thickness of the GaAs substrate, which has low thermal conductivity, is thick. 'fch visceral resistance increases. On the other hand, in (b) "characteristics of the structure", Ga
As the As substrate is thin, it can reduce thermal resistance, but the disadvantage is that it requires GaAs and mounting fan solder.
Because of the ``G'a'As'' and lining, the ``reverse'' of the pellet tends to become large during heat treatment.
（発明が解決しようとする問題点）
高出力ＧａＡｓＭＥＳＦＥＴの性能向上を図る上で、熱
抵抗低減は重要な要素であシ、ベレットの厚さを薄くす
ることが最も効果を発揮する。一方。(Problems to be Solved by the Invention) Reducing thermal resistance is an important element in improving the performance of high-power GaAs MESFETs, and reducing the thickness of the pellet is most effective. on the other hand.
ベレットの厚さを薄くすると、加熱処理時にベレットの
１反）」が太きくなシ、その結果ベレットクラック、電
極あるいはパッシベーション膜と基板との剥れ、残留応
力などの原因とな如、ＰＥＴの特性、信頼度に支障を来
たす。If the thickness of the pellet is made thinner, the thickness of the pellet (1 roll) will not be as thick during heat treatment, which may cause pellet cracks, peeling of the electrode or passivation film from the substrate, residual stress, etc. The characteristics and reliability will be affected.
本発明の目的は、ベレットの厚さに関し相反する事象で
ある熱抵抗低減とベレットのｒ反シ」の抑制を同時に改
善した半導体装置を提案するものである。An object of the present invention is to propose a semiconductor device that simultaneously improves the reduction in thermal resistance and the suppression of the r-reflection of the pellet, which are contradictory phenomena related to the thickness of the pellet.
（問題点を解決するだめの手段）
本発明によれば、能動領域直下の半導体基板の厚さをそ
の周辺部よシ薄くなるように半導体基板裏面に窪み部を
有し、この窪み部に金属を充填した半導体装置を得る。(Means for Solving the Problem) According to the present invention, a recess is provided on the back surface of the semiconductor substrate so that the thickness of the semiconductor substrate directly under the active region is thinner than that of the surrounding area, and the recess is filled with metal. A semiconductor device filled with is obtained.
（実施例） 次に、図面を参照して本発明をより詳細に説明する。(Example) Next, the present invention will be explained in more detail with reference to the drawings.
Ｎ個のゲート電極が同一半導体基板上で接続された高出
力ＧａＡｓ ＭＥ８ＦＥＴの熱抵抗几＋ｈは実験的に次
式で示すことができる。The thermal resistance +h of a high-power GaAs ME8FET in which N gate electrodes are connected on the same semiconductor substrate can be experimentally expressed by the following equation.
・・・・・・＋１）
ここで、Ｚは単位ゲート幅、Ｌｓｄはソース及びドレイ
ンオーミック電極間距離、Ｂはソース及びドレイン電極
幅、にはＧ ａ Ａ ｓの熱伝導率、ａはＧａＡｓの厚
みである。・・・・・・+1) Here, Z is the unit gate width, Lsd is the distance between the source and drain ohmic electrodes, B is the source and drain electrode width, is the thermal conductivity of GaAs, and a is the thermal conductivity of GaAs. It is thick.
また、ベレットの「反り」を表わす量として、第２図に
示す様にベレット２０の中心から、Ｘの距離にある点の
「反）」による変位量ｙを用いると、変位量ｙは次式で
示すことができる。Furthermore, if we use the amount of displacement y due to the "curvature" of a point located at a distance of X from the center of the pellet 20 as shown in Figure 2 as the amount representing the "warpage" of the pellet, then the displacement y can be calculated using the following formula: It can be shown as
（０≦Ｘ≦ｅ） ここでＷは加熱処理時にベレット２０に加わる力。(0≦X≦e) Here, W is the force applied to the pellet 20 during the heat treatment.
ＥはＧａＡｓのヤング率、ｂはベレットの幅、ｅはベレ
ット２０の長さである。（１］式より、熱抵抗低減を図
るためにはペレッ）２０の厚さを薄くスることが有効で
あるが、（２）式よシ、ペレッ）２０の厚さを薄くする
と、ベレン）２０のｒ反シ」は著しく大きくなることが
判る。この様にベレット２０の厚さに関し、熱抵抗低減
とベレッ）２０の「反シ」の抑制は相反する事象であシ
、一般には同時に改善されない。E is the Young's modulus of GaAs, b is the width of the pellet, and e is the length of the pellet 20. From equation (1), it is effective to reduce the thickness of Pellet 20 in order to reduce the thermal resistance, but according to equation (2), reducing the thickness of Pellet 20 results in lower thermal resistance. It can be seen that the value of 20 becomes significantly large. As described above, regarding the thickness of the beret 20, reducing the thermal resistance and suppressing the "reflection" of the beret 20 are contradictory phenomena, and are generally not improved at the same time.
ペレット内における熱の発生領域は第３図に示す様に、
ソース電極３２．ゲート電極３３．ドレイン電極３４が
集まっているＰＥＴの能動領域３５であシ、この能動領
域で発生した熱の放熱は、図中点線で示すように、主ｊ
ＣＧ ａ Ａ ｓ基板３１を伝わって行なわれるため、
熱の伝導領域は、はぼ能動領域３５の直下と考えられる
。よって、能動領域３５の直下のＧ ａ Ａ ｓ基板３
１の厚さを薄くし、残る領域のＧ ａ Ａ ｓ基板３１
の厚さを厚くすることによシ、熱抵抗低減及びベレット
の１反）」を抑制できる。The heat generation area within the pellet is shown in Figure 3.
Source electrode 32. Gate electrode 33. In the active region 35 of PET where the drain electrode 34 is gathered, the heat generated in this active region is mainly radiated as shown by the dotted line in the figure.
Since it is carried out through the CG a As substrate 31,
The heat conduction area is considered to be directly below the active area 35. Therefore, the GaAs substrate 3 directly below the active region 35
1 is thinned and the remaining area of the GaAs substrate 31 is
By increasing the thickness of the steel plate, it is possible to reduce the thermal resistance and suppress the occurrence of the bullet damage.
第１図に本発明によるＰＥＴの基板の構造の一例を示す
。Ｇ ａ Ａ ｓ基板ｌの能動領域３の直下の厚さを薄
くシ、その周囲の厚さを厚くするように、ＧａＡｓ基板
１の裏面には窪みが設けられている。FIG. 1 shows an example of the structure of a PET substrate according to the present invention. A recess is provided on the back surface of the GaAs substrate 1 so that the thickness immediately below the active region 3 of the GaAs substrate 1 is thinned and the thickness around it is thickened.
この結果、Ｇ ａ Ａ ｓ基板ｌの断面形状は凹型とな
っている。ここで、凹型形状は、ＧａＡｓ基板１を貫通
するような溝とするのではなく、四辺の周囲が厚くなる
「くぼみ」状とする必要がある。これは凹部への応力の
集中を避けるためである。その後、凹領域１２．Ａｕあ
るいはＡｇの選択メッキによって金属２を充填し、裏面
の平坦化を行っている。As a result, the cross-sectional shape of the GaAs substrate l is concave. Here, the concave shape should not be a groove penetrating the GaAs substrate 1, but a "concave" shape with thicker peripheries on all four sides. This is to avoid concentration of stress on the recess. After that, the recessed area 12. The metal 2 is filled by selective plating of Au or Ag, and the back surface is flattened.
この金属２によって、能動領域３からの放熱特性、は改
善され、機械的強度も保たれる。又能動領域３は薄いの
でここでの発熱による基板の「反シ」も少ない。This metal 2 improves the heat dissipation characteristics from the active region 3 and maintains mechanical strength. Furthermore, since the active region 3 is thin, there is little "reflection" of the substrate due to heat generation here.
（発明の効果）
本発明による半導体装置は、特に高出力Ｇ ａ Ａ ｓ
ＭＥＳＦ’ＥＴにおける熱抵抗低減、及びベレットクラ
ック、電極やパッシベーション膜と基板との剥れ、残留
応力などの原因となるペレットマウント。(Effects of the Invention) The semiconductor device according to the present invention has a particularly high output GaAs
Pellet mounting reduces thermal resistance in MESF'ET, and causes pellet cracks, peeling of electrodes and passivation films from substrates, and residual stress.
ボンディング時の加熱処理によるペレットの「反り」抑
制に寄与でき、高出力ＧａＡｓＭＥ８ＦＥＴの特性、信
頼度の向上を図ることができる。This can contribute to suppressing the "warping" of the pellets caused by heat treatment during bonding, and can improve the characteristics and reliability of high-output GaAsME8FETs.
第１図（ａｌ、 ｌｂ）、 （Ｃ）は本発明の一実施例
に用いる半導体基板の平面図およびそれぞれの側面から
の断面図である。第２図は半導体基板のｒ反シ」を説明
する図、第３図は従来の半導体装置の放熱特性を示す断
面図である。
ｌ、３１・・・・・・Ｇ ａ Ａ ｓ基板、２・・・・
・・金属、３゜３５・・・・・・能動領域、２０・・・
・・・ペレット、３２・・・・・・ソース電極、３３・
・・・・・ゲート電極、３４・・・・・・ドレイン電極
７一FIGS. 1 (al, lb) and (C) are a plan view and a cross-sectional view from each side of a semiconductor substrate used in an embodiment of the present invention. FIG. 2 is a diagram illustrating the r-reflection of a semiconductor substrate, and FIG. 3 is a sectional view showing the heat dissipation characteristics of a conventional semiconductor device. l, 31...G a As substrate, 2...
...Metal, 3゜35...Active area, 20...
... Pellet, 32 ... Source electrode, 33.
...Gate electrode, 34...Drain electrode 7-
Claims (1)
くなるように前記半導体基板に窪み部を有し、該窪み部
に金属を充填したことを特徴とする半導体装置。1. A semiconductor device, characterized in that the semiconductor substrate has a recessed portion so that the thickness of the semiconductor substrate immediately below the active region is thinner than the surrounding region, and the recessed portion is filled with metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14468884A JPS6123350A (en) | 1984-07-12 | 1984-07-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14468884A JPS6123350A (en) | 1984-07-12 | 1984-07-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6123350A true JPS6123350A (en) | 1986-01-31 |
Family
ID=15367944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14468884A Pending JPS6123350A (en) | 1984-07-12 | 1984-07-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123350A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200641A (en) * | 1990-10-04 | 1993-04-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device structure including bending-resistant radiating layer |
| US5338967A (en) * | 1993-01-12 | 1994-08-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device structure with plated heat sink and supporting substrate |
| US5438212A (en) * | 1993-02-25 | 1995-08-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with heat dissipation structure |
| US6316827B1 (en) | 1997-09-12 | 2001-11-13 | Nec Corporation | Semiconductor device having improved temperature distribution |
| US7504707B2 (en) | 2003-06-05 | 2009-03-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| JP2010098251A (en) * | 2008-10-20 | 2010-04-30 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
-
1984
- 1984-07-12 JP JP14468884A patent/JPS6123350A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200641A (en) * | 1990-10-04 | 1993-04-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device structure including bending-resistant radiating layer |
| US5338967A (en) * | 1993-01-12 | 1994-08-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device structure with plated heat sink and supporting substrate |
| US5770468A (en) * | 1993-01-12 | 1998-06-23 | Mitsubishi Denki Kabushiki Kaisha | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere |
| US5438212A (en) * | 1993-02-25 | 1995-08-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with heat dissipation structure |
| US6316827B1 (en) | 1997-09-12 | 2001-11-13 | Nec Corporation | Semiconductor device having improved temperature distribution |
| US7504707B2 (en) | 2003-06-05 | 2009-03-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US7629226B2 (en) | 2003-06-05 | 2009-12-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| JP2010098251A (en) * | 2008-10-20 | 2010-04-30 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
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